Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+7 -1

drivers/gpu/drm/exynos/exynos_drm_encoder.c

··· 226 226 * already updated or not by exynos_drm_encoder_dpms function. 227 227 */ 228 228 exynos_encoder->updated = true; 229 + 230 + /* 231 + * In case of setcrtc, there is no way to update encoder's dpms 232 + * so update it here. 233 + */ 234 + exynos_encoder->dpms = DRM_MODE_DPMS_ON; 229 235 } 230 236 231 237 static void exynos_drm_encoder_disable(struct drm_encoder *encoder) ··· 513 507 * because the setting for disabling the overlay will be updated 514 508 * at vsync. 515 509 */ 516 - if (overlay_ops->wait_for_vblank) 510 + if (overlay_ops && overlay_ops->wait_for_vblank) 517 511 overlay_ops->wait_for_vblank(manager->dev); 518 512 }

+2 -1

drivers/gpu/drm/exynos/exynos_drm_fbdev.c

··· 87 87 88 88 dev->mode_config.fb_base = (resource_size_t)buffer->dma_addr; 89 89 fbi->screen_base = buffer->kvaddr + offset; 90 - fbi->fix.smem_start = (unsigned long)(buffer->dma_addr + offset); 90 + fbi->fix.smem_start = (unsigned long)(page_to_phys(buffer->pages[0]) + 91 + offset); 91 92 fbi->screen_size = size; 92 93 fbi->fix.smem_len = size; 93 94

+2 -2

drivers/gpu/drm/exynos/exynos_drm_fimd.c

··· 61 61 unsigned int timing_base; 62 62 }; 63 63 64 - struct fimd_driver_data exynos4_fimd_driver_data = { 64 + static struct fimd_driver_data exynos4_fimd_driver_data = { 65 65 .timing_base = 0x0, 66 66 }; 67 67 68 - struct fimd_driver_data exynos5_fimd_driver_data = { 68 + static struct fimd_driver_data exynos5_fimd_driver_data = { 69 69 .timing_base = 0x20000, 70 70 }; 71 71

-1

drivers/gpu/drm/exynos/exynos_drm_plane.c

··· 204 204 return ret; 205 205 206 206 plane->crtc = crtc; 207 - plane->fb = crtc->fb; 208 207 209 208 exynos_plane_commit(plane); 210 209 exynos_plane_dpms(plane, DRM_MODE_DPMS_ON);

+2 -9

drivers/gpu/drm/i915/intel_bios.c

··· 499 499 500 500 edp = find_section(bdb, BDB_EDP); 501 501 if (!edp) { 502 - if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) { 503 - DRM_DEBUG_KMS("No eDP BDB found but eDP panel " 504 - "supported, assume %dbpp panel color " 505 - "depth.\n", 506 - dev_priv->edp.bpp); 507 - } 502 + if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) 503 + DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n"); 508 504 return; 509 505 } 510 506 ··· 653 657 dev_priv->lvds_use_ssc = 1; 654 658 dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1); 655 659 DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq); 656 - 657 - /* eDP data */ 658 - dev_priv->edp.bpp = 18; 659 660 } 660 661 661 662 static int __init intel_no_opregion_vbt_callback(const struct dmi_system_id *id)

+1 -1

drivers/gpu/drm/i915/intel_display.c

··· 3845 3845 /* Use VBT settings if we have an eDP panel */ 3846 3846 unsigned int edp_bpc = dev_priv->edp.bpp / 3; 3847 3847 3848 - if (edp_bpc < display_bpc) { 3848 + if (edp_bpc && edp_bpc < display_bpc) { 3849 3849 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); 3850 3850 display_bpc = edp_bpc; 3851 3851 }

+3 -9

drivers/gpu/drm/i915/intel_pm.c

··· 2373 2373 if (i915_enable_rc6 >= 0) 2374 2374 return i915_enable_rc6; 2375 2375 2376 - if (INTEL_INFO(dev)->gen == 5) { 2377 - #ifdef CONFIG_INTEL_IOMMU 2378 - /* Disable rc6 on ilk if VT-d is on. */ 2379 - if (intel_iommu_gfx_mapped) 2380 - return false; 2381 - #endif 2382 - DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n"); 2383 - return INTEL_RC6_ENABLE; 2384 - } 2376 + /* Disable RC6 on Ironlake */ 2377 + if (INTEL_INFO(dev)->gen == 5) 2378 + return 0; 2385 2379 2386 2380 if (IS_HASWELL(dev)) { 2387 2381 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");

+10 -7

drivers/gpu/drm/i915/intel_sdvo.c

··· 2201 2201 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2202 2202 intel_sdvo->is_hdmi = true; 2203 2203 } 2204 - intel_sdvo->base.cloneable = true; 2205 2204 2206 2205 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2207 2206 if (intel_sdvo->is_hdmi) ··· 2231 2232 2232 2233 intel_sdvo->is_tv = true; 2233 2234 intel_sdvo->base.needs_tv_clock = true; 2234 - intel_sdvo->base.cloneable = false; 2235 2235 2236 2236 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2237 2237 ··· 2273 2275 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2274 2276 } 2275 2277 2276 - intel_sdvo->base.cloneable = true; 2277 - 2278 2278 intel_sdvo_connector_init(intel_sdvo_connector, 2279 2279 intel_sdvo); 2280 2280 return true; ··· 2302 2306 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2303 2307 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2304 2308 } 2305 - 2306 - /* SDVO LVDS is not cloneable because the input mode gets adjusted by the encoder */ 2307 - intel_sdvo->base.cloneable = false; 2308 2309 2309 2310 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2310 2311 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) ··· 2713 2720 /* Output_setup can leave behind connectors! */ 2714 2721 goto err_output; 2715 2722 } 2723 + 2724 + /* 2725 + * Cloning SDVO with anything is often impossible, since the SDVO 2726 + * encoder can request a special input timing mode. And even if that's 2727 + * not the case we have evidence that cloning a plain unscaled mode with 2728 + * VGA doesn't really work. Furthermore the cloning flags are way too 2729 + * simplistic anyway to express such constraints, so just give up on 2730 + * cloning for SDVO encoders. 2731 + */ 2732 + intel_sdvo->base.cloneable = false; 2716 2733 2717 2734 /* Only enable the hotplug irq if we need it, to work around noisy 2718 2735 * hotplug lines.

+14 -34

drivers/gpu/drm/radeon/atombios_crtc.c

··· 1696 1696 return ATOM_PPLL2; 1697 1697 DRM_ERROR("unable to allocate a PPLL\n"); 1698 1698 return ATOM_PPLL_INVALID; 1699 - } else if (ASIC_IS_AVIVO(rdev)) { 1700 - /* in DP mode, the DP ref clock can come from either PPLL 1701 - * depending on the asic: 1702 - * DCE3: PPLL1 or PPLL2 1703 - */ 1704 - if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1705 - /* use the same PPLL for all DP monitors */ 1706 - pll = radeon_get_shared_dp_ppll(crtc); 1707 - if (pll != ATOM_PPLL_INVALID) 1708 - return pll; 1709 - } else { 1710 - /* use the same PPLL for all monitors with the same clock */ 1711 - pll = radeon_get_shared_nondp_ppll(crtc); 1712 - if (pll != ATOM_PPLL_INVALID) 1713 - return pll; 1714 - } 1715 - /* all other cases */ 1716 - pll_in_use = radeon_get_pll_use_mask(crtc); 1717 - /* the order shouldn't matter here, but we probably 1718 - * need this until we have atomic modeset 1719 - */ 1720 - if (rdev->flags & RADEON_IS_IGP) { 1721 - if (!(pll_in_use & (1 << ATOM_PPLL1))) 1722 - return ATOM_PPLL1; 1723 - if (!(pll_in_use & (1 << ATOM_PPLL2))) 1724 - return ATOM_PPLL2; 1725 - } else { 1726 - if (!(pll_in_use & (1 << ATOM_PPLL2))) 1727 - return ATOM_PPLL2; 1728 - if (!(pll_in_use & (1 << ATOM_PPLL1))) 1729 - return ATOM_PPLL1; 1730 - } 1731 - DRM_ERROR("unable to allocate a PPLL\n"); 1732 - return ATOM_PPLL_INVALID; 1733 1699 } else { 1734 1700 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1701 + /* some atombios (observed in some DCE2/DCE3) code have a bug, 1702 + * the matching btw pll and crtc is done through 1703 + * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1704 + * pll (1 or 2) to select which register to write. ie if using 1705 + * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1706 + * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1707 + * choose which value to write. Which is reverse order from 1708 + * register logic. So only case that works is when pllid is 1709 + * same as crtcid or when both pll and crtc are enabled and 1710 + * both use same clock. 1711 + * 1712 + * So just return crtc id as if crtc and pll were hard linked 1713 + * together even if they aren't 1714 + */ 1735 1715 return radeon_crtc->crtc_id; 1736 1716 } 1737 1717 }

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