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drm/amdgpu: Return EINVAL if no PT BO

This change is also useful for the upcoming changes where page tables
can be updated by CPU.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Harish Kasiviswanathan and committed by
Alex Deucher cc28c4ed 92456b93

+30 -18
+30 -18
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 1187 1187 * @flags: mapping flags 1188 1188 * 1189 1189 * Update the page tables in the range @start - @end. 1190 + * Returns 0 for success, -EINVAL for failure. 1190 1191 */ 1191 - static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 1192 + static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 1192 1193 uint64_t start, uint64_t end, 1193 1194 uint64_t dst, uint64_t flags) 1194 1195 { ··· 1207 1206 pt = amdgpu_vm_get_pt(params, addr); 1208 1207 if (!pt) { 1209 1208 pr_err("PT not found, aborting update_ptes\n"); 1210 - return; 1209 + return -EINVAL; 1211 1210 } 1212 1211 1213 1212 if (params->shadow) { 1214 1213 if (!pt->shadow) 1215 - return; 1214 + return 0; 1216 1215 pt = pt->shadow; 1217 1216 } 1218 1217 if ((addr & ~mask) == (end & ~mask)) ··· 1234 1233 pt = amdgpu_vm_get_pt(params, addr); 1235 1234 if (!pt) { 1236 1235 pr_err("PT not found, aborting update_ptes\n"); 1237 - return; 1236 + return -EINVAL; 1238 1237 } 1239 1238 1240 1239 if (params->shadow) { 1241 1240 if (!pt->shadow) 1242 - return; 1241 + return 0; 1243 1242 pt = pt->shadow; 1244 1243 } 1245 1244 ··· 1274 1273 1275 1274 params->func(params, cur_pe_start, cur_dst, cur_nptes, 1276 1275 AMDGPU_GPU_PAGE_SIZE, flags); 1276 + 1277 + return 0; 1277 1278 } 1278 1279 1279 1280 /* ··· 1287 1284 * @end: last PTE to handle 1288 1285 * @dst: addr those PTEs should point to 1289 1286 * @flags: hw mapping flags 1287 + * Returns 0 for success, -EINVAL for failure. 1290 1288 */ 1291 - static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, 1289 + static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, 1292 1290 uint64_t start, uint64_t end, 1293 1291 uint64_t dst, uint64_t flags) 1294 1292 { 1293 + int r; 1294 + 1295 1295 /** 1296 1296 * The MC L1 TLB supports variable sized pages, based on a fragment 1297 1297 * field in the PTE. When this field is set to a non-zero value, page ··· 1323 1317 1324 1318 /* system pages are non continuously */ 1325 1319 if (params->src || !(flags & AMDGPU_PTE_VALID) || 1326 - (frag_start >= frag_end)) { 1327 - 1328 - amdgpu_vm_update_ptes(params, start, end, dst, flags); 1329 - return; 1330 - } 1320 + (frag_start >= frag_end)) 1321 + return amdgpu_vm_update_ptes(params, start, end, dst, flags); 1331 1322 1332 1323 /* handle the 4K area at the beginning */ 1333 1324 if (start != frag_start) { 1334 - amdgpu_vm_update_ptes(params, start, frag_start, 1335 - dst, flags); 1325 + r = amdgpu_vm_update_ptes(params, start, frag_start, 1326 + dst, flags); 1327 + if (r) 1328 + return r; 1336 1329 dst += (frag_start - start) * AMDGPU_GPU_PAGE_SIZE; 1337 1330 } 1338 1331 1339 1332 /* handle the area in the middle */ 1340 - amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, 1341 - flags | frag_flags); 1333 + r = amdgpu_vm_update_ptes(params, frag_start, frag_end, dst, 1334 + flags | frag_flags); 1335 + if (r) 1336 + return r; 1342 1337 1343 1338 /* handle the 4K area at the end */ 1344 1339 if (frag_end != end) { 1345 1340 dst += (frag_end - frag_start) * AMDGPU_GPU_PAGE_SIZE; 1346 - amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); 1341 + r = amdgpu_vm_update_ptes(params, frag_end, end, dst, flags); 1347 1342 } 1343 + return r; 1348 1344 } 1349 1345 1350 1346 /** ··· 1467 1459 goto error_free; 1468 1460 1469 1461 params.shadow = true; 1470 - amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags); 1462 + r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags); 1463 + if (r) 1464 + goto error_free; 1471 1465 params.shadow = false; 1472 - amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags); 1466 + r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags); 1467 + if (r) 1468 + goto error_free; 1473 1469 1474 1470 amdgpu_ring_pad_ib(ring, params.ib); 1475 1471 WARN_ON(params.ib->length_dw > ndw);