tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
"About the usual for this stage, bunch of amdgpu, a few i915 and a
scattering of fixes across the board"

dsc:
- macro fixes

simplefb:
- fix VESA format

scheduler:
- timeout handling fix

fbdev:
- avoid potential out-of-bounds access in generic fbdev emulation

ast:
- improve AST2500+ compat on ARM

mipi-dsi:
- small mipi-dsi fix

amdgpu:
- VCN3 fixes
- APUs always support PCI atomics
- legacy power management fixes
- DCN 3.1.4 fix
- DCFCLK fix
- fix several RAS irq refcount mismatches
- GPU Reset fix
- GFX 11.0.4 fix

i915:
- taint kernel when force_probe is used
- NULL deref and div-by-zero fixes for display
- GuC error capture fix for Xe devices"

* tag 'drm-fixes-2023-05-12' of git://anongit.freedesktop.org/drm/drm: (24 commits)
drm/amdgpu: change gfx 11.0.4 external_id range
drm/amdgpu/jpeg: Remove harvest checking for JPEG3
drm/amdgpu/gfx: disable gfx9 cp_ecc_error_irq only when enabling legacy gfx ras
drm/amd/pm: avoid potential UBSAN issue on legacy asics
drm/i915: taint kernel when force probing unsupported devices
drm/i915/dp: prevent potential div-by-zero
drm/i915: Fix NULL ptr deref by checking new_crtc_state
drm/i915/guc: Don't capture Gen8 regs on Xe devices
drm/amdgpu: disable sdma ecc irq only when sdma RAS is enabled in suspend
drm/amdgpu: Fix vram recover doesn't work after whole GPU reset (v2)
drm/amdgpu: drop gfx_v11_0_cp_ecc_error_irq_funcs
drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
drm/amd/display: Add symclk workaround during disable link output
drm/amd/pm: parse pp_handle under appropriate conditions
drm/amdgpu: set gfx9 onwards APU atomics support to be true
drm/amdgpu/nv: update VCN 3 max HEVC encoding resolution
drm/sched: Check scheduler work queue before calling timeout handling
drm/mipi-dsi: Set the fwnode for mipi_dsi_device
drm/nouveau/disp: More DP_RECEIVER_CAP_SIZE array fixes
drm/dsc: fix DP_DSC_MAX_BPP_DELTA_* macro values
...

Linus Torvalds cc3c44c9 849a4f09

+188 -100
+3 -1
drivers/firmware/sysfb_simplefb.c
··· 51 51 * 52 52 * It's not easily possible to fix this in struct screen_info, 53 53 * as this could break UAPI. The best solution is to compute 54 - * bits_per_pixel here and ignore lfb_depth. In the loop below, 54 + * bits_per_pixel from the color bits, reserved bits and 55 + * reported lfb_depth, whichever is highest. In the loop below, 55 56 * ignore simplefb formats with alpha bits, as EFI and VESA 56 57 * don't specify alpha channels. 57 58 */ ··· 61 60 si->green_size + si->green_pos, 62 61 si->blue_size + si->blue_pos), 63 62 si->rsvd_size + si->rsvd_pos); 63 + bits_per_pixel = max_t(u32, bits_per_pixel, si->lfb_depth); 64 64 } else { 65 65 bits_per_pixel = si->lfb_depth; 66 66 }
+11 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 3757 3757 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *) 3758 3758 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags == 3759 3759 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64); 3760 + /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a 3761 + * internal path natively support atomics, set have_atomics_support to true. 3762 + */ 3763 + else if ((adev->flags & AMD_IS_APU) && 3764 + (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))) 3765 + adev->have_atomics_support = true; 3760 3766 else 3761 3767 adev->have_atomics_support = 3762 3768 !pci_enable_atomic_ops_to_root(adev->pdev, ··· 4512 4506 dev_info(adev->dev, "recover vram bo from shadow start\n"); 4513 4507 mutex_lock(&adev->shadow_list_lock); 4514 4508 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { 4515 - shadow = &vmbo->bo; 4509 + /* If vm is compute context or adev is APU, shadow will be NULL */ 4510 + if (!vmbo->shadow) 4511 + continue; 4512 + shadow = vmbo->shadow; 4513 + 4516 4514 /* No need to recover an evicted BO */ 4517 4515 if (shadow->tbo.resource->mem_type != TTM_PL_TT || 4518 4516 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
+5 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 687 687 if (r) 688 688 return r; 689 689 690 - r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 691 - if (r) 692 - goto late_fini; 690 + if (adev->gfx.cp_ecc_error_irq.funcs) { 691 + r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 692 + if (r) 693 + goto late_fini; 694 + } 693 695 } else { 694 696 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 695 697 }
-46
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 1315 1315 if (r) 1316 1316 return r; 1317 1317 1318 - /* ECC error */ 1319 - r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP, 1320 - GFX_11_0_0__SRCID__CP_ECC_ERROR, 1321 - &adev->gfx.cp_ecc_error_irq); 1322 - if (r) 1323 - return r; 1324 - 1325 1318 /* FED error */ 1326 1319 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1327 1320 GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT, ··· 4437 4444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4438 4445 int r; 4439 4446 4440 - amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 4441 4447 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4442 4448 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4443 4449 ··· 5889 5897 } 5890 5898 } 5891 5899 5892 - #define CP_ME1_PIPE_INST_ADDR_INTERVAL 0x1 5893 - #define SET_ECC_ME_PIPE_STATE(reg_addr, state) \ 5894 - do { \ 5895 - uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \ 5896 - tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \ 5897 - WREG32_SOC15_IP(GC, reg_addr, tmp); \ 5898 - } while (0) 5899 - 5900 - static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5901 - struct amdgpu_irq_src *source, 5902 - unsigned type, 5903 - enum amdgpu_interrupt_state state) 5904 - { 5905 - uint32_t ecc_irq_state = 0; 5906 - uint32_t pipe0_int_cntl_addr = 0; 5907 - int i = 0; 5908 - 5909 - ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0; 5910 - 5911 - pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); 5912 - 5913 - WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state); 5914 - 5915 - for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) 5916 - SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL, 5917 - ecc_irq_state); 5918 - 5919 - return 0; 5920 - } 5921 - 5922 5900 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5923 5901 struct amdgpu_irq_src *src, 5924 5902 unsigned type, ··· 6303 6341 .process = gfx_v11_0_priv_inst_irq, 6304 6342 }; 6305 6343 6306 - static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = { 6307 - .set = gfx_v11_0_set_cp_ecc_error_state, 6308 - .process = amdgpu_gfx_cp_ecc_error_irq, 6309 - }; 6310 - 6311 6344 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = { 6312 6345 .process = gfx_v11_0_rlc_gc_fed_irq, 6313 6346 }; ··· 6317 6360 6318 6361 adev->gfx.priv_inst_irq.num_types = 1; 6319 6362 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs; 6320 - 6321 - adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */ 6322 - adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs; 6323 6363 6324 6364 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ 6325 6365 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
+2 -1
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 3764 3764 { 3765 3765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3766 3766 3767 - amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3767 + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 3768 + amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3768 3769 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3769 3770 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3770 3771
+1
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
··· 54 54 55 55 switch (adev->ip_versions[UVD_HWIP][0]) { 56 56 case IP_VERSION(3, 1, 1): 57 + case IP_VERSION(3, 1, 2): 57 58 break; 58 59 default: 59 60 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+16 -6
drivers/gpu/drm/amd/amdgpu/nv.c
··· 98 98 }; 99 99 100 100 /* Sienna Cichlid */ 101 + static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 102 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 103 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 104 + }; 105 + 106 + static const struct amdgpu_video_codecs sc_video_codecs_encode = { 107 + .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 108 + .codec_array = sc_video_codecs_encode_array, 109 + }; 110 + 101 111 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = 102 112 { 103 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, ··· 146 136 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 147 137 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 148 138 { 149 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 150 - {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 139 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2160, 0)}, 140 + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 4352, 0)}, 151 141 }; 152 142 153 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = ··· 247 237 } else { 248 238 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 249 239 if (encode) 250 - *codecs = &nv_video_codecs_encode; 240 + *codecs = &sc_video_codecs_encode; 251 241 else 252 242 *codecs = &sc_video_codecs_decode_vcn1; 253 243 } else { 254 244 if (encode) 255 - *codecs = &nv_video_codecs_encode; 245 + *codecs = &sc_video_codecs_encode; 256 246 else 257 247 *codecs = &sc_video_codecs_decode_vcn0; 258 248 } ··· 261 251 case IP_VERSION(3, 0, 16): 262 252 case IP_VERSION(3, 0, 2): 263 253 if (encode) 264 - *codecs = &nv_video_codecs_encode; 254 + *codecs = &sc_video_codecs_encode; 265 255 else 266 256 *codecs = &sc_video_codecs_decode_vcn0; 267 257 return 0; 268 258 case IP_VERSION(3, 1, 1): 269 259 case IP_VERSION(3, 1, 2): 270 260 if (encode) 271 - *codecs = &nv_video_codecs_encode; 261 + *codecs = &sc_video_codecs_encode; 272 262 else 273 263 *codecs = &yc_video_codecs_decode; 274 264 return 0;
+5 -3
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 1917 1917 return 0; 1918 1918 } 1919 1919 1920 - for (i = 0; i < adev->sdma.num_instances; i++) { 1921 - amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1922 - AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1920 + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) { 1921 + for (i = 0; i < adev->sdma.num_instances; i++) { 1922 + amdgpu_irq_put(adev, &adev->sdma.ecc_irq, 1923 + AMDGPU_SDMA_IRQ_INSTANCE0 + i); 1924 + } 1923 1925 } 1924 1926 1925 1927 sdma_v4_0_ctx_switch_enable(adev, false);
+1 -1
drivers/gpu/drm/amd/amdgpu/soc21.c
··· 711 711 AMD_PG_SUPPORT_VCN_DPG | 712 712 AMD_PG_SUPPORT_GFX_PG | 713 713 AMD_PG_SUPPORT_JPEG; 714 - adev->external_rev_id = adev->rev_id + 0x1; 714 + adev->external_rev_id = adev->rev_id + 0x80; 715 715 break; 716 716 717 717 default:
+65
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
··· 423 423 424 424 PERF_TRACE(); 425 425 } 426 + static void apply_symclk_on_tx_off_wa(struct dc_link *link) 427 + { 428 + /* There are use cases where SYMCLK is referenced by OTG. For instance 429 + * for TMDS signal, OTG relies SYMCLK even if TX video output is off. 430 + * However current link interface will power off PHY when disabling link 431 + * output. This will turn off SYMCLK generated by PHY. The workaround is 432 + * to identify such case where SYMCLK is still in use by OTG when we 433 + * power off PHY. When this is detected, we will temporarily power PHY 434 + * back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling 435 + * program_pix_clk interface. When OTG is disabled, we will then power 436 + * off PHY by calling disable link output again. 437 + * 438 + * In future dcn generations, we plan to rework transmitter control 439 + * interface so that we could have an option to set SYMCLK ON TX OFF 440 + * state in one step without this workaround 441 + */ 442 + 443 + struct dc *dc = link->ctx->dc; 444 + struct pipe_ctx *pipe_ctx = NULL; 445 + uint8_t i; 446 + 447 + if (link->phy_state.symclk_ref_cnts.otg > 0) { 448 + for (i = 0; i < MAX_PIPES; i++) { 449 + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 450 + if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { 451 + pipe_ctx->clock_source->funcs->program_pix_clk( 452 + pipe_ctx->clock_source, 453 + &pipe_ctx->stream_res.pix_clk_params, 454 + dc->link_srv->dp_get_encoding_format( 455 + &pipe_ctx->link_config.dp_link_settings), 456 + &pipe_ctx->pll_settings); 457 + link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 458 + break; 459 + } 460 + } 461 + } 462 + } 463 + 464 + void dcn314_disable_link_output(struct dc_link *link, 465 + const struct link_resource *link_res, 466 + enum signal_type signal) 467 + { 468 + struct dc *dc = link->ctx->dc; 469 + const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 470 + struct dmcu *dmcu = dc->res_pool->dmcu; 471 + 472 + if (signal == SIGNAL_TYPE_EDP && 473 + link->dc->hwss.edp_backlight_control) 474 + link->dc->hwss.edp_backlight_control(link, false); 475 + else if (dmcu != NULL && dmcu->funcs->lock_phy) 476 + dmcu->funcs->lock_phy(dmcu); 477 + 478 + link_hwss->disable_link_output(link, link_res, signal); 479 + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 480 + /* 481 + * Add the logic to extract BOTH power up and power down sequences 482 + * from enable/disable link output and only call edp panel control 483 + * in enable_link_dp and disable_link_dp once. 484 + */ 485 + if (dmcu != NULL && dmcu->funcs->lock_phy) 486 + dmcu->funcs->unlock_phy(dmcu); 487 + dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 488 + 489 + apply_symclk_on_tx_off_wa(link); 490 + }
+2
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
··· 45 45 46 46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on); 47 47 48 + void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); 49 + 48 50 #endif /* __DC_HWSS_DCN314_H__ */
+1 -1
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
··· 105 105 .enable_lvds_link_output = dce110_enable_lvds_link_output, 106 106 .enable_tmds_link_output = dce110_enable_tmds_link_output, 107 107 .enable_dp_link_output = dce110_enable_dp_link_output, 108 - .disable_link_output = dce110_disable_link_output, 108 + .disable_link_output = dcn314_disable_link_output, 109 109 .z10_restore = dcn31_z10_restore, 110 110 .z10_save_init = dcn31_z10_save_init, 111 111 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+3 -2
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
··· 810 810 v->SwathHeightY[k], 811 811 v->SwathHeightC[k], 812 812 TWait, 813 - v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ? 813 + (v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ || 814 + v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ? 814 815 mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, 815 816 /* Output */ 816 817 &v->DSTXAfterScaler[k], ··· 3311 3310 v->swath_width_chroma_ub_this_state[k], 3312 3311 v->SwathHeightYThisState[k], 3313 3312 v->SwathHeightCThisState[k], v->TWait, 3314 - v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ? 3313 + (v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ? 3315 3314 mode_lib->vba.ip.min_prefetch_in_strobe_us : 0, 3316 3315 3317 3316 /* Output */
+1
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.h
··· 53 53 #define BPP_BLENDED_PIPE 0xffffffff 54 54 55 55 #define MEM_STROBE_FREQ_MHZ 1600 56 + #define MIN_DCFCLK_FREQ_MHZ 200 56 57 #define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0 57 58 58 59 struct display_mode_lib;
+18 -7
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 36 36 #define amdgpu_dpm_enable_bapm(adev, e) \ 37 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 38 38 39 + #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) 40 + 39 41 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) 40 42 { 41 43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; ··· 1462 1460 1463 1461 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) 1464 1462 { 1465 - struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 1466 - struct smu_context *smu = adev->powerplay.pp_handle; 1463 + if (is_support_sw_smu(adev)) { 1464 + struct smu_context *smu = adev->powerplay.pp_handle; 1467 1465 1468 - if ((is_support_sw_smu(adev) && smu->od_enabled) || 1469 - (is_support_sw_smu(adev) && smu->is_apu) || 1470 - (!is_support_sw_smu(adev) && hwmgr->od_enabled)) 1471 - return true; 1466 + return (smu->od_enabled || smu->is_apu); 1467 + } else { 1468 + struct pp_hwmgr *hwmgr; 1472 1469 1473 - return false; 1470 + /* 1471 + * dpm on some legacy asics don't carry od_enabled member 1472 + * as its pp_handle is casted directly from adev. 1473 + */ 1474 + if (amdgpu_dpm_is_legacy_dpm(adev)) 1475 + return false; 1476 + 1477 + hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; 1478 + 1479 + return hwmgr->od_enabled; 1480 + } 1474 1481 } 1475 1482 1476 1483 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
+5 -4
drivers/gpu/drm/ast/ast_main.c
··· 425 425 return ERR_PTR(-EIO); 426 426 427 427 /* 428 - * If we don't have IO space at all, use MMIO now and 429 - * assume the chip has MMIO enabled by default (rev 0x20 430 - * and higher). 428 + * After AST2500, MMIO is enabled by default, and it should be adopted 429 + * to be compatible with Arm. 431 430 */ 432 - if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { 431 + if (pdev->revision >= 0x40) { 432 + ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 433 + } else if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) { 433 434 drm_info(dev, "platform has no IO space, trying MMIO\n"); 434 435 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 435 436 }
+12 -4
drivers/gpu/drm/drm_fb_helper.c
··· 641 641 static void drm_fb_helper_memory_range_to_clip(struct fb_info *info, off_t off, size_t len, 642 642 struct drm_rect *clip) 643 643 { 644 + u32 line_length = info->fix.line_length; 645 + u32 fb_height = info->var.yres; 644 646 off_t end = off + len; 645 647 u32 x1 = 0; 646 - u32 y1 = off / info->fix.line_length; 648 + u32 y1 = off / line_length; 647 649 u32 x2 = info->var.xres; 648 - u32 y2 = DIV_ROUND_UP(end, info->fix.line_length); 650 + u32 y2 = DIV_ROUND_UP(end, line_length); 651 + 652 + /* Don't allow any of them beyond the bottom bound of display area */ 653 + if (y1 > fb_height) 654 + y1 = fb_height; 655 + if (y2 > fb_height) 656 + y2 = fb_height; 649 657 650 658 if ((y2 - y1) == 1) { 651 659 /* 652 660 * We've only written to a single scanline. Try to reduce 653 661 * the number of horizontal pixels that need an update. 654 662 */ 655 - off_t bit_off = (off % info->fix.line_length) * 8; 656 - off_t bit_end = (end % info->fix.line_length) * 8; 663 + off_t bit_off = (off % line_length) * 8; 664 + off_t bit_end = (end % line_length) * 8; 657 665 658 666 x1 = bit_off / info->var.bits_per_pixel; 659 667 x2 = DIV_ROUND_UP(bit_end, info->var.bits_per_pixel);
+1 -1
drivers/gpu/drm/drm_mipi_dsi.c
··· 221 221 return dsi; 222 222 } 223 223 224 - dsi->dev.of_node = info->node; 224 + device_set_node(&dsi->dev, of_fwnode_handle(info->node)); 225 225 dsi->channel = info->channel; 226 226 strlcpy(dsi->name, info->type, sizeof(dsi->name)); 227 227
+7 -5
drivers/gpu/drm/i915/Kconfig
··· 62 62 This is the default value for the i915.force_probe module 63 63 parameter. Using the module parameter overrides this option. 64 64 65 - Force probe the i915 for Intel graphics devices that are 66 - recognized but not properly supported by this kernel version. It is 67 - recommended to upgrade to a kernel version with proper support as soon 68 - as it is available. 65 + Force probe the i915 driver for Intel graphics devices that are 66 + recognized but not properly supported by this kernel version. Force 67 + probing an unsupported device taints the kernel. It is recommended to 68 + upgrade to a kernel version with proper support as soon as it is 69 + available. 69 70 70 71 It can also be used to block the probe of recognized and fully 71 72 supported devices. ··· 76 75 Use "<pci-id>[,<pci-id>,...]" to force probe the i915 for listed 77 76 devices. For example, "4500" or "4500,4571". 78 77 79 - Use "*" to force probe the driver for all known devices. 78 + Use "*" to force probe the driver for all known devices. Not 79 + recommended. 80 80 81 81 Use "!" right before the ID to block the probe of the device. For 82 82 example, "4500,!4571" forces the probe of 4500 and blocks the probe of
+2 -2
drivers/gpu/drm/i915/display/intel_atomic_plane.c
··· 1028 1028 int ret; 1029 1029 1030 1030 if (old_obj) { 1031 - const struct intel_crtc_state *crtc_state = 1031 + const struct intel_crtc_state *new_crtc_state = 1032 1032 intel_atomic_get_new_crtc_state(state, 1033 1033 to_intel_crtc(old_plane_state->hw.crtc)); 1034 1034 ··· 1043 1043 * This should only fail upon a hung GPU, in which case we 1044 1044 * can safely continue. 1045 1045 */ 1046 - if (intel_crtc_needs_modeset(crtc_state)) { 1046 + if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) { 1047 1047 ret = i915_sw_fence_await_reservation(&state->commit_ready, 1048 1048 old_obj->base.resv, 1049 1049 false, 0,
+5
drivers/gpu/drm/i915/display/intel_dp.c
··· 1601 1601 pipe_config->dsc.slice_count = 1602 1602 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 1603 1603 true); 1604 + if (!pipe_config->dsc.slice_count) { 1605 + drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", 1606 + pipe_config->dsc.slice_count); 1607 + return -EINVAL; 1608 + } 1604 1609 } else { 1605 1610 u16 dsc_max_output_bpp = 0; 1606 1611 u8 dsc_dp_slice_count;
+5 -2
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
··· 31 31 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } 32 32 33 33 #define COMMON_GEN9BASE_GLOBAL \ 34 - { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 35 - { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ 36 34 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ 37 35 { DONE_REG, 0, 0, "DONE_REG" }, \ 38 36 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } 37 + 38 + #define GEN9_GLOBAL \ 39 + { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 40 + { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } 39 41 40 42 #define COMMON_GEN12BASE_GLOBAL \ 41 43 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ ··· 144 142 static const struct __guc_mmio_reg_descr default_global_regs[] = { 145 143 COMMON_BASE_GLOBAL, 146 144 COMMON_GEN9BASE_GLOBAL, 145 + GEN9_GLOBAL, 147 146 }; 148 147 149 148 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
+6
drivers/gpu/drm/i915/i915_pci.c
··· 1344 1344 return -ENODEV; 1345 1345 } 1346 1346 1347 + if (intel_info->require_force_probe) { 1348 + dev_info(&pdev->dev, "Force probing unsupported Device ID %04x, tainting kernel\n", 1349 + pdev->device); 1350 + add_taint(TAINT_USER, LOCKDEP_STILL_OK); 1351 + } 1352 + 1347 1353 /* Only bind to function 0 of the device. Early generations 1348 1354 * used function 1 as a placeholder for multi-head. This causes 1349 1355 * us confusion instead, especially on the systems where both
+3 -1
drivers/gpu/drm/nouveau/include/nvif/if0012.h
··· 2 2 #ifndef __NVIF_IF0012_H__ 3 3 #define __NVIF_IF0012_H__ 4 4 5 + #include <drm/display/drm_dp.h> 6 + 5 7 union nvif_outp_args { 6 8 struct nvif_outp_v0 { 7 9 __u8 version; ··· 65 63 __u8 hda; 66 64 __u8 mst; 67 65 __u8 pad04[4]; 68 - __u8 dpcd[16]; 66 + __u8 dpcd[DP_RECEIVER_CAP_SIZE]; 69 67 } dp; 70 68 }; 71 69 } v0;
+2 -1
drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h
··· 3 3 #define __NVKM_DISP_OUTP_H__ 4 4 #include "priv.h" 5 5 6 + #include <drm/display/drm_dp.h> 6 7 #include <subdev/bios.h> 7 8 #include <subdev/bios/dcb.h> 8 9 #include <subdev/bios/dp.h> ··· 43 42 bool aux_pwr_pu; 44 43 u8 lttpr[6]; 45 44 u8 lttprs; 46 - u8 dpcd[16]; 45 + u8 dpcd[DP_RECEIVER_CAP_SIZE]; 47 46 48 47 struct { 49 48 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */
+1 -1
drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c
··· 146 146 } 147 147 148 148 static int 149 - nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[16], 149 + nvkm_uoutp_mthd_acquire_dp(struct nvkm_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], 150 150 u8 link_nr, u8 link_bw, bool hda, bool mst) 151 151 { 152 152 int ret;
+1 -1
drivers/gpu/drm/scheduler/sched_main.c
··· 309 309 */ 310 310 void drm_sched_fault(struct drm_gpu_scheduler *sched) 311 311 { 312 - if (sched->ready) 312 + if (sched->timeout_wq) 313 313 mod_delayed_work(sched->timeout_wq, &sched->work_tdr, 0); 314 314 } 315 315 EXPORT_SYMBOL(drm_sched_fault);
+2 -3
include/drm/display/drm_dp.h
··· 286 286 287 287 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 288 288 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) 289 - # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 290 - # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 291 - # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 289 + # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */ 290 + # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */ 292 291 293 292 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 294 293 # define DP_DSC_RGB (1 << 0)
+2 -3
include/drm/display/drm_dp_helper.h
··· 181 181 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 182 182 { 183 183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 184 - (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 185 - DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << 186 - DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); 184 + ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 185 + DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 187 186 } 188 187 189 188 static inline u32