Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A collection of small fixes for various SoC vendor clk drivers"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399
clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399
clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399
clk: renesas: r8a7795: Fix SD clocks
clk: rockchip: fix rk3399 aclk_vio gate bit
clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
+14
-12
+5
-4
drivers/clk/renesas/r8a7795-cpg-mssr.c
+5
-4
drivers/clk/renesas/r8a7795-cpg-mssr.c
···
69
69
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
70
70
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
71
71
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
72
+
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72
73
73
74
/* Core Clock Outputs */
74
75
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
···
88
87
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
89
88
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
90
89
91
-
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
92
-
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
93
-
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
94
-
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
90
+
DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x0074),
91
+
DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x0078),
92
+
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x0268),
93
+
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x026c),
95
94
96
95
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
97
96
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
+6
-5
drivers/clk/rockchip/clk-rk3399.c
+6
-5
drivers/clk/rockchip/clk-rk3399.c
···
833
833
834
834
/* perihp */
835
835
GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
836
-
RK3399_CLKGATE_CON(5), 0, GFLAGS),
837
-
GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
838
836
RK3399_CLKGATE_CON(5), 1, GFLAGS),
837
+
GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
838
+
RK3399_CLKGATE_CON(5), 0, GFLAGS),
839
839
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
840
840
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
841
841
RK3399_CLKGATE_CON(5), 2, GFLAGS),
···
923
923
RK3399_CLKGATE_CON(6), 14, GFLAGS),
924
924
925
925
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
926
-
RK3399_CLKGATE_CON(6), 12, GFLAGS),
927
-
GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
928
926
RK3399_CLKGATE_CON(6), 13, GFLAGS),
927
+
GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
928
+
RK3399_CLKGATE_CON(6), 12, GFLAGS),
929
929
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
930
930
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
931
931
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
···
1071
1071
/* vio */
1072
1072
COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1073
1073
RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1074
-
RK3399_CLKGATE_CON(11), 10, GFLAGS),
1074
+
RK3399_CLKGATE_CON(11), 0, GFLAGS),
1075
1075
COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1076
1076
RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1077
1077
RK3399_CLKGATE_CON(11), 1, GFLAGS),
···
1484
1484
"hclk_perilp1",
1485
1485
"hclk_perilp1_noc",
1486
1486
"aclk_dmac0_perilp",
1487
+
"aclk_emmc_noc",
1487
1488
"gpll_hclk_perilp1_src",
1488
1489
"gpll_aclk_perilp0_src",
1489
1490
"gpll_aclk_perihp_src",
+1
-1
drivers/clk/sunxi-ng/ccu_common.c
+1
-1
drivers/clk/sunxi-ng/ccu_common.c
+2
-2
drivers/clk/tegra/clk-tegra114.c
+2
-2
drivers/clk/tegra/clk-tegra114.c
···
428
428
.div_nmp = &pllp_nmp,
429
429
.freq_table = pll_d_freq_table,
430
430
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
431
-
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
431
+
TEGRA_PLL_HAS_LOCK_ENABLE,
432
432
};
433
433
434
434
static struct tegra_clk_pll_params pll_d2_params = {
···
446
446
.div_nmp = &pllp_nmp,
447
447
.freq_table = pll_d_freq_table,
448
448
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
449
-
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
449
+
TEGRA_PLL_HAS_LOCK_ENABLE,
450
450
};
451
451
452
452
static const struct pdiv_map pllu_p[] = {