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drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series. The change to use clamp_t() was
done manually.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/667869/
Link: https://lore.kernel.org/r/20250810-drm-msm-phy-clk-round-rate-v2-2-0fd1f7979c83@redhat.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Brian Masney and committed by
Dmitry Baryshkov cc41f29a fe3190a3

+17 -17
+17 -17
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
··· 578 578 pll_14nm->phy->pll_on = false; 579 579 } 580 580 581 - static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, 582 - unsigned long rate, unsigned long *parent_rate) 581 + static int dsi_pll_14nm_clk_determine_rate(struct clk_hw *hw, 582 + struct clk_rate_request *req) 583 583 { 584 584 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 585 585 586 - if (rate < pll_14nm->phy->cfg->min_pll_rate) 587 - return pll_14nm->phy->cfg->min_pll_rate; 588 - else if (rate > pll_14nm->phy->cfg->max_pll_rate) 589 - return pll_14nm->phy->cfg->max_pll_rate; 590 - else 591 - return rate; 586 + req->rate = clamp_t(unsigned long, req->rate, 587 + pll_14nm->phy->cfg->min_pll_rate, pll_14nm->phy->cfg->max_pll_rate); 588 + 589 + return 0; 592 590 } 593 591 594 592 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { 595 - .round_rate = dsi_pll_14nm_clk_round_rate, 593 + .determine_rate = dsi_pll_14nm_clk_determine_rate, 596 594 .set_rate = dsi_pll_14nm_vco_set_rate, 597 595 .recalc_rate = dsi_pll_14nm_vco_recalc_rate, 598 596 .prepare = dsi_pll_14nm_vco_prepare, ··· 620 622 postdiv->flags, width); 621 623 } 622 624 623 - static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, 624 - unsigned long rate, 625 - unsigned long *prate) 625 + static int dsi_pll_14nm_postdiv_determine_rate(struct clk_hw *hw, 626 + struct clk_rate_request *req) 626 627 { 627 628 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 628 629 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 629 630 630 - DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); 631 + DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, req->rate); 631 632 632 - return divider_round_rate(hw, rate, prate, NULL, 633 - postdiv->width, 634 - postdiv->flags); 633 + req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, 634 + NULL, 635 + postdiv->width, 636 + postdiv->flags); 637 + 638 + return 0; 635 639 } 636 640 637 641 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, ··· 680 680 681 681 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { 682 682 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, 683 - .round_rate = dsi_pll_14nm_postdiv_round_rate, 683 + .determine_rate = dsi_pll_14nm_postdiv_determine_rate, 684 684 .set_rate = dsi_pll_14nm_postdiv_set_rate, 685 685 }; 686 686