Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/panel: himax-hx83102: Add support for Holitech HTF065H045

This 720x1600 panel is found in several Motorola/Lenovo smartphones like
the Moto G9 Play (guamp). The initialization sequence is based on the
datasheet. Add it to the existing HX83102 panel driver.

Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260217070121.190108-4-val@packett.cool

authored by

Val Packett and committed by
Neil Armstrong
cc72a473 896e7b8c

+86
+86
drivers/gpu/drm/panel/panel-himax-hx83102.c
··· 701 701 return dsi_ctx.accum_err; 702 702 } 703 703 704 + static int holitech_htf065h045_init(struct hx83102 *ctx) 705 + { 706 + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 707 + 708 + msleep(50); 709 + 710 + hx83102_enable_extended_cmds(&dsi_ctx, true); 711 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x22, 0x44, 0x27, 0x27, 0x32, 712 + 0x52, 0x57, 0x39, 0x08, 0x08, 0x08); 713 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x00, 0x06, 0x40, 0x00, 714 + 0x0e, 0xae, 0x38, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xa0); 715 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x01, 0x58, 0x01, 0x58, 0x01, 716 + 0x58, 0x03, 0x58, 0x03, 0xff, 0x01, 0x20, 0x00, 0xff); 717 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 718 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x00, 0x00, 719 + 0x10, 0x00, 0x17, 0x00, 0x63, 0x37, 0x0e, 0x0e, 0x00, 0x00, 720 + 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x16, 0x4e, 0x06, 0x4e); 721 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x04, 0x0c, 0xb2, 0x01); 722 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x24, 0x25, 0x18, 0x18, 0x19, 723 + 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 724 + 0x18, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05, 0x18, 0x18, 0x18, 725 + 0x18, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21, 0x18, 0x18, 0x18, 726 + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 727 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x00, 0x09, 0x16, 0x1f, 0x28, 728 + 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 0x91, 0xa0, 0x9e, 729 + 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 0x7f, 0x00, 0x09, 730 + 0x16, 0x1f, 0x28, 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 731 + 0x91, 0xa0, 0x9e, 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 732 + 0x7f); 733 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xff, 0x14, 0x00, 0x00); 734 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 735 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x01); 736 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 737 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xff, 738 + 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0); 739 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 740 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 741 + 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 742 + 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 743 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 744 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x70, 0x23, 0xa8, 0x93, 0xb2, 745 + 0xc0, 0xc0, 0x01, 0x10, 0x00, 0x00, 0x00, 0x0d, 0x3d, 0x82, 746 + 0x77, 0x04, 0x01, 0x04); 747 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 748 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x01); 749 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 750 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x00, 0x53, 0x00, 0x02, 0x59); 751 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x00, 0x04, 0x9e, 0xf6, 752 + 0x00, 0x5d); 753 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 754 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x42, 0x00, 0x33, 0x00, 0x33, 755 + 0x88, 0xb3, 0x00); 756 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 757 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x20, 0x01); 758 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 759 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x7f, 0x03, 0xf5); 760 + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 761 + 762 + return dsi_ctx.accum_err; 763 + } 764 + 704 765 static const struct drm_display_mode starry_mode = { 705 766 .clock = 162680, 706 767 .hdisplay = 1200, ··· 892 831 .height_mm = 235, 893 832 }, 894 833 .init = starry_2082109qfh040022_50e_init, 834 + }; 835 + 836 + static const struct drm_display_mode holitech_htf065h045_default_mode = { 837 + .clock = 90720, 838 + .hdisplay = 720, 839 + .hsync_start = 720 + 40, 840 + .hsync_end = 720 + 40 + 40, 841 + .htotal = 720 + 40 + 40 + 40, 842 + .vdisplay = 1600, 843 + .vsync_start = 1600 + 186, 844 + .vsync_end = 1600 + 186 + 2, 845 + .vtotal = 1600 + 186 + 2 + 12, 846 + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 847 + }; 848 + 849 + static const struct hx83102_panel_desc holitech_htf065h045_desc = { 850 + .modes = &holitech_htf065h045_default_mode, 851 + .size = { 852 + .width_mm = 68, 853 + .height_mm = 151, 854 + }, 855 + .init = holitech_htf065h045_init, 895 856 }; 896 857 897 858 static int hx83102_enable(struct drm_panel *panel) ··· 1151 1068 }, 1152 1069 { .compatible = "starry,himax83102-j02", 1153 1070 .data = &starry_desc 1071 + }, 1072 + { .compatible = "holitech,htf065h045", 1073 + .data = &holitech_htf065h045_desc 1154 1074 }, 1155 1075 { /* sentinel */ } 1156 1076 };