tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2024-06-01' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"This is the weekly fixes. Lots of small fixes across the board, one
BUG_ON fix in shmem seems most important, otherwise amdgpu, i915, xe
mostly with small fixes to all the other drivers.

shmem:
- fix BUG_ON in COW handling
- warn when trying to pin imported objects

buddy:
- fix page size handling

dma-buf:
- sw-sync: Don't interfere with IRQ handling
- fix kthreads-handling error path

i915:
- fix a race in audio component by registering it later
- make DPT object unshrinkable to avoid shrinking when framebuffer
has not shrunk
- fix CCS id calculation to fix a perf regression
- fix selftest caching mode
- fix FIELD_PREP compiler warnings
- fix indefinite wait for GT wakeref release
- revert overeager multi-gt pm reference removal

xe:
- pcode polling timeout change
- fix for deadlocks for faulting VMs
- error-path lock imbalance fix

amdgpu:
- RAS fix
- fix colorspace property for MST connectors
- fix for PCIe DPM
- silence UBSAN warning
- GPUVM robustness fix
- partition fix
- drop deprecated I2C_CLASS_SPD

amdkfd:
- revert unused changes for certain 11.0.3 devices
- simplify APU VRAM handling

lima:
- fix dma_resv-related deadlock in object pin

msm:
- remove build-time dependency on Python 3.9

nouveau:
- nvif: Fix possible integer overflow

panel:
- lg-sw43408: Select DP helpers; Declare backlight ops as static
- sitronix-st7789v: Various fixes for jt240mhqs_hwt_ek_e3 panel

panfrost:
- fix dma_resv-related deadlock in object pin"

* tag 'drm-fixes-2024-06-01' of https://gitlab.freedesktop.org/drm/kernel: (35 commits)
drm/msm: remove python 3.9 dependency for compiling msm
drm/panel: sitronix-st7789v: fix display size for jt240mhqs_hwt_ek_e3 panel
drm/panel: sitronix-st7789v: tweak timing for jt240mhqs_hwt_ek_e3 panel
drm/panel: sitronix-st7789v: fix timing for jt240mhqs_hwt_ek_e3 panel
drm/amd/pm: remove deprecated I2C_CLASS_SPD support from newly added SMU_14_0_2
drm/amdgpu: Make CPX mode auto default in NPS4
drm/amdkfd: simplify APU VRAM handling
Revert "drm/amdkfd: fix gfx_target_version for certain 11.0.3 devices"
drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
drm/amdgpu: silence UBSAN warning
drm/amdgpu: Adjust logic in amdgpu_device_partner_bandwidth()
drm/i915: Fix audio component initialization
drm/i915/dpt: Make DPT object unshrinkable
drm/i915/gt: Fix CCS id's calculation for CCS mode setting
drm/panel/lg-sw43408: mark sw43408_backlight_ops as static
drm/i915/selftests: Set always_coherent to false when reading from CPU
drm/panel/lg-sw43408: select CONFIG_DRM_DISPLAY_DP_HELPER
drm/i915/guc: avoid FIELD_PREP warning
drm/i915/gt: Disarm breadcrumbs if engines are already idle
Revert "drm/i915: Remove extra multi-gt pm-references"
...

Linus Torvalds cc8ed4d0 1b907b83

+186 -114
+6
drivers/dma-buf/st-dma-fence.c
··· 540 540 t[i].before = pass; 541 541 t[i].task = kthread_run(thread_signal_callback, &t[i], 542 542 "dma-fence:%d", i); 543 + if (IS_ERR(t[i].task)) { 544 + ret = PTR_ERR(t[i].task); 545 + while (--i >= 0) 546 + kthread_stop_put(t[i].task); 547 + return ret; 548 + } 543 549 get_task_struct(t[i].task); 544 550 } 545 551
+2 -2
drivers/dma-buf/sync_debug.c
··· 110 110 111 111 seq_printf(s, "%s: %d\n", obj->name, obj->value); 112 112 113 - spin_lock_irq(&obj->lock); 113 + spin_lock(&obj->lock); /* Caller already disabled IRQ. */ 114 114 list_for_each(pos, &obj->pt_list) { 115 115 struct sync_pt *pt = container_of(pos, struct sync_pt, link); 116 116 sync_print_fence(s, &pt->base, false); 117 117 } 118 - spin_unlock_irq(&obj->lock); 118 + spin_unlock(&obj->lock); 119 119 } 120 120 121 121 static void sync_print_sync_file(struct seq_file *s,
+8 -8
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 196 196 return -EINVAL; 197 197 198 198 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id); 199 - if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) { 199 + if (adev->flags & AMD_IS_APU) { 200 200 system_mem_needed = size; 201 201 ttm_mem_needed = size; 202 202 } ··· 233 233 if (adev && xcp_id >= 0) { 234 234 adev->kfd.vram_used[xcp_id] += vram_needed; 235 235 adev->kfd.vram_used_aligned[xcp_id] += 236 - (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) ? 236 + (adev->flags & AMD_IS_APU) ? 237 237 vram_needed : 238 238 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN); 239 239 } ··· 261 261 262 262 if (adev) { 263 263 adev->kfd.vram_used[xcp_id] -= size; 264 - if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) { 264 + if (adev->flags & AMD_IS_APU) { 265 265 adev->kfd.vram_used_aligned[xcp_id] -= size; 266 266 kfd_mem_limit.system_mem_used -= size; 267 267 kfd_mem_limit.ttm_mem_used -= size; ··· 890 890 * if peer device has large BAR. In contrast, access over xGMI is 891 891 * allowed for both small and large BAR configurations of peer device 892 892 */ 893 - if ((adev != bo_adev && !(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU)) && 893 + if ((adev != bo_adev && !(adev->flags & AMD_IS_APU)) && 894 894 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) || 895 895 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || 896 896 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { ··· 1658 1658 - atomic64_read(&adev->vram_pin_size) 1659 1659 - reserved_for_pt; 1660 1660 1661 - if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) { 1661 + if (adev->flags & AMD_IS_APU) { 1662 1662 system_mem_available = no_system_mem_limit ? 1663 1663 kfd_mem_limit.max_system_mem_limit : 1664 1664 kfd_mem_limit.max_system_mem_limit - ··· 1706 1706 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1707 1707 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; 1708 1708 1709 - if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) { 1709 + if (adev->flags & AMD_IS_APU) { 1710 1710 domain = AMDGPU_GEM_DOMAIN_GTT; 1711 1711 alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1712 1712 alloc_flags = 0; ··· 1953 1953 if (size) { 1954 1954 if (!is_imported && 1955 1955 (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM || 1956 - ((adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) && 1956 + ((adev->flags & AMD_IS_APU) && 1957 1957 mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT))) 1958 1958 *size = bo_size; 1959 1959 else ··· 2376 2376 (*mem)->bo = bo; 2377 2377 (*mem)->va = va; 2378 2378 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && 2379 - !(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) ? 2379 + !(adev->flags & AMD_IS_APU) ? 2380 2380 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT; 2381 2381 2382 2382 (*mem)->mapped_to_gpu_memory = 0;
+12 -7
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 5944 5944 *speed = PCI_SPEED_UNKNOWN; 5945 5945 *width = PCIE_LNK_WIDTH_UNKNOWN; 5946 5946 5947 - while ((parent = pci_upstream_bridge(parent))) { 5948 - /* skip upstream/downstream switches internal to dGPU*/ 5949 - if (parent->vendor == PCI_VENDOR_ID_ATI) 5950 - continue; 5951 - *speed = pcie_get_speed_cap(parent); 5952 - *width = pcie_get_width_cap(parent); 5953 - break; 5947 + if (amdgpu_device_pcie_dynamic_switching_supported(adev)) { 5948 + while ((parent = pci_upstream_bridge(parent))) { 5949 + /* skip upstream/downstream switches internal to dGPU*/ 5950 + if (parent->vendor == PCI_VENDOR_ID_ATI) 5951 + continue; 5952 + *speed = pcie_get_speed_cap(parent); 5953 + *width = pcie_get_width_cap(parent); 5954 + break; 5955 + } 5956 + } else { 5957 + /* use the current speeds rather than max if switching is not supported */ 5958 + pcie_bandwidth_available(adev->pdev, NULL, speed, width); 5954 5959 } 5955 5960 } 5956 5961
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
··· 46 46 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7) 47 47 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8) 48 48 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11) 49 - #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 13, 13) 49 + #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13) 50 50 #define AMDGPU_RAS_GPU_ERR_BOOT_STATUS(x) AMDGPU_GET_REG_FIELD(x, 31, 31) 51 51 52 52 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 1000
+5 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
··· 706 706 struct amdgpu_vm_bo_base *entry) 707 707 { 708 708 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry); 709 - struct amdgpu_bo *bo = parent->bo, *pbo; 709 + struct amdgpu_bo *bo, *pbo; 710 710 struct amdgpu_vm *vm = params->vm; 711 711 uint64_t pde, pt, flags; 712 712 unsigned int level; 713 713 714 + if (WARN_ON(!parent)) 715 + return -EINVAL; 716 + 717 + bo = parent->bo; 714 718 for (level = 0, pbo = bo->parent; pbo; ++level) 715 719 pbo = pbo->parent; 716 720
+1 -1
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
··· 422 422 423 423 if (adev->gmc.num_mem_partitions == num_xcc / 2) 424 424 return (adev->flags & AMD_IS_APU) ? AMDGPU_TPX_PARTITION_MODE : 425 - AMDGPU_QPX_PARTITION_MODE; 425 + AMDGPU_CPX_PARTITION_MODE; 426 426 427 427 if (adev->gmc.num_mem_partitions == 2 && !(adev->flags & AMD_IS_APU)) 428 428 return AMDGPU_DPX_PARTITION_MODE;
+2 -9
drivers/gpu/drm/amd/amdkfd/kfd_device.c
··· 408 408 f2g = &gfx_v11_kfd2kgd; 409 409 break; 410 410 case IP_VERSION(11, 0, 3): 411 - if ((adev->pdev->device == 0x7460 && 412 - adev->pdev->revision == 0x00) || 413 - (adev->pdev->device == 0x7461 && 414 - adev->pdev->revision == 0x00)) 415 - /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 416 - gfx_target_version = 110005; 417 - else 418 - /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 419 - gfx_target_version = 110001; 411 + /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 412 + gfx_target_version = 110001; 420 413 f2g = &gfx_v11_kfd2kgd; 421 414 break; 422 415 case IP_VERSION(11, 5, 0):
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
··· 1023 1023 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 1)) 1024 1024 return -EINVAL; 1025 1025 1026 - if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) 1026 + if (adev->flags & AMD_IS_APU) 1027 1027 return 0; 1028 1028 1029 1029 pgmap = &kfddev->pgmap;
+2 -4
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
··· 2619 2619 return -1; 2620 2620 } 2621 2621 2622 - if (node->adev->gmc.is_app_apu || 2623 - node->adev->flags & AMD_IS_APU) 2622 + if (node->adev->flags & AMD_IS_APU) 2624 2623 return 0; 2625 2624 2626 2625 if (prange->preferred_loc == gpuid || ··· 3337 3338 goto out; 3338 3339 } 3339 3340 3340 - if (bo_node->adev->gmc.is_app_apu || 3341 - bo_node->adev->flags & AMD_IS_APU) { 3341 + if (bo_node->adev->flags & AMD_IS_APU) { 3342 3342 best_loc = 0; 3343 3343 goto out; 3344 3344 }
-1
drivers/gpu/drm/amd/amdkfd/kfd_svm.h
··· 201 201 * is initialized to not 0 when page migration register device memory. 202 202 */ 203 203 #define KFD_IS_SVM_API_SUPPORTED(adev) ((adev)->kfd.pgmap.type != 0 ||\ 204 - (adev)->gmc.is_app_apu ||\ 205 204 ((adev)->flags & AMD_IS_APU)) 206 205 207 206 void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
+3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 613 613 &connector->base, 614 614 dev->mode_config.tile_property, 615 615 0); 616 + connector->colorspace_property = master->base.colorspace_property; 617 + if (connector->colorspace_property) 618 + drm_connector_attach_colorspace_property(connector); 616 619 617 620 drm_connector_set_path_property(connector, pathprop); 618 621
+1 -1
drivers/gpu/drm/amd/include/atomfirmware.h
··· 3583 3583 uint8_t phase_delay_us; // phase delay in unit of micro second 3584 3584 uint8_t reserved; 3585 3585 uint32_t gpio_mask_val; // GPIO Mask value 3586 - struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3586 + struct atom_voltage_gpio_map_lut voltage_gpio_lut[] __counted_by(gpio_entry_num); 3587 3587 }; 3588 3588 3589 3589 struct atom_svid2_voltage_object_v4
-1
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
··· 1562 1562 smu_i2c->port = i; 1563 1563 mutex_init(&smu_i2c->mutex); 1564 1564 control->owner = THIS_MODULE; 1565 - control->class = I2C_CLASS_SPD; 1566 1565 control->dev.parent = &adev->pdev->dev; 1567 1566 control->algo = &smu_v14_0_2_i2c_algo; 1568 1567 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
+1 -1
drivers/gpu/drm/drm_buddy.c
··· 239 239 if (size < chunk_size) 240 240 return -EINVAL; 241 241 242 - if (chunk_size < PAGE_SIZE) 242 + if (chunk_size < SZ_4K) 243 243 return -EINVAL; 244 244 245 245 if (!is_power_of_2(chunk_size))
+5
drivers/gpu/drm/drm_gem_shmem_helper.c
··· 233 233 234 234 dma_resv_assert_held(shmem->base.resv); 235 235 236 + drm_WARN_ON(shmem->base.dev, shmem->base.import_attach); 237 + 236 238 ret = drm_gem_shmem_get_pages(shmem); 237 239 238 240 return ret; ··· 612 610 613 611 return ret; 614 612 } 613 + 614 + if (is_cow_mapping(vma->vm_flags)) 615 + return -EINVAL; 615 616 616 617 dma_resv_lock(shmem->base.resv, NULL); 617 618 ret = drm_gem_shmem_get_pages(shmem);
+21 -11
drivers/gpu/drm/i915/display/intel_audio.c
··· 1252 1252 static void i915_audio_component_init(struct drm_i915_private *i915) 1253 1253 { 1254 1254 u32 aud_freq, aud_freq_init; 1255 - int ret; 1256 - 1257 - ret = component_add_typed(i915->drm.dev, 1258 - &i915_audio_component_bind_ops, 1259 - I915_COMPONENT_AUDIO); 1260 - if (ret < 0) { 1261 - drm_err(&i915->drm, 1262 - "failed to add audio component (%d)\n", ret); 1263 - /* continue with reduced functionality */ 1264 - return; 1265 - } 1266 1255 1267 1256 if (DISPLAY_VER(i915) >= 9) { 1268 1257 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); ··· 1274 1285 1275 1286 /* init with current cdclk */ 1276 1287 intel_audio_cdclk_change_post(i915); 1288 + } 1289 + 1290 + static void i915_audio_component_register(struct drm_i915_private *i915) 1291 + { 1292 + int ret; 1293 + 1294 + ret = component_add_typed(i915->drm.dev, 1295 + &i915_audio_component_bind_ops, 1296 + I915_COMPONENT_AUDIO); 1297 + if (ret < 0) { 1298 + drm_err(&i915->drm, 1299 + "failed to add audio component (%d)\n", ret); 1300 + /* continue with reduced functionality */ 1301 + return; 1302 + } 1277 1303 1278 1304 i915->display.audio.component_registered = true; 1279 1305 } ··· 1319 1315 { 1320 1316 if (intel_lpe_audio_init(i915) < 0) 1321 1317 i915_audio_component_init(i915); 1318 + } 1319 + 1320 + void intel_audio_register(struct drm_i915_private *i915) 1321 + { 1322 + if (!i915->display.audio.lpe.platdev) 1323 + i915_audio_component_register(i915); 1322 1324 } 1323 1325 1324 1326 /**
+1
drivers/gpu/drm/i915/display/intel_audio.h
··· 28 28 void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv); 29 29 void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv); 30 30 void intel_audio_init(struct drm_i915_private *dev_priv); 31 + void intel_audio_register(struct drm_i915_private *i915); 31 32 void intel_audio_deinit(struct drm_i915_private *dev_priv); 32 33 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state); 33 34
+2
drivers/gpu/drm/i915/display/intel_display_driver.c
··· 540 540 541 541 intel_display_driver_enable_user_access(i915); 542 542 543 + intel_audio_register(i915); 544 + 543 545 intel_display_debugfs_register(i915); 544 546 545 547 /*
+18
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
··· 255 255 struct intel_context *context; /* logical state for the request */ 256 256 struct i915_gem_context *gem_context; /** caller's context */ 257 257 intel_wakeref_t wakeref; 258 + intel_wakeref_t wakeref_gt0; 258 259 259 260 /** our requests to build */ 260 261 struct i915_request *requests[MAX_ENGINE_INSTANCE + 1]; ··· 2686 2685 eb_select_engine(struct i915_execbuffer *eb) 2687 2686 { 2688 2687 struct intel_context *ce, *child; 2688 + struct intel_gt *gt; 2689 2689 unsigned int idx; 2690 2690 int err; 2691 2691 ··· 2710 2708 } 2711 2709 } 2712 2710 eb->num_batches = ce->parallel.number_children + 1; 2711 + gt = ce->engine->gt; 2713 2712 2714 2713 for_each_child(ce, child) 2715 2714 intel_context_get(child); 2716 2715 eb->wakeref = intel_gt_pm_get(ce->engine->gt); 2716 + /* 2717 + * Keep GT0 active on MTL so that i915_vma_parked() doesn't 2718 + * free VMAs while execbuf ioctl is validating VMAs. 2719 + */ 2720 + if (gt->info.id) 2721 + eb->wakeref_gt0 = intel_gt_pm_get(to_gt(gt->i915)); 2717 2722 2718 2723 if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { 2719 2724 err = intel_context_alloc_state(ce); ··· 2759 2750 return err; 2760 2751 2761 2752 err: 2753 + if (gt->info.id) 2754 + intel_gt_pm_put(to_gt(gt->i915), eb->wakeref_gt0); 2755 + 2762 2756 intel_gt_pm_put(ce->engine->gt, eb->wakeref); 2763 2757 for_each_child(ce, child) 2764 2758 intel_context_put(child); ··· 2775 2763 struct intel_context *child; 2776 2764 2777 2765 i915_vm_put(eb->context->vm); 2766 + /* 2767 + * This works in conjunction with eb_select_engine() to prevent 2768 + * i915_vma_parked() from interfering while execbuf validates vmas. 2769 + */ 2770 + if (eb->gt->info.id) 2771 + intel_gt_pm_put(to_gt(eb->gt->i915), eb->wakeref_gt0); 2778 2772 intel_gt_pm_put(eb->context->engine->gt, eb->wakeref); 2779 2773 for_each_child(eb->context, child) 2780 2774 intel_context_put(child);
+3 -1
drivers/gpu/drm/i915/gem/i915_gem_object.h
··· 284 284 static inline bool 285 285 i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) 286 286 { 287 - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE); 287 + /* TODO: make DPT shrinkable when it has no bound vmas */ 288 + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) && 289 + !obj->is_dpt; 288 290 } 289 291 290 292 static inline bool
+1 -1
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
··· 196 196 if (err) 197 197 goto out_file; 198 198 199 - mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true); 199 + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false); 200 200 vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode); 201 201 if (IS_ERR(vaddr)) { 202 202 err = PTR_ERR(vaddr);
+7 -8
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c
··· 263 263 i915_request_put(rq); 264 264 } 265 265 266 + /* Lazy irq enabling after HW submission */ 266 267 if (!READ_ONCE(b->irq_armed) && !list_empty(&b->signalers)) 267 268 intel_breadcrumbs_arm_irq(b); 269 + 270 + /* And confirm that we still want irqs enabled before we yield */ 271 + if (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) 272 + intel_breadcrumbs_disarm_irq(b); 268 273 } 269 274 270 275 struct intel_breadcrumbs * ··· 320 315 return; 321 316 322 317 /* Kick the work once more to drain the signalers, and disarm the irq */ 323 - irq_work_sync(&b->irq_work); 324 - while (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) { 325 - local_irq_disable(); 326 - signal_irq_work(&b->irq_work); 327 - local_irq_enable(); 328 - cond_resched(); 329 - } 318 + irq_work_queue(&b->irq_work); 330 319 } 331 320 332 321 void intel_breadcrumbs_free(struct kref *kref) ··· 403 404 * the request as it may have completed and raised the interrupt as 404 405 * we were attaching it into the lists. 405 406 */ 406 - if (!b->irq_armed || __i915_request_is_complete(rq)) 407 + if (!READ_ONCE(b->irq_armed) || __i915_request_is_complete(rq)) 407 408 irq_work_queue(&b->irq_work); 408 409 } 409 410
+6
drivers/gpu/drm/i915/gt/intel_engine_cs.c
··· 885 885 if (IS_DG2(gt->i915)) { 886 886 u8 first_ccs = __ffs(CCS_MASK(gt)); 887 887 888 + /* 889 + * Store the number of active cslices before 890 + * changing the CCS engine configuration 891 + */ 892 + gt->ccs.cslices = CCS_MASK(gt); 893 + 888 894 /* Mask off all the CCS engine */ 889 895 info->engine_mask &= ~GENMASK(CCS3, CCS0); 890 896 /* Put back in the first CCS engine */
+1 -1
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
··· 19 19 20 20 /* Build the value for the fixed CCS load balancing */ 21 21 for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { 22 - if (CCS_MASK(gt) & BIT(cslice)) 22 + if (gt->ccs.cslices & BIT(cslice)) 23 23 /* 24 24 * If available, assign the cslice 25 25 * to the first available engine...
+8
drivers/gpu/drm/i915/gt/intel_gt_types.h
··· 207 207 [MAX_ENGINE_INSTANCE + 1]; 208 208 enum intel_submission_method submission_method; 209 209 210 + struct { 211 + /* 212 + * Mask of the non fused CCS slices 213 + * to be used for the load balancing 214 + */ 215 + intel_engine_mask_t cslices; 216 + } ccs; 217 + 210 218 /* 211 219 * Default address space (either GGTT or ppGTT depending on arch). 212 220 *
+3 -3
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
··· 29 29 */ 30 30 31 31 #define GUC_KLV_LEN_MIN 1u 32 - #define GUC_KLV_0_KEY (0xffff << 16) 33 - #define GUC_KLV_0_LEN (0xffff << 0) 34 - #define GUC_KLV_n_VALUE (0xffffffff << 0) 32 + #define GUC_KLV_0_KEY (0xffffu << 16) 33 + #define GUC_KLV_0_LEN (0xffffu << 0) 34 + #define GUC_KLV_n_VALUE (0xffffffffu << 0) 35 35 36 36 /** 37 37 * DOC: GuC Self Config KLVs
+1 -1
drivers/gpu/drm/lima/lima_gem.c
··· 185 185 if (bo->heap_size) 186 186 return -EINVAL; 187 187 188 - return drm_gem_shmem_pin(&bo->base); 188 + return drm_gem_shmem_pin_locked(&bo->base); 189 189 } 190 190 191 191 static int lima_gem_vmap(struct drm_gem_object *obj, struct iosys_map *map)
+3 -2
drivers/gpu/drm/msm/registers/gen_header.py
··· 538 538 self.variants.add(reg.domain) 539 539 540 540 def do_validate(self, schemafile): 541 - if self.validate == False: 541 + if not self.validate: 542 542 return 543 543 544 544 try: ··· 948 948 parser = argparse.ArgumentParser() 949 949 parser.add_argument('--rnn', type=str, required=True) 950 950 parser.add_argument('--xml', type=str, required=True) 951 - parser.add_argument('--validate', action=argparse.BooleanOptionalAction) 951 + parser.add_argument('--validate', default=False, action='store_true') 952 + parser.add_argument('--no-validate', dest='validate', action='store_false') 952 953 953 954 subparsers = parser.add_subparsers() 954 955 subparsers.required = True
+18 -6
drivers/gpu/drm/nouveau/nvif/object.c
··· 142 142 struct nvif_ioctl_v0 ioctl; 143 143 struct nvif_ioctl_mthd_v0 mthd; 144 144 } *args; 145 + u32 args_size; 145 146 u8 stack[128]; 146 147 int ret; 147 148 148 - if (sizeof(*args) + size > sizeof(stack)) { 149 - if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) 149 + if (check_add_overflow(sizeof(*args), size, &args_size)) 150 + return -ENOMEM; 151 + 152 + if (args_size > sizeof(stack)) { 153 + args = kmalloc(args_size, GFP_KERNEL); 154 + if (!args) 150 155 return -ENOMEM; 151 156 } else { 152 157 args = (void *)stack; ··· 162 157 args->mthd.method = mthd; 163 158 164 159 memcpy(args->mthd.data, data, size); 165 - ret = nvif_object_ioctl(object, args, sizeof(*args) + size, NULL); 160 + ret = nvif_object_ioctl(object, args, args_size, NULL); 166 161 memcpy(data, args->mthd.data, size); 167 162 if (args != (void *)stack) 168 163 kfree(args); ··· 281 276 object->map.size = 0; 282 277 283 278 if (parent) { 284 - if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) { 279 + u32 args_size; 280 + 281 + if (check_add_overflow(sizeof(*args), size, &args_size)) { 282 + nvif_object_dtor(object); 283 + return -ENOMEM; 284 + } 285 + 286 + args = kmalloc(args_size, GFP_KERNEL); 287 + if (!args) { 285 288 nvif_object_dtor(object); 286 289 return -ENOMEM; 287 290 } ··· 306 293 args->new.oclass = oclass; 307 294 308 295 memcpy(args->new.data, data, size); 309 - ret = nvif_object_ioctl(parent, args, sizeof(*args) + size, 310 - &object->priv); 296 + ret = nvif_object_ioctl(parent, args, args_size, &object->priv); 311 297 memcpy(data, args->new.data, size); 312 298 kfree(args); 313 299 if (ret == 0)
+2
drivers/gpu/drm/panel/Kconfig
··· 340 340 depends on OF 341 341 depends on DRM_MIPI_DSI 342 342 depends on BACKLIGHT_CLASS_DEVICE 343 + select DRM_DISPLAY_DP_HELPER 344 + select DRM_DISPLAY_HELPER 343 345 help 344 346 Say Y here if you want to enable support for LG sw43408 panel. 345 347 The panel has a 1080x2160@60Hz resolution and uses 24 bit RGB per
+1 -1
drivers/gpu/drm/panel/panel-lg-sw43408.c
··· 182 182 return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); 183 183 } 184 184 185 - const struct backlight_ops sw43408_backlight_ops = { 185 + static const struct backlight_ops sw43408_backlight_ops = { 186 186 .update_status = sw43408_backlight_update_status, 187 187 }; 188 188
+8 -8
drivers/gpu/drm/panel/panel-sitronix-st7789v.c
··· 282 282 static const struct drm_display_mode jt240mhqs_hwt_ek_e3_mode = { 283 283 .clock = 6000, 284 284 .hdisplay = 240, 285 - .hsync_start = 240 + 28, 286 - .hsync_end = 240 + 28 + 10, 287 - .htotal = 240 + 28 + 10 + 10, 285 + .hsync_start = 240 + 38, 286 + .hsync_end = 240 + 38 + 10, 287 + .htotal = 240 + 38 + 10 + 10, 288 288 .vdisplay = 280, 289 - .vsync_start = 280 + 8, 290 - .vsync_end = 280 + 8 + 4, 291 - .vtotal = 280 + 8 + 4 + 4, 292 - .width_mm = 43, 293 - .height_mm = 37, 289 + .vsync_start = 280 + 48, 290 + .vsync_end = 280 + 48 + 4, 291 + .vtotal = 280 + 48 + 4 + 4, 292 + .width_mm = 37, 293 + .height_mm = 43, 294 294 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 295 295 }; 296 296
+1 -1
drivers/gpu/drm/panfrost/panfrost_gem.c
··· 192 192 if (bo->is_heap) 193 193 return -EINVAL; 194 194 195 - return drm_gem_shmem_pin(&bo->base); 195 + return drm_gem_shmem_pin_locked(&bo->base); 196 196 } 197 197 198 198 static enum drm_gem_object_status panfrost_gem_status(struct drm_gem_object *obj)
+21 -21
drivers/gpu/drm/tests/drm_buddy_test.c
··· 505 505 * Eventually we will have a fully 50% fragmented mm. 506 506 */ 507 507 508 - mm_size = PAGE_SIZE << max_order; 509 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, PAGE_SIZE), 508 + mm_size = SZ_4K << max_order; 509 + KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), 510 510 "buddy_init failed\n"); 511 511 512 512 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); ··· 520 520 } 521 521 522 522 for (order = top; order--;) { 523 - size = get_size(order, PAGE_SIZE); 523 + size = get_size(order, mm.chunk_size); 524 524 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, 525 525 mm_size, size, size, 526 526 &tmp, flags), ··· 534 534 } 535 535 536 536 /* There should be one final page for this sub-allocation */ 537 - size = get_size(0, PAGE_SIZE); 537 + size = get_size(0, mm.chunk_size); 538 538 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 539 539 size, size, &tmp, flags), 540 540 "buddy_alloc hit -ENOMEM for hole\n"); ··· 544 544 545 545 list_move_tail(&block->link, &holes); 546 546 547 - size = get_size(top, PAGE_SIZE); 547 + size = get_size(top, mm.chunk_size); 548 548 KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 549 549 size, size, &tmp, flags), 550 550 "buddy_alloc unexpectedly succeeded at top-order %d/%d, it should be full!", ··· 555 555 556 556 /* Nothing larger than blocks of chunk_size now available */ 557 557 for (order = 1; order <= max_order; order++) { 558 - size = get_size(order, PAGE_SIZE); 558 + size = get_size(order, mm.chunk_size); 559 559 KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 560 560 size, size, &tmp, flags), 561 561 "buddy_alloc unexpectedly succeeded at order %d, it should be full!", ··· 584 584 * page left. 585 585 */ 586 586 587 - mm_size = PAGE_SIZE << max_order; 588 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, PAGE_SIZE), 587 + mm_size = SZ_4K << max_order; 588 + KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), 589 589 "buddy_init failed\n"); 590 590 591 591 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); 592 592 593 593 for (order = 0; order < max_order; order++) { 594 - size = get_size(order, PAGE_SIZE); 594 + size = get_size(order, mm.chunk_size); 595 595 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 596 596 size, size, &tmp, flags), 597 597 "buddy_alloc hit -ENOMEM with order=%d\n", ··· 604 604 } 605 605 606 606 /* And now the last remaining block available */ 607 - size = get_size(0, PAGE_SIZE); 607 + size = get_size(0, mm.chunk_size); 608 608 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 609 609 size, size, &tmp, flags), 610 610 "buddy_alloc hit -ENOMEM on final alloc\n"); ··· 616 616 617 617 /* Should be completely full! */ 618 618 for (order = max_order; order--;) { 619 - size = get_size(order, PAGE_SIZE); 619 + size = get_size(order, mm.chunk_size); 620 620 KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 621 621 size, size, &tmp, flags), 622 622 "buddy_alloc unexpectedly succeeded, it should be full!"); ··· 632 632 list_del(&block->link); 633 633 drm_buddy_free_block(&mm, block); 634 634 635 - size = get_size(order, PAGE_SIZE); 635 + size = get_size(order, mm.chunk_size); 636 636 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 637 637 size, size, &tmp, flags), 638 638 "buddy_alloc hit -ENOMEM with order=%d\n", ··· 647 647 } 648 648 649 649 /* To confirm, now the whole mm should be available */ 650 - size = get_size(max_order, PAGE_SIZE); 650 + size = get_size(max_order, mm.chunk_size); 651 651 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 652 652 size, size, &tmp, flags), 653 653 "buddy_alloc (realloc) hit -ENOMEM with order=%d\n", ··· 678 678 * try to allocate them all. 679 679 */ 680 680 681 - mm_size = PAGE_SIZE * ((1 << (max_order + 1)) - 1); 681 + mm_size = SZ_4K * ((1 << (max_order + 1)) - 1); 682 682 683 - KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, PAGE_SIZE), 683 + KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_init(&mm, mm_size, SZ_4K), 684 684 "buddy_init failed\n"); 685 685 686 686 KUNIT_EXPECT_EQ(test, mm.max_order, max_order); 687 687 688 688 for (order = 0; order <= max_order; order++) { 689 - size = get_size(order, PAGE_SIZE); 689 + size = get_size(order, mm.chunk_size); 690 690 KUNIT_ASSERT_FALSE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 691 691 size, size, &tmp, flags), 692 692 "buddy_alloc hit -ENOMEM with order=%d\n", ··· 699 699 } 700 700 701 701 /* Should be completely full! */ 702 - size = get_size(0, PAGE_SIZE); 702 + size = get_size(0, mm.chunk_size); 703 703 KUNIT_ASSERT_TRUE_MSG(test, drm_buddy_alloc_blocks(&mm, start, mm_size, 704 704 size, size, &tmp, flags), 705 705 "buddy_alloc unexpectedly succeeded, it should be full!"); ··· 716 716 LIST_HEAD(allocated); 717 717 struct drm_buddy mm; 718 718 719 - KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, size, PAGE_SIZE)); 719 + KUNIT_EXPECT_FALSE(test, drm_buddy_init(&mm, size, SZ_4K)); 720 720 721 721 KUNIT_EXPECT_EQ_MSG(test, mm.max_order, DRM_BUDDY_MAX_ORDER, 722 722 "mm.max_order(%d) != %d\n", mm.max_order, ··· 724 724 725 725 size = mm.chunk_size << mm.max_order; 726 726 KUNIT_EXPECT_FALSE(test, drm_buddy_alloc_blocks(&mm, start, size, size, 727 - PAGE_SIZE, &allocated, flags)); 727 + mm.chunk_size, &allocated, flags)); 728 728 729 729 block = list_first_entry_or_null(&allocated, struct drm_buddy_block, link); 730 730 KUNIT_EXPECT_TRUE(test, block); ··· 734 734 drm_buddy_block_order(block), mm.max_order); 735 735 736 736 KUNIT_EXPECT_EQ_MSG(test, drm_buddy_block_size(&mm, block), 737 - BIT_ULL(mm.max_order) * PAGE_SIZE, 737 + BIT_ULL(mm.max_order) * mm.chunk_size, 738 738 "block size(%llu) != %llu\n", 739 739 drm_buddy_block_size(&mm, block), 740 - BIT_ULL(mm.max_order) * PAGE_SIZE); 740 + BIT_ULL(mm.max_order) * mm.chunk_size); 741 741 742 742 drm_buddy_free_list(&mm, &allocated, 0); 743 743 drm_buddy_fini(&mm);
+1
drivers/gpu/drm/xe/xe_guc_submit.c
··· 1240 1240 return 0; 1241 1241 1242 1242 err_entity: 1243 + mutex_unlock(&guc->submission_state.lock); 1243 1244 xe_sched_entity_fini(&ge->entity); 1244 1245 err_sched: 1245 1246 xe_sched_fini(&ge->sched);
+5 -7
drivers/gpu/drm/xe/xe_migrate.c
··· 34 34 #include "xe_sync.h" 35 35 #include "xe_trace.h" 36 36 #include "xe_vm.h" 37 - #include "xe_wa.h" 38 37 39 38 /** 40 39 * struct xe_migrate - migrate context. ··· 299 300 } 300 301 301 302 /* 302 - * Due to workaround 16017236439, odd instance hardware copy engines are 303 - * faster than even instance ones. 304 - * This function returns the mask involving all fast copy engines and the 305 - * reserved copy engine to be used as logical mask for migrate engine. 306 303 * Including the reserved copy engine is required to avoid deadlocks due to 307 304 * migrate jobs servicing the faults gets stuck behind the job that faulted. 308 305 */ ··· 312 317 if (hwe->class != XE_ENGINE_CLASS_COPY) 313 318 continue; 314 319 315 - if (!XE_WA(gt, 16017236439) || 316 - xe_gt_is_usm_hwe(gt, hwe) || hwe->instance & 1) 320 + if (xe_gt_is_usm_hwe(gt, hwe)) 317 321 logical_mask |= BIT(hwe->logical_instance); 318 322 } 319 323 ··· 363 369 if (!hwe || !logical_mask) 364 370 return ERR_PTR(-EINVAL); 365 371 372 + /* 373 + * XXX: Currently only reserving 1 (likely slow) BCS instance on 374 + * PVC, may want to revisit if performance is needed. 375 + */ 366 376 m->q = xe_exec_queue_create(xe, vm, logical_mask, 1, hwe, 367 377 EXEC_QUEUE_FLAG_KERNEL | 368 378 EXEC_QUEUE_FLAG_PERMANENT |
+1 -1
drivers/gpu/drm/xe/xe_pcode.c
··· 191 191 drm_WARN_ON_ONCE(&gt_to_xe(gt)->drm, timeout_base_ms > 1); 192 192 preempt_disable(); 193 193 ret = pcode_try_request(gt, mbox, request, reply_mask, reply, &status, 194 - true, timeout_base_ms * 1000, true); 194 + true, 50 * 1000, true); 195 195 preempt_enable(); 196 196 197 197 out:
+3 -3
include/drm/drm_buddy.h
··· 56 56 struct list_head tmp_link; 57 57 }; 58 58 59 - /* Order-zero must be at least PAGE_SIZE */ 60 - #define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) 59 + /* Order-zero must be at least SZ_4K */ 60 + #define DRM_BUDDY_MAX_ORDER (63 - 12) 61 61 62 62 /* 63 63 * Binary Buddy System. ··· 85 85 unsigned int n_roots; 86 86 unsigned int max_order; 87 87 88 - /* Must be at least PAGE_SIZE */ 88 + /* Must be at least SZ_4K */ 89 89 u64 chunk_size; 90 90 u64 size; 91 91 u64 avail;