Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/{i915, xe}/dsb: move DSB buffer to parent interface
Move the DSB buffer handling to the display parent interface, making
display more independent of i915 and xe driver implementations.
Since the DSB parent interface is only called from intel_dsb.c, add the
wrappers there with smaller visibility instead of the usual
intel_parent.[ch], and using struct intel_dsb as the context parameter
for convenience.
Unfortunately, memset() being a macro in linux/fortify-string.h, we
can't use that as the function pointer name. dsb->memset() would be
using the macro and leading to build failures. Therefore, use .fill()
for the memset() functionality.
v2: s/memset/fill/
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/df117c862a6d34dae340e4a85c2482b4e29c8884.1768923917.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+146
-60
+70
-22
drivers/gpu/drm/i915/display/intel_dsb.c
+70
-22
drivers/gpu/drm/i915/display/intel_dsb.c
···
8
8
9
9
#include <drm/drm_print.h>
10
10
#include <drm/drm_vblank.h>
11
+
#include <drm/intel/display_parent_interface.h>
11
12
12
13
#include "intel_crtc.h"
13
14
#include "intel_de.h"
···
16
15
#include "intel_display_rpm.h"
17
16
#include "intel_display_types.h"
18
17
#include "intel_dsb.h"
19
-
#include "intel_dsb_buffer.h"
20
18
#include "intel_dsb_regs.h"
21
19
#include "intel_vblank.h"
22
20
#include "intel_vrr.h"
···
74
74
* DSB HW can support only register writes (both indexed and direct MMIO
75
75
* writes). There are no registers reads possible with DSB HW engine.
76
76
*/
77
+
78
+
/*
79
+
* DSB buffer parent interface calls are here instead of intel_parent.[ch]
80
+
* because they're not used outside of intel_dsb.c.
81
+
*/
82
+
static u32 dsb_buffer_ggtt_offset(struct intel_dsb *dsb)
83
+
{
84
+
struct intel_display *display = to_intel_display(dsb->crtc);
85
+
86
+
return display->parent->dsb->ggtt_offset(dsb->dsb_buf);
87
+
}
88
+
89
+
static void dsb_buffer_write(struct intel_dsb *dsb, u32 idx, u32 val)
90
+
{
91
+
struct intel_display *display = to_intel_display(dsb->crtc);
92
+
93
+
display->parent->dsb->write(dsb->dsb_buf, idx, val);
94
+
}
95
+
96
+
static u32 dsb_buffer_read(struct intel_dsb *dsb, u32 idx)
97
+
{
98
+
struct intel_display *display = to_intel_display(dsb->crtc);
99
+
100
+
return display->parent->dsb->read(dsb->dsb_buf, idx);
101
+
}
102
+
103
+
static void dsb_buffer_fill(struct intel_dsb *dsb, u32 idx, u32 val, size_t size)
104
+
{
105
+
struct intel_display *display = to_intel_display(dsb->crtc);
106
+
107
+
display->parent->dsb->fill(dsb->dsb_buf, idx, val, size);
108
+
}
109
+
110
+
static struct intel_dsb_buffer *dsb_buffer_create(struct intel_display *display, size_t size)
111
+
{
112
+
return display->parent->dsb->create(display->drm, size);
113
+
}
114
+
115
+
static void dsb_buffer_cleanup(struct intel_dsb *dsb)
116
+
{
117
+
struct intel_display *display = to_intel_display(dsb->crtc);
118
+
119
+
display->parent->dsb->cleanup(dsb->dsb_buf);
120
+
}
121
+
122
+
static void dsb_buffer_flush_map(struct intel_dsb *dsb)
123
+
{
124
+
struct intel_display *display = to_intel_display(dsb->crtc);
125
+
126
+
display->parent->dsb->flush_map(dsb->dsb_buf);
127
+
}
77
128
78
129
/* DSB opcodes. */
79
130
#define DSB_OPCODE_SHIFT 24
···
262
211
for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
263
212
drm_dbg_kms(display->drm,
264
213
" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4,
265
-
intel_dsb_buffer_read(dsb->dsb_buf, i),
266
-
intel_dsb_buffer_read(dsb->dsb_buf, i + 1),
267
-
intel_dsb_buffer_read(dsb->dsb_buf, i + 2),
268
-
intel_dsb_buffer_read(dsb->dsb_buf, i + 3));
214
+
dsb_buffer_read(dsb, i),
215
+
dsb_buffer_read(dsb, i + 1),
216
+
dsb_buffer_read(dsb, i + 2),
217
+
dsb_buffer_read(dsb, i + 3));
269
218
drm_dbg_kms(display->drm, "}\n");
270
219
}
271
220
···
282
231
283
232
unsigned int intel_dsb_head(struct intel_dsb *dsb)
284
233
{
285
-
return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf);
234
+
return dsb_buffer_ggtt_offset(dsb);
286
235
}
287
236
288
237
static unsigned int intel_dsb_tail(struct intel_dsb *dsb)
289
238
{
290
-
return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf) + intel_dsb_size(dsb);
239
+
return dsb_buffer_ggtt_offset(dsb) + intel_dsb_size(dsb);
291
240
}
292
241
293
242
static void intel_dsb_ins_align(struct intel_dsb *dsb)
···
314
263
dsb->ins[0] = ldw;
315
264
dsb->ins[1] = udw;
316
265
317
-
intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]);
318
-
intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]);
266
+
dsb_buffer_write(dsb, dsb->free_pos++, dsb->ins[0]);
267
+
dsb_buffer_write(dsb, dsb->free_pos++, dsb->ins[1]);
319
268
}
320
269
321
270
static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
···
386
335
387
336
/* Update the count */
388
337
dsb->ins[0]++;
389
-
intel_dsb_buffer_write(dsb->dsb_buf, dsb->ins_start_offset + 0,
390
-
dsb->ins[0]);
338
+
dsb_buffer_write(dsb, dsb->ins_start_offset + 0, dsb->ins[0]);
391
339
392
-
intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, val);
340
+
dsb_buffer_write(dsb, dsb->free_pos++, val);
393
341
/* if number of data words is odd, then the last dword should be 0.*/
394
342
if (dsb->free_pos & 0x1)
395
-
intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos, 0);
343
+
dsb_buffer_write(dsb, dsb->free_pos, 0);
396
344
}
397
345
398
346
void intel_dsb_reg_write(struct intel_dsb *dsb,
···
571
521
aligned_tail = ALIGN(tail, CACHELINE_BYTES);
572
522
573
523
if (aligned_tail > tail)
574
-
intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0,
575
-
aligned_tail - tail);
524
+
dsb_buffer_fill(dsb, dsb->free_pos, 0, aligned_tail - tail);
576
525
577
526
dsb->free_pos = aligned_tail / 4;
578
527
}
···
590
541
* "Ensure GOSUB is not placed in cacheline QW slot 6 or 7 (numbered 0-7)"
591
542
*/
592
543
if (aligned_tail - tail <= 2 * 8)
593
-
intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0,
594
-
aligned_tail - tail);
544
+
dsb_buffer_fill(dsb, dsb->free_pos, 0, aligned_tail - tail);
595
545
596
546
dsb->free_pos = aligned_tail / 4;
597
547
}
···
654
606
*/
655
607
intel_dsb_noop(dsb, 8);
656
608
657
-
intel_dsb_buffer_flush_map(dsb->dsb_buf);
609
+
dsb_buffer_flush_map(dsb);
658
610
}
659
611
660
612
void intel_dsb_finish(struct intel_dsb *dsb)
661
613
{
662
614
intel_dsb_align_tail(dsb);
663
615
664
-
intel_dsb_buffer_flush_map(dsb->dsb_buf);
616
+
dsb_buffer_flush_map(dsb);
665
617
}
666
618
667
619
static u32 dsb_error_int_status(struct intel_display *display)
···
965
917
!is_busy,
966
918
100, 1000, false);
967
919
if (ret) {
968
-
u32 offset = intel_dsb_buffer_ggtt_offset(dsb->dsb_buf);
920
+
u32 offset = dsb_buffer_ggtt_offset(dsb);
969
921
970
922
intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id),
971
923
DSB_ENABLE | DSB_HALT);
···
1031
983
/* ~1 qword per instruction, full cachelines */
1032
984
size = ALIGN(max_cmds * 8, CACHELINE_BYTES);
1033
985
1034
-
dsb_buf = intel_dsb_buffer_create(display->drm, size);
986
+
dsb_buf = dsb_buffer_create(display, size);
1035
987
if (IS_ERR(dsb_buf))
1036
988
goto out_put_rpm;
1037
989
···
1069
1021
*/
1070
1022
void intel_dsb_cleanup(struct intel_dsb *dsb)
1071
1023
{
1072
-
intel_dsb_buffer_cleanup(dsb->dsb_buf);
1024
+
dsb_buffer_cleanup(dsb);
1073
1025
kfree(dsb);
1074
1026
}
1075
1027
-22
drivers/gpu/drm/i915/display/intel_dsb_buffer.h
-22
drivers/gpu/drm/i915/display/intel_dsb_buffer.h
···
1
-
/* SPDX-License-Identifier: MIT */
2
-
/*
3
-
* Copyright © 2023 Intel Corporation
4
-
*/
5
-
6
-
#ifndef _INTEL_DSB_BUFFER_H
7
-
#define _INTEL_DSB_BUFFER_H
8
-
9
-
#include <linux/types.h>
10
-
11
-
struct drm_device;
12
-
struct intel_dsb_buffer;
13
-
14
-
u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf);
15
-
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val);
16
-
u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx);
17
-
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size);
18
-
struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size);
19
-
void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf);
20
-
void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf);
21
-
22
-
#endif
+2
drivers/gpu/drm/i915/i915_driver.c
+2
drivers/gpu/drm/i915/i915_driver.c
···
93
93
#include "i915_driver.h"
94
94
#include "i915_drm_client.h"
95
95
#include "i915_drv.h"
96
+
#include "i915_dsb_buffer.h"
96
97
#include "i915_edram.h"
97
98
#include "i915_file_private.h"
98
99
#include "i915_getparam.h"
···
765
764
}
766
765
767
766
static const struct intel_display_parent_interface parent = {
767
+
.dsb = &i915_display_dsb_interface,
768
768
.hdcp = &i915_display_hdcp_interface,
769
769
.initial_plane = &i915_display_initial_plane_interface,
770
770
.irq = &i915_display_irq_interface,
+20
-8
drivers/gpu/drm/i915/i915_dsb_buffer.c
+20
-8
drivers/gpu/drm/i915/i915_dsb_buffer.c
···
3
3
* Copyright 2023, Intel Corporation.
4
4
*/
5
5
6
-
#include "display/intel_dsb_buffer.h"
6
+
#include <drm/intel/display_parent_interface.h>
7
+
7
8
#include "gem/i915_gem_internal.h"
8
9
#include "gem/i915_gem_lmem.h"
9
10
#include "i915_drv.h"
11
+
#include "i915_dsb_buffer.h"
10
12
#include "i915_vma.h"
11
13
12
14
struct intel_dsb_buffer {
···
17
15
size_t buf_size;
18
16
};
19
17
20
-
u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
18
+
static u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
21
19
{
22
20
return i915_ggtt_offset(dsb_buf->vma);
23
21
}
24
22
25
-
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
23
+
static void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
26
24
{
27
25
dsb_buf->cmd_buf[idx] = val;
28
26
}
29
27
30
-
u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
28
+
static u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
31
29
{
32
30
return dsb_buf->cmd_buf[idx];
33
31
}
34
32
35
-
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
33
+
static void intel_dsb_buffer_fill(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
36
34
{
37
35
WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
38
36
39
37
memset(&dsb_buf->cmd_buf[idx], val, size);
40
38
}
41
39
42
-
struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size)
40
+
static struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size)
43
41
{
44
42
struct drm_i915_private *i915 = to_i915(drm);
45
43
struct intel_dsb_buffer *dsb_buf;
···
95
93
return ERR_PTR(ret);
96
94
}
97
95
98
-
void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
96
+
static void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
99
97
{
100
98
i915_vma_unpin_and_release(&dsb_buf->vma, I915_VMA_RELEASE_MAP);
101
99
kfree(dsb_buf);
102
100
}
103
101
104
-
void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
102
+
static void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
105
103
{
106
104
i915_gem_object_flush_map(dsb_buf->vma->obj);
107
105
}
106
+
107
+
const struct intel_display_dsb_interface i915_display_dsb_interface = {
108
+
.ggtt_offset = intel_dsb_buffer_ggtt_offset,
109
+
.write = intel_dsb_buffer_write,
110
+
.read = intel_dsb_buffer_read,
111
+
.fill = intel_dsb_buffer_fill,
112
+
.create = intel_dsb_buffer_create,
113
+
.cleanup = intel_dsb_buffer_cleanup,
114
+
.flush_map = intel_dsb_buffer_flush_map,
115
+
};
+9
drivers/gpu/drm/i915/i915_dsb_buffer.h
+9
drivers/gpu/drm/i915/i915_dsb_buffer.h
+2
drivers/gpu/drm/xe/display/xe_display.c
+2
drivers/gpu/drm/xe/display/xe_display.c
···
36
36
#include "intel_opregion.h"
37
37
#include "skl_watermark.h"
38
38
#include "xe_display_rpm.h"
39
+
#include "xe_dsb_buffer.h"
39
40
#include "xe_hdcp_gsc.h"
40
41
#include "xe_initial_plane.h"
41
42
#include "xe_module.h"
···
539
538
};
540
539
541
540
static const struct intel_display_parent_interface parent = {
541
+
.dsb = &xe_display_dsb_interface,
542
542
.hdcp = &xe_display_hdcp_interface,
543
543
.initial_plane = &xe_display_initial_plane_interface,
544
544
.irq = &xe_display_irq_interface,
+20
-8
drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+20
-8
drivers/gpu/drm/xe/display/xe_dsb_buffer.c
···
3
3
* Copyright 2023, Intel Corporation.
4
4
*/
5
5
6
-
#include "intel_dsb_buffer.h"
6
+
#include <drm/intel/display_parent_interface.h>
7
+
7
8
#include "xe_bo.h"
8
9
#include "xe_device.h"
9
10
#include "xe_device_types.h"
11
+
#include "xe_dsb_buffer.h"
10
12
11
13
struct intel_dsb_buffer {
12
14
u32 *cmd_buf;
···
16
14
size_t buf_size;
17
15
};
18
16
19
-
u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
17
+
static u32 xe_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
20
18
{
21
19
return xe_bo_ggtt_addr(dsb_buf->bo);
22
20
}
23
21
24
-
void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
22
+
static void xe_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
25
23
{
26
24
iosys_map_wr(&dsb_buf->bo->vmap, idx * 4, u32, val);
27
25
}
28
26
29
-
u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
27
+
static u32 xe_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
30
28
{
31
29
return iosys_map_rd(&dsb_buf->bo->vmap, idx * 4, u32);
32
30
}
33
31
34
-
void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
32
+
static void xe_dsb_buffer_fill(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
35
33
{
36
34
WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
37
35
38
36
iosys_map_memset(&dsb_buf->bo->vmap, idx * 4, val, size);
39
37
}
40
38
41
-
struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size)
39
+
static struct intel_dsb_buffer *xe_dsb_buffer_create(struct drm_device *drm, size_t size)
42
40
{
43
41
struct xe_device *xe = to_xe_device(drm);
44
42
struct intel_dsb_buffer *dsb_buf;
···
71
69
return ERR_PTR(ret);
72
70
}
73
71
74
-
void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
72
+
static void xe_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
75
73
{
76
74
xe_bo_unpin_map_no_vm(dsb_buf->bo);
77
75
kfree(dsb_buf);
78
76
}
79
77
80
-
void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
78
+
static void xe_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
81
79
{
82
80
struct xe_device *xe = dsb_buf->bo->tile->xe;
83
81
···
88
86
xe_device_wmb(xe);
89
87
xe_device_l2_flush(xe);
90
88
}
89
+
90
+
const struct intel_display_dsb_interface xe_display_dsb_interface = {
91
+
.ggtt_offset = xe_dsb_buffer_ggtt_offset,
92
+
.write = xe_dsb_buffer_write,
93
+
.read = xe_dsb_buffer_read,
94
+
.fill = xe_dsb_buffer_fill,
95
+
.create = xe_dsb_buffer_create,
96
+
.cleanup = xe_dsb_buffer_cleanup,
97
+
.flush_map = xe_dsb_buffer_flush_map,
98
+
};
+9
drivers/gpu/drm/xe/display/xe_dsb_buffer.h
+9
drivers/gpu/drm/xe/display/xe_dsb_buffer.h
+14
include/drm/intel/display_parent_interface.h
+14
include/drm/intel/display_parent_interface.h
···
14
14
struct drm_plane_state;
15
15
struct drm_scanout_buffer;
16
16
struct i915_vma;
17
+
struct intel_dsb_buffer;
17
18
struct intel_hdcp_gsc_context;
18
19
struct intel_initial_plane_config;
19
20
struct intel_panic;
···
22
21
struct ref_tracker;
23
22
24
23
/* Keep struct definitions sorted */
24
+
25
+
struct intel_display_dsb_interface {
26
+
u32 (*ggtt_offset)(struct intel_dsb_buffer *dsb_buf);
27
+
void (*write)(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val);
28
+
u32 (*read)(struct intel_dsb_buffer *dsb_buf, u32 idx);
29
+
void (*fill)(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size);
30
+
struct intel_dsb_buffer *(*create)(struct drm_device *drm, size_t size);
31
+
void (*cleanup)(struct intel_dsb_buffer *dsb_buf);
32
+
void (*flush_map)(struct intel_dsb_buffer *dsb_buf);
33
+
};
25
34
26
35
struct intel_display_hdcp_interface {
27
36
ssize_t (*gsc_msg_send)(struct intel_hdcp_gsc_context *gsc_context,
···
117
106
* check the optional pointers.
118
107
*/
119
108
struct intel_display_parent_interface {
109
+
/** @dsb: DSB buffer interface */
110
+
const struct intel_display_dsb_interface *dsb;
111
+
120
112
/** @hdcp: HDCP GSC interface */
121
113
const struct intel_display_hdcp_interface *hdcp;
122
114