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drm/amdkfd: update buffer_{store,load}_* modifiers for gfx940

Instruction modifiers of the untyped vector memory buffer instructions
(MUBUF encoded) changed in gfx940. The slc, scc and glc modifiers have
been replaced with sc0, sc1 and nt.

The current CWSR trap handler is written using pre-gfx940 modifier
names, making the source incompatible with a strict gfx940 assembler.

This patch updates the cwsr_trap_handler_gfx9.s source file to be
compatible with all gfx9 variants of the ISA. The binary assembled code
is unchanged (so the behaviour is unchanged as well), only the source
representation is updated.

Signed-off-by: Lancelot SIX <lancelot.six@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lancelot SIX and committed by
Alex Deucher ccca9964 71985559

+15 -9
+15 -9
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
··· 48 48 var SAVE_AFTER_XNACK_ERROR = 1 //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger 49 49 var SINGLE_STEP_MISSED_WORKAROUND = (ASIC_FAMILY <= CHIP_ALDEBARAN) //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 50 50 51 + #if ASIC_FAMILY < CHIP_GC_9_4_3 52 + #define VMEM_MODIFIERS slc:1 glc:1 53 + #else 54 + #define VMEM_MODIFIERS sc0:1 nt:1 55 + #endif 56 + 51 57 /**************************************************************************/ 52 58 /* variables */ 53 59 /**************************************************************************/ ··· 587 581 L_SAVE_LDS_LOOP_VECTOR: 588 582 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 589 583 s_waitcnt lgkmcnt(0) 590 - buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 584 + buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset VMEM_MODIFIERS offen:1 591 585 // s_waitcnt vmcnt(0) 592 586 // v_add_u32 v2, vcc[0:1], v2, v3 593 587 v_add_u32 v2, v2, v3 ··· 985 979 end 986 980 987 981 function write_4vgprs_to_mem(s_rsrc, s_mem_offset) 988 - buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 989 - buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 990 - buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 991 - buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 982 + buffer_store_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 983 + buffer_store_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256 984 + buffer_store_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2 985 + buffer_store_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3 992 986 end 993 987 994 988 function read_4vgprs_from_mem(s_rsrc, s_mem_offset) 995 - buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1 996 - buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256 997 - buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2 998 - buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3 989 + buffer_load_dword v0, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS 990 + buffer_load_dword v1, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256 991 + buffer_load_dword v2, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*2 992 + buffer_load_dword v3, v0, s_rsrc, s_mem_offset VMEM_MODIFIERS offset:256*3 999 993 s_waitcnt vmcnt(0) 1000 994 end 1001 995