Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: qat - refactor compression template logic
The logic that generates the compression templates, which are used by to
submit compression requests to the QAT device, is very similar between
QAT devices and diverges mainly on the HW generation-specific
configuration word.
This makes the logic that generates the compression and decompression
templates common between GEN2 and GEN4 devices and abstracts the
generation-specific logic to the generation-specific implementations.
The adf_gen2_dc.c and adf_gen4_dc.c have been replaced by adf_dc.c, and
the generation-specific logic has been reduced and moved to
adf_gen2_hw_data.c and adf_gen4_hw_data.c.
This does not introduce any functional change.
Co-developed-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com>
Signed-off-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com>
Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Suman Kumar Chakraborty
and committed by
Herbert Xu
cd0e7160
b8ca4380
+173
-146
-1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
-1
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
-1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
-1
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
-1
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
-1
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
-1
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
-1
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
-1
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
-1
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
-1
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
-1
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
+1
-2
drivers/crypto/intel/qat/qat_common/Makefile
+1
-2
drivers/crypto/intel/qat/qat_common/Makefile
···
8
8
adf_cfg_services.o \
9
9
adf_clock.o \
10
10
adf_ctl_drv.o \
11
+
adf_dc.o \
11
12
adf_dev_mgr.o \
12
13
adf_gen2_config.o \
13
-
adf_gen2_dc.o \
14
14
adf_gen2_hw_csr_data.o \
15
15
adf_gen2_hw_data.o \
16
16
adf_gen4_config.o \
17
-
adf_gen4_dc.o \
18
17
adf_gen4_hw_csr_data.o \
19
18
adf_gen4_hw_data.o \
20
19
adf_gen4_pm.o \
+3
-1
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+3
-1
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
···
12
12
#include <linux/qat/qat_mig_dev.h>
13
13
#include <linux/wordpart.h>
14
14
#include "adf_cfg_common.h"
15
+
#include "adf_dc.h"
15
16
#include "adf_rl.h"
16
17
#include "adf_telemetry.h"
17
18
#include "adf_pfvf_msg.h"
···
268
267
};
269
268
270
269
struct adf_dc_ops {
271
-
void (*build_deflate_ctx)(void *ctx);
270
+
int (*build_comp_block)(void *ctx, enum adf_dc_algo algo);
271
+
int (*build_decomp_block)(void *ctx, enum adf_dc_algo algo);
272
272
};
273
273
274
274
struct qat_migdev_ops {
+17
drivers/crypto/intel/qat/qat_common/adf_dc.h
+17
drivers/crypto/intel/qat/qat_common/adf_dc.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/* Copyright(c) 2025 Intel Corporation */
3
+
#ifndef ADF_DC_H
4
+
#define ADF_DC_H
5
+
6
+
struct adf_accel_dev;
7
+
8
+
enum adf_dc_algo {
9
+
QAT_DEFLATE,
10
+
QAT_LZ4,
11
+
QAT_LZ4S,
12
+
QAT_ZSTD,
13
+
};
14
+
15
+
int qat_comp_build_ctx(struct adf_accel_dev *accel_dev, void *ctx, enum adf_dc_algo algo);
16
+
17
+
#endif /* ADF_DC_H */
+20
-27
drivers/crypto/intel/qat/qat_common/adf_gen2_dc.c
drivers/crypto/intel/qat/qat_common/adf_dc.c
+20
-27
drivers/crypto/intel/qat/qat_common/adf_gen2_dc.c
drivers/crypto/intel/qat/qat_common/adf_dc.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/* Copyright(c) 2022 Intel Corporation */
3
3
#include "adf_accel_devices.h"
4
-
#include "adf_gen2_dc.h"
4
+
#include "adf_dc.h"
5
5
#include "icp_qat_fw_comp.h"
6
6
7
-
static void qat_comp_build_deflate_ctx(void *ctx)
7
+
int qat_comp_build_ctx(struct adf_accel_dev *accel_dev, void *ctx, enum adf_dc_algo algo)
8
8
{
9
-
struct icp_qat_fw_comp_req *req_tmpl = (struct icp_qat_fw_comp_req *)ctx;
10
-
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
11
-
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
12
-
struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
9
+
struct icp_qat_fw_comp_req *req_tmpl = ctx;
13
10
struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
11
+
struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
12
+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
13
+
int ret;
14
14
15
15
memset(req_tmpl, 0, sizeof(*req_tmpl));
16
16
header->hdr_flags =
17
17
ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
18
18
header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
19
-
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
20
19
header->comn_req_flags =
21
20
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
22
21
QAT_COMN_PTR_TYPE_SGL);
···
25
26
ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
26
27
ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
27
28
ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
28
-
cd_pars->u.sl.comp_slice_cfg_word[0] =
29
-
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
30
-
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
31
-
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
32
-
ICP_QAT_HW_COMPRESSION_DEPTH_1,
33
-
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
29
+
30
+
/* Build HW config block for compression */
31
+
ret = GET_DC_OPS(accel_dev)->build_comp_block(ctx, algo);
32
+
if (ret) {
33
+
dev_err(&GET_DEV(accel_dev), "Failed to build compression block\n");
34
+
return ret;
35
+
}
36
+
34
37
req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
35
38
req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
36
39
req_pars->req_par_flags =
···
53
52
/* Fill second half of the template for decompression */
54
53
memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
55
54
req_tmpl++;
56
-
header = &req_tmpl->comn_hdr;
57
-
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
58
-
cd_pars = &req_tmpl->cd_pars;
59
-
cd_pars->u.sl.comp_slice_cfg_word[0] =
60
-
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
61
-
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
62
-
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
63
-
ICP_QAT_HW_COMPRESSION_DEPTH_1,
64
-
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
65
-
}
66
55
67
-
void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
68
-
{
69
-
dc_ops->build_deflate_ctx = qat_comp_build_deflate_ctx;
56
+
/* Build HW config block for decompression */
57
+
ret = GET_DC_OPS(accel_dev)->build_decomp_block(req_tmpl, algo);
58
+
if (ret)
59
+
dev_err(&GET_DEV(accel_dev), "Failed to build decompression block\n");
60
+
61
+
return ret;
70
62
}
71
-
EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);
-10
drivers/crypto/intel/qat/qat_common/adf_gen2_dc.h
-10
drivers/crypto/intel/qat/qat_common/adf_gen2_dc.h
+57
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
+57
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
···
1
1
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2
2
/* Copyright(c) 2020 Intel Corporation */
3
3
#include "adf_common_drv.h"
4
+
#include "adf_dc.h"
4
5
#include "adf_gen2_hw_data.h"
6
+
#include "icp_qat_fw_comp.h"
5
7
#include "icp_qat_hw.h"
6
8
#include <linux/pci.h>
7
9
···
171
169
}
172
170
}
173
171
EXPORT_SYMBOL_GPL(adf_gen2_set_ssm_wdtimer);
172
+
173
+
static int adf_gen2_build_comp_block(void *ctx, enum adf_dc_algo algo)
174
+
{
175
+
struct icp_qat_fw_comp_req *req_tmpl = ctx;
176
+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
177
+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
178
+
179
+
switch (algo) {
180
+
case QAT_DEFLATE:
181
+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
182
+
break;
183
+
default:
184
+
return -EINVAL;
185
+
}
186
+
187
+
cd_pars->u.sl.comp_slice_cfg_word[0] =
188
+
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
189
+
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
190
+
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
191
+
ICP_QAT_HW_COMPRESSION_DEPTH_1,
192
+
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
193
+
194
+
return 0;
195
+
}
196
+
197
+
static int adf_gen2_build_decomp_block(void *ctx, enum adf_dc_algo algo)
198
+
{
199
+
struct icp_qat_fw_comp_req *req_tmpl = ctx;
200
+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
201
+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
202
+
203
+
switch (algo) {
204
+
case QAT_DEFLATE:
205
+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
206
+
break;
207
+
default:
208
+
return -EINVAL;
209
+
}
210
+
211
+
cd_pars->u.sl.comp_slice_cfg_word[0] =
212
+
ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
213
+
ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
214
+
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
215
+
ICP_QAT_HW_COMPRESSION_DEPTH_1,
216
+
ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
217
+
218
+
return 0;
219
+
}
220
+
221
+
void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
222
+
{
223
+
dc_ops->build_comp_block = adf_gen2_build_comp_block;
224
+
dc_ops->build_decomp_block = adf_gen2_build_decomp_block;
225
+
}
226
+
EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);
+1
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
+1
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
-83
drivers/crypto/intel/qat/qat_common/adf_gen4_dc.c
-83
drivers/crypto/intel/qat/qat_common/adf_gen4_dc.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/* Copyright(c) 2022 Intel Corporation */
3
-
#include "adf_accel_devices.h"
4
-
#include "icp_qat_fw_comp.h"
5
-
#include "icp_qat_hw_20_comp.h"
6
-
#include "adf_gen4_dc.h"
7
-
8
-
static void qat_comp_build_deflate(void *ctx)
9
-
{
10
-
struct icp_qat_fw_comp_req *req_tmpl =
11
-
(struct icp_qat_fw_comp_req *)ctx;
12
-
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
13
-
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
14
-
struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
15
-
struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = {0};
16
-
struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = {0};
17
-
struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = {0};
18
-
u32 upper_val;
19
-
u32 lower_val;
20
-
21
-
memset(req_tmpl, 0, sizeof(*req_tmpl));
22
-
header->hdr_flags =
23
-
ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
24
-
header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
25
-
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
26
-
header->comn_req_flags =
27
-
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
28
-
QAT_COMN_PTR_TYPE_SGL);
29
-
header->serv_specif_flags =
30
-
ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
31
-
ICP_QAT_FW_COMP_AUTO_SELECT_BEST,
32
-
ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
33
-
ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
34
-
ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
35
-
hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
36
-
hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
37
-
hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
38
-
hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
39
-
hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
40
-
hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
41
-
hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
42
-
hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
43
-
44
-
upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
45
-
lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
46
-
47
-
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
48
-
cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
49
-
50
-
req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
51
-
req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
52
-
req_pars->req_par_flags =
53
-
ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
54
-
ICP_QAT_FW_COMP_EOP,
55
-
ICP_QAT_FW_COMP_BFINAL,
56
-
ICP_QAT_FW_COMP_CNV,
57
-
ICP_QAT_FW_COMP_CNV_RECOVERY,
58
-
ICP_QAT_FW_COMP_NO_CNV_DFX,
59
-
ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
60
-
ICP_QAT_FW_COMP_NO_XXHASH_ACC,
61
-
ICP_QAT_FW_COMP_CNV_ERROR_NONE,
62
-
ICP_QAT_FW_COMP_NO_APPEND_CRC,
63
-
ICP_QAT_FW_COMP_NO_DROP_DATA);
64
-
65
-
/* Fill second half of the template for decompression */
66
-
memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
67
-
req_tmpl++;
68
-
header = &req_tmpl->comn_hdr;
69
-
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
70
-
cd_pars = &req_tmpl->cd_pars;
71
-
72
-
hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
73
-
lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
74
-
75
-
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
76
-
cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
77
-
}
78
-
79
-
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
80
-
{
81
-
dc_ops->build_deflate_ctx = qat_comp_build_deflate;
82
-
}
83
-
EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);
-10
drivers/crypto/intel/qat/qat_common/adf_gen4_dc.h
-10
drivers/crypto/intel/qat/qat_common/adf_gen4_dc.h
+70
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
+70
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
···
9
9
#include "adf_fw_config.h"
10
10
#include "adf_gen4_hw_data.h"
11
11
#include "adf_gen4_pm.h"
12
+
#include "icp_qat_fw_comp.h"
13
+
#include "icp_qat_hw_20_comp.h"
12
14
13
15
u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)
14
16
{
···
665
663
return ret;
666
664
}
667
665
EXPORT_SYMBOL_GPL(adf_gen4_bank_state_restore);
666
+
667
+
static int adf_gen4_build_comp_block(void *ctx, enum adf_dc_algo algo)
668
+
{
669
+
struct icp_qat_fw_comp_req *req_tmpl = ctx;
670
+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
671
+
struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr = { };
672
+
struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr = { };
673
+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
674
+
u32 upper_val;
675
+
u32 lower_val;
676
+
677
+
switch (algo) {
678
+
case QAT_DEFLATE:
679
+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DYNAMIC;
680
+
break;
681
+
default:
682
+
return -EINVAL;
683
+
}
684
+
685
+
hw_comp_lower_csr.skip_ctrl = ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
686
+
hw_comp_lower_csr.algo = ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
687
+
hw_comp_lower_csr.lllbd = ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
688
+
hw_comp_lower_csr.sd = ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
689
+
hw_comp_lower_csr.hash_update = ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
690
+
hw_comp_lower_csr.edmm = ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
691
+
hw_comp_upper_csr.nice = ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
692
+
hw_comp_upper_csr.lazy = ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
693
+
694
+
upper_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(hw_comp_upper_csr);
695
+
lower_val = ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(hw_comp_lower_csr);
696
+
697
+
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
698
+
cd_pars->u.sl.comp_slice_cfg_word[1] = upper_val;
699
+
700
+
return 0;
701
+
}
702
+
703
+
static int adf_gen4_build_decomp_block(void *ctx, enum adf_dc_algo algo)
704
+
{
705
+
struct icp_qat_fw_comp_req *req_tmpl = ctx;
706
+
struct icp_qat_hw_decomp_20_config_csr_lower hw_decomp_lower_csr = { };
707
+
struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
708
+
struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
709
+
u32 lower_val;
710
+
711
+
switch (algo) {
712
+
case QAT_DEFLATE:
713
+
header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
714
+
break;
715
+
default:
716
+
return -EINVAL;
717
+
}
718
+
719
+
hw_decomp_lower_csr.algo = ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
720
+
lower_val = ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(hw_decomp_lower_csr);
721
+
722
+
cd_pars->u.sl.comp_slice_cfg_word[0] = lower_val;
723
+
cd_pars->u.sl.comp_slice_cfg_word[1] = 0;
724
+
725
+
return 0;
726
+
}
727
+
728
+
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops)
729
+
{
730
+
dc_ops->build_comp_block = adf_gen4_build_comp_block;
731
+
dc_ops->build_decomp_block = adf_gen4_build_decomp_block;
732
+
}
733
+
EXPORT_SYMBOL_GPL(adf_gen4_init_dc_ops);
+2
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
+2
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h
···
7
7
8
8
#include "adf_accel_devices.h"
9
9
#include "adf_cfg_common.h"
10
+
#include "adf_dc.h"
10
11
11
12
/* PCIe configuration space */
12
13
#define ADF_GEN4_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
···
181
180
int adf_gen4_bank_state_restore(struct adf_accel_dev *accel_dev,
182
181
u32 bank_number, struct bank_state *state);
183
182
bool adf_gen4_services_supported(unsigned long service_mask);
183
+
void adf_gen4_init_dc_ops(struct adf_dc_ops *dc_ops);
184
184
185
185
#endif
+2
-3
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
+2
-3
drivers/crypto/intel/qat/qat_common/qat_comp_algs.c
···
8
8
#include <linux/workqueue.h>
9
9
#include "adf_accel_devices.h"
10
10
#include "adf_common_drv.h"
11
+
#include "adf_dc.h"
11
12
#include "qat_bl.h"
12
13
#include "qat_comp_req.h"
13
14
#include "qat_compression.h"
···
146
145
return -EINVAL;
147
146
ctx->inst = inst;
148
147
149
-
ctx->inst->build_deflate_ctx(ctx->comp_ctx);
150
-
151
-
return 0;
148
+
return qat_comp_build_ctx(inst->accel_dev, ctx->comp_ctx, QAT_DEFLATE);
152
149
}
153
150
154
151
static void qat_comp_alg_exit_tfm(struct crypto_acomp *acomp_tfm)
-1
drivers/crypto/intel/qat/qat_common/qat_compression.c
-1
drivers/crypto/intel/qat/qat_common/qat_compression.c
···
144
144
inst->id = i;
145
145
atomic_set(&inst->refctr, 0);
146
146
inst->accel_dev = accel_dev;
147
-
inst->build_deflate_ctx = GET_DC_OPS(accel_dev)->build_deflate_ctx;
148
147
149
148
snprintf(key, sizeof(key), ADF_DC "%d" ADF_RING_DC_BANK_NUM, i);
150
149
ret = adf_cfg_get_param_value(accel_dev, SEC, key, val);
-1
drivers/crypto/intel/qat/qat_common/qat_compression.h
-1
drivers/crypto/intel/qat/qat_common/qat_compression.h
-1
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
-1
drivers/crypto/intel/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
-1
drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
-1
drivers/crypto/intel/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c