+1

drivers/clk/Kconfig

reviewed

··· 504 504 source "drivers/clk/aspeed/Kconfig" 505 505 source "drivers/clk/baikal-t1/Kconfig" 506 506 source "drivers/clk/bcm/Kconfig" 507 507 + source "drivers/clk/eswin/Kconfig" 507 508 source "drivers/clk/hisilicon/Kconfig" 508 509 source "drivers/clk/imgtec/Kconfig" 509 510 source "drivers/clk/imx/Kconfig"

+1

drivers/clk/Makefile

reviewed

··· 120 120 obj-y += bcm/ 121 121 obj-$(CONFIG_ARCH_BERLIN) += berlin/ 122 122 obj-$(CONFIG_ARCH_DAVINCI) += davinci/ 123 123 + obj-$(CONFIG_COMMON_CLK_ESWIN) += eswin/ 123 124 obj-$(CONFIG_ARCH_HISI) += hisilicon/ 124 125 obj-y += imgtec/ 125 126 obj-y += imx/

+15

drivers/clk/eswin/Kconfig

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + 3 3 + config COMMON_CLK_ESWIN 4 4 + bool 5 5 + 6 6 + config COMMON_CLK_EIC7700 7 7 + tristate "EIC7700 Clock Driver" 8 8 + depends on ARCH_ESWIN || COMPILE_TEST 9 9 + select COMMON_CLK_ESWIN 10 10 + default ARCH_ESWIN 11 11 + help 12 12 + This driver provides support for clock controller on ESWIN EIC7700 13 13 + SoC. The clock controller generates and supplies clocks to various 14 14 + peripherals within the SoC. 15 15 + Say yes here to support the clock controller on the EIC7700 SoC.

+8

drivers/clk/eswin/Makefile

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + # 3 3 + # Eswin Clock specific Makefile 4 4 + # 5 5 + 6 6 + obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o 7 7 + 8 8 + obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o

+1376

drivers/clk/eswin/clk-eic7700.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4 4 + * All rights reserved. 5 5 + * 6 6 + * ESWIN EIC7700 Clk Provider Driver 7 7 + * 8 8 + * Authors: 9 9 + * Yifeng Huang <huangyifeng@eswincomputing.com> 10 10 + * Xuyang Dong <dongxuyang@eswincomputing.com> 11 11 + */ 12 12 + 13 13 + #include <linux/clk.h> 14 14 + #include <linux/clk-provider.h> 15 15 + #include <linux/platform_device.h> 16 16 + 17 17 + #include <dt-bindings/clock/eswin,eic7700-clock.h> 18 18 + 19 19 + #include "common.h" 20 20 + 21 21 + /* REG OFFSET OF SYS-CRG */ 22 22 + #define EIC7700_REG_OFFSET_SPLL0_CFG_0 0x0 23 23 + #define EIC7700_REG_OFFSET_SPLL0_CFG_1 0x4 24 24 + #define EIC7700_REG_OFFSET_SPLL0_CFG_2 0x8 25 25 + #define EIC7700_REG_OFFSET_SPLL0_DSKEWCAL 0xC 26 26 + #define EIC7700_REG_OFFSET_SPLL0_SSC 0x10 27 27 + #define EIC7700_REG_OFFSET_SPLL1_CFG_0 0x14 28 28 + #define EIC7700_REG_OFFSET_SPLL1_CFG_1 0x18 29 29 + #define EIC7700_REG_OFFSET_SPLL1_CFG_2 0x1C 30 30 + #define EIC7700_REG_OFFSET_SPLL1_DSKEWCAL 0x20 31 31 + #define EIC7700_REG_OFFSET_SPLL1_SSC 0x24 32 32 + #define EIC7700_REG_OFFSET_SPLL2_CFG_0 0x28 33 33 + #define EIC7700_REG_OFFSET_SPLL2_CFG_1 0x2C 34 34 + #define EIC7700_REG_OFFSET_SPLL2_CFG_2 0x30 35 35 + #define EIC7700_REG_OFFSET_SPLL2_DSKEWCAL 0x34 36 36 + #define EIC7700_REG_OFFSET_SPLL2_SSC 0x38 37 37 + #define EIC7700_REG_OFFSET_VPLL_CFG_0 0x3C 38 38 + #define EIC7700_REG_OFFSET_VPLL_CFG_1 0x40 39 39 + #define EIC7700_REG_OFFSET_VPLL_CFG_2 0x44 40 40 + #define EIC7700_REG_OFFSET_VPLL_DSKEWCAL 0x48 41 41 + #define EIC7700_REG_OFFSET_VPLL_SSC 0x4C 42 42 + #define EIC7700_REG_OFFSET_APLL_CFG_0 0x50 43 43 + #define EIC7700_REG_OFFSET_APLL_CFG_1 0x54 44 44 + #define EIC7700_REG_OFFSET_APLL_CFG_2 0x58 45 45 + #define EIC7700_REG_OFFSET_APLL_DSKEWCAL 0x5C 46 46 + #define EIC7700_REG_OFFSET_APLL_SSC 0x60 47 47 + #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0 0x64 48 48 + #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1 0x68 49 49 + #define EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2 0x6C 50 50 + #define EIC7700_REG_OFFSET_MCPUT_PLL_DSKEWCAL 0x70 51 51 + #define EIC7700_REG_OFFSET_MCPUT_PLL_SSC 0x74 52 52 + #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_0 0x78 53 53 + #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_1 0x7C 54 54 + #define EIC7700_REG_OFFSET_DDRT_PLL_CFG_2 0x80 55 55 + #define EIC7700_REG_OFFSET_DDRT_PLL_DSKEWCAL 0x84 56 56 + #define EIC7700_REG_OFFSET_DDRT_PLL_SSC 0x88 57 57 + #define EIC7700_REG_OFFSET_PLL_STATUS 0xA4 58 58 + #define EIC7700_REG_OFFSET_NOC 0x100 59 59 + #define EIC7700_REG_OFFSET_BOOTSPI 0x104 60 60 + #define EIC7700_REG_OFFSET_BOOTSPI_CFGCLK 0x108 61 61 + #define EIC7700_REG_OFFSET_SCPU_CORE 0x10C 62 62 + #define EIC7700_REG_OFFSET_SCPU_BUSCLK 0x110 63 63 + #define EIC7700_REG_OFFSET_LPCPU_CORE 0x114 64 64 + #define EIC7700_REG_OFFSET_LPCPU_BUSCLK 0x118 65 65 + #define EIC7700_REG_OFFSET_TCU_ACLK 0x11C 66 66 + #define EIC7700_REG_OFFSET_TCU_CFG 0x120 67 67 + #define EIC7700_REG_OFFSET_DDR 0x124 68 68 + #define EIC7700_REG_OFFSET_DDR1 0x128 69 69 + #define EIC7700_REG_OFFSET_GPU_ACLK 0x12C 70 70 + #define EIC7700_REG_OFFSET_GPU_CFG 0x130 71 71 + #define EIC7700_REG_OFFSET_GPU_GRAY 0x134 72 72 + #define EIC7700_REG_OFFSET_DSP_ACLK 0x138 73 73 + #define EIC7700_REG_OFFSET_DSP_CFG 0x13C 74 74 + #define EIC7700_REG_OFFSET_D2D_ACLK 0x140 75 75 + #define EIC7700_REG_OFFSET_D2D_CFG 0x144 76 76 + #define EIC7700_REG_OFFSET_HSP_ACLK 0x148 77 77 + #define EIC7700_REG_OFFSET_HSP_CFG 0x14C 78 78 + #define EIC7700_REG_OFFSET_SATA_RBC 0x150 79 79 + #define EIC7700_REG_OFFSET_SATA_OOB 0x154 80 80 + #define EIC7700_REG_OFFSET_ETH0 0x158 81 81 + #define EIC7700_REG_OFFSET_ETH1 0x15C 82 82 + #define EIC7700_REG_OFFSET_MSHC0_CORE 0x160 83 83 + #define EIC7700_REG_OFFSET_MSHC1_CORE 0x164 84 84 + #define EIC7700_REG_OFFSET_MSHC2_CORE 0x168 85 85 + #define EIC7700_REG_OFFSET_MSHC_USB_SLWCLK 0x16C 86 86 + #define EIC7700_REG_OFFSET_PCIE_ACLK 0x170 87 87 + #define EIC7700_REG_OFFSET_PCIE_CFG 0x174 88 88 + #define EIC7700_REG_OFFSET_NPU_ACLK 0x178 89 89 + #define EIC7700_REG_OFFSET_NPU_LLC 0x17C 90 90 + #define EIC7700_REG_OFFSET_NPU_CORE 0x180 91 91 + #define EIC7700_REG_OFFSET_VI_DWCLK 0x184 92 92 + #define EIC7700_REG_OFFSET_VI_ACLK 0x188 93 93 + #define EIC7700_REG_OFFSET_VI_DIG_ISP 0x18C 94 94 + #define EIC7700_REG_OFFSET_VI_DVP 0x190 95 95 + #define EIC7700_REG_OFFSET_VI_SHUTTER0 0x194 96 96 + #define EIC7700_REG_OFFSET_VI_SHUTTER1 0x198 97 97 + #define EIC7700_REG_OFFSET_VI_SHUTTER2 0x19C 98 98 + #define EIC7700_REG_OFFSET_VI_SHUTTER3 0x1A0 99 99 + #define EIC7700_REG_OFFSET_VI_SHUTTER4 0x1A4 100 100 + #define EIC7700_REG_OFFSET_VI_SHUTTER5 0x1A8 101 101 + #define EIC7700_REG_OFFSET_VI_PHY 0x1AC 102 102 + #define EIC7700_REG_OFFSET_VO_ACLK 0x1B0 103 103 + #define EIC7700_REG_OFFSET_VO_IESMCLK 0x1B4 104 104 + #define EIC7700_REG_OFFSET_VO_PIXEL 0x1B8 105 105 + #define EIC7700_REG_OFFSET_VO_MCLK 0x1BC 106 106 + #define EIC7700_REG_OFFSET_VO_PHY_CLK 0x1C0 107 107 + #define EIC7700_REG_OFFSET_VC_ACLK 0x1C4 108 108 + #define EIC7700_REG_OFFSET_VCDEC_ROOT 0x1C8 109 109 + #define EIC7700_REG_OFFSET_G2D 0x1CC 110 110 + #define EIC7700_REG_OFFSET_VC_CLKEN 0x1D0 111 111 + #define EIC7700_REG_OFFSET_JE 0x1D4 112 112 + #define EIC7700_REG_OFFSET_JD 0x1D8 113 113 + #define EIC7700_REG_OFFSET_VD 0x1DC 114 114 + #define EIC7700_REG_OFFSET_VE 0x1E0 115 115 + #define EIC7700_REG_OFFSET_AON_DMA 0x1E4 116 116 + #define EIC7700_REG_OFFSET_TIMER 0x1E8 117 117 + #define EIC7700_REG_OFFSET_RTC 0x1EC 118 118 + #define EIC7700_REG_OFFSET_PKA 0x1F0 119 119 + #define EIC7700_REG_OFFSET_SPACC 0x1F4 120 120 + #define EIC7700_REG_OFFSET_TRNG 0x1F8 121 121 + #define EIC7700_REG_OFFSET_OTP 0x1FC 122 122 + #define EIC7700_REG_OFFSET_LSP_EN0 0x200 123 123 + #define EIC7700_REG_OFFSET_LSP_EN1 0x204 124 124 + #define EIC7700_REG_OFFSET_U84 0x208 125 125 + #define EIC7700_REG_OFFSET_SYSCFG 0x20C 126 126 + #define EIC7700_REG_OFFSET_I2C0 0x210 127 127 + #define EIC7700_REG_OFFSET_I2C1 0x214 128 128 + 129 129 + #define EIC7700_NR_CLKS (EIC7700_CLK_GATE_NOC_WDREF + 1) 130 130 + 131 131 + /* 132 132 + * The 24 MHz oscillator, the root of most of the clock tree. 133 133 + */ 134 134 + static const struct clk_parent_data xtal24M[] = { 135 135 + { .index = 0, } 136 136 + }; 137 137 + 138 138 + /* fixed rate clocks */ 139 139 + static struct eswin_fixed_rate_clock eic7700_fixed_rate_clks[] = { 140 140 + ESWIN_FIXED(EIC7700_CLK_XTAL_32K, "fixed_rate_clk_xtal_32k", 0, 32768), 141 141 + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT1, "fixed_rate_clk_spll0_fout1", 0, 142 142 + 1600000000), 143 143 + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT2, "fixed_rate_clk_spll0_fout2", 0, 144 144 + 800000000), 145 145 + ESWIN_FIXED(EIC7700_CLK_SPLL0_FOUT3, "fixed_rate_clk_spll0_fout3", 0, 146 146 + 400000000), 147 147 + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT1, "fixed_rate_clk_spll1_fout1", 0, 148 148 + 1500000000), 149 149 + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT2, "fixed_rate_clk_spll1_fout2", 0, 150 150 + 300000000), 151 151 + ESWIN_FIXED(EIC7700_CLK_SPLL1_FOUT3, "fixed_rate_clk_spll1_fout3", 0, 152 152 + 250000000), 153 153 + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT1, "fixed_rate_clk_spll2_fout1", 0, 154 154 + 2080000000), 155 155 + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT2, "fixed_rate_clk_spll2_fout2", 0, 156 156 + 1040000000), 157 157 + ESWIN_FIXED(EIC7700_CLK_SPLL2_FOUT3, "fixed_rate_clk_spll2_fout3", 0, 158 158 + 416000000), 159 159 + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT1, "fixed_rate_clk_vpll_fout1", 0, 160 160 + 1188000000), 161 161 + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT2, "fixed_rate_clk_vpll_fout2", 0, 162 162 + 594000000), 163 163 + ESWIN_FIXED(EIC7700_CLK_VPLL_FOUT3, "fixed_rate_clk_vpll_fout3", 0, 164 164 + 49500000), 165 165 + ESWIN_FIXED(EIC7700_CLK_APLL_FOUT2, "fixed_rate_clk_apll_fout2", 0, 0), 166 166 + ESWIN_FIXED(EIC7700_CLK_APLL_FOUT3, "fixed_rate_clk_apll_fout3", 0, 0), 167 167 + ESWIN_FIXED(EIC7700_CLK_EXT_MCLK, "fixed_rate_ext_mclk", 0, 0), 168 168 + ESWIN_FIXED(EIC7700_CLK_LPDDR_REF_BAK, "fixed_rate_lpddr_ref_bak", 0, 169 169 + 50000000), 170 170 + }; 171 171 + 172 172 + /* pll clocks */ 173 173 + static struct eswin_pll_clock eic7700_pll_clks[] = { 174 174 + ESWIN_PLL(EIC7700_CLK_APLL_FOUT1, "clk_apll_fout1", xtal24M, 175 175 + EIC7700_REG_OFFSET_APLL_CFG_0, 20, 176 176 + EIC7700_REG_OFFSET_APLL_CFG_1, 4, 177 177 + EIC7700_REG_OFFSET_APLL_CFG_2, EIC7700_REG_OFFSET_PLL_STATUS, 178 178 + 4, 1, APLL_HIGH_FREQ, APLL_LOW_FREQ), 179 179 + ESWIN_PLL(EIC7700_CLK_PLL_CPU, "clk_pll_cpu", xtal24M, 180 180 + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_0, 20, 181 181 + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_1, 4, 182 182 + EIC7700_REG_OFFSET_MCPUT_PLL_CFG_2, 183 183 + EIC7700_REG_OFFSET_PLL_STATUS, 5, 1, PLL_HIGH_FREQ, 184 184 + PLL_LOW_FREQ), 185 185 + }; 186 186 + 187 187 + /* fixed factor clocks */ 188 188 + static struct eswin_fixed_factor_clock eic7700_factor_clks[] = { 189 189 + ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 190 190 + "fixed_factor_clk_1m_div24", xtal24M, 1, 24, 0), 191 191 + ESWIN_FACTOR(EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, 192 192 + "fixed_factor_pvt_div20", xtal24M, 1, 20, 0), 193 193 + }; 194 194 + 195 195 + /* divider clocks */ 196 196 + static struct eswin_divider_clock eic7700_div_clks[] = { 197 197 + ESWIN_DIV(EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM, 198 198 + "divider_u84_rtc_toggle_dynm", xtal24M, 0, 199 199 + EIC7700_REG_OFFSET_RTC, 16, 5, 200 200 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 201 201 + ESWIN_DIV(EIC7700_CLK_DIV_NOC_WDREF_DYNM, "divider_noc_wdref_dynm", 202 202 + xtal24M, 0, EIC7700_REG_OFFSET_NOC, 4, 16, 203 203 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 204 204 + }; 205 205 + 206 206 + /* gate clocks */ 207 207 + static struct eswin_gate_clock eic7700_gate_clks[] = { 208 208 + ESWIN_GATE(EIC7700_CLK_GATE_GPU_GRAY_CLK, "gate_gpu_gray_clk", xtal24M, 209 209 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_GRAY, 31, 0), 210 210 + ESWIN_GATE(EIC7700_CLK_GATE_VI_PHY_CFG, "gate_vi_phy_cfg", xtal24M, 211 211 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 1, 0), 212 212 + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_0, "gate_time_clk_0", xtal24M, 213 213 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 0, 0), 214 214 + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_1, "gate_time_clk_1", xtal24M, 215 215 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 1, 0), 216 216 + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_2, "gate_time_clk_2", xtal24M, 217 217 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 2, 0), 218 218 + ESWIN_GATE(EIC7700_CLK_GATE_TIMER_CLK_3, "gate_time_clk_3", xtal24M, 219 219 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 3, 0), 220 220 + }; 221 221 + 222 222 + /* Define the early clocks as the parent clocks of the mux clocks. */ 223 223 + static struct eswin_clk_info eic7700_early_clks[] = { 224 224 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6, 225 225 + "fixed_factor_hsp_rmii_ref_div6", 226 226 + EIC7700_CLK_SPLL1_FOUT2, 1, 6, 0), 227 227 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM, 228 228 + "divider_npu_llc_src0_div_dynm", 229 229 + EIC7700_CLK_SPLL0_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC, 230 230 + 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 231 231 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM, 232 232 + "divider_npu_llc_src1_div_dynm", 233 233 + EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NPU_LLC, 234 234 + 8, 4, 0, ESWIN_PRIV_DIV_MIN_2), 235 235 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPLL0_FOUT2, "gate_clk_spll0_fout2", 236 236 + EIC7700_CLK_SPLL0_FOUT2, 237 237 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 238 238 + EIC7700_REG_OFFSET_SPLL0_CFG_2, 31, 0), 239 239 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_BOOTSPI_DYNM, "divider_bootspi_div_dynm", 240 240 + EIC7700_CLK_GATE_SPLL0_FOUT2, 0, 241 241 + EIC7700_REG_OFFSET_BOOTSPI, 4, 6, 0, 242 242 + ESWIN_PRIV_DIV_MIN_2), 243 243 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SCPU_CORE_DYNM, 244 244 + "divider_scpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, 245 245 + EIC7700_REG_OFFSET_SCPU_CORE, 4, 4, 0, 246 246 + ESWIN_PRIV_DIV_MIN_2), 247 247 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_LPCPU_CORE_DYNM, 248 248 + "divider_lpcpu_core_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 249 249 + 0, EIC7700_REG_OFFSET_LPCPU_CORE, 4, 4, 0, 250 250 + ESWIN_PRIV_DIV_MIN_2), 251 251 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_MCLK_DYNM, "divider_vo_mclk_div_dynm", 252 252 + EIC7700_CLK_APLL_FOUT1, 0, EIC7700_REG_OFFSET_VO_MCLK, 4, 253 253 + 8, 0, ESWIN_PRIV_DIV_MIN_2), 254 254 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AONDMA_AXI_DYNM, 255 255 + "divider_aondma_axi_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 256 256 + 0, EIC7700_REG_OFFSET_AON_DMA, 4, 4, 0, 257 257 + ESWIN_PRIV_DIV_MIN_2), 258 258 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SATA_PHY_REF_DYNM, 259 259 + "divider_sata_phy_ref_div_dynm", 260 260 + EIC7700_CLK_SPLL1_FOUT2, 0, EIC7700_REG_OFFSET_SATA_OOB, 261 261 + 0, 4, 0, ESWIN_PRIV_DIV_MIN_2), 262 262 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_SYS_CFG_DYNM, "divider_sys_cfg_div_dynm", 263 263 + EIC7700_CLK_SPLL0_FOUT3, 0, EIC7700_REG_OFFSET_SYSCFG, 4, 264 264 + 3, 0, ESWIN_PRIV_DIV_MIN_2), 265 265 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2, 266 266 + "fixed_factor_u84_core_lp_div2", 267 267 + EIC7700_CLK_GATE_SPLL0_FOUT2, 1, 2, 0), 268 268 + }; 269 269 + 270 270 + static const struct clk_parent_data dsp_aclk_root_2mux1_gfree_mux_p[] = { 271 271 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 272 272 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 273 273 + }; 274 274 + 275 275 + static const struct clk_parent_data d2d_aclk_root_2mux1_gfree_mux_p[] = { 276 276 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 277 277 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 278 278 + }; 279 279 + 280 280 + static const struct clk_parent_data ddr_aclk_root_2mux1_gfree_mux_p[] = { 281 281 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 282 282 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 283 283 + }; 284 284 + 285 285 + static const struct clk_parent_data mshcore_root_3mux1_0_mux_p[] = { 286 286 + { .hw = &eic7700_fixed_rate_clks[3].hw }, 287 287 + { .hw = &eic7700_fixed_rate_clks[9].hw }, 288 288 + }; 289 289 + 290 290 + static const struct clk_parent_data mshcore_root_3mux1_1_mux_p[] = { 291 291 + { .hw = &eic7700_fixed_rate_clks[3].hw }, 292 292 + { .hw = &eic7700_fixed_rate_clks[9].hw }, 293 293 + }; 294 294 + 295 295 + static const struct clk_parent_data mshcore_root_3mux1_2_mux_p[] = { 296 296 + { .hw = &eic7700_fixed_rate_clks[3].hw }, 297 297 + { .hw = &eic7700_fixed_rate_clks[9].hw }, 298 298 + }; 299 299 + 300 300 + static const struct clk_parent_data npu_core_3mux1_gfree_mux_p[] = { 301 301 + { .hw = &eic7700_fixed_rate_clks[4].hw }, 302 302 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 303 303 + { .hw = &eic7700_fixed_rate_clks[8].hw }, 304 304 + }; 305 305 + 306 306 + static const struct clk_parent_data npu_e31_3mux1_gfree_mux_p[] = { 307 307 + { .hw = &eic7700_fixed_rate_clks[4].hw }, 308 308 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 309 309 + { .hw = &eic7700_fixed_rate_clks[8].hw }, 310 310 + }; 311 311 + 312 312 + static const struct clk_parent_data vi_aclk_root_2mux1_gfree_mux_p[] = { 313 313 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 314 314 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 315 315 + }; 316 316 + 317 317 + static const struct clk_parent_data mux_vi_dw_root_2mux1_p[] = { 318 318 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 319 319 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 320 320 + }; 321 321 + 322 322 + static const struct clk_parent_data mux_vi_dvp_root_2mux1_gfree_p[] = { 323 323 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 324 324 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 325 325 + }; 326 326 + 327 327 + static const struct clk_parent_data mux_vi_dig_isp_root_2mux1_gfree_p[] = { 328 328 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 329 329 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 330 330 + }; 331 331 + 332 332 + static const struct clk_parent_data mux_vo_aclk_root_2mux1_gfree_p[] = { 333 333 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 334 334 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 335 335 + }; 336 336 + 337 337 + static const struct clk_parent_data mux_vo_pixel_root_2mux1_p[] = { 338 338 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 339 339 + { .hw = &eic7700_fixed_rate_clks[8].hw }, 340 340 + }; 341 341 + 342 342 + static const struct clk_parent_data mux_vcdec_root_2mux1_gfree_p[] = { 343 343 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 344 344 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 345 345 + }; 346 346 + 347 347 + static const struct clk_parent_data mux_vcaclk_root_2mux1_gfree_p[] = { 348 348 + { .hw = &eic7700_fixed_rate_clks[1].hw }, 349 349 + { .hw = &eic7700_fixed_rate_clks[7].hw }, 350 350 + }; 351 351 + 352 352 + static const struct clk_parent_data npu_llclk_3mux1_gfree_mux_p[] = { 353 353 + { .hw = &eic7700_early_clks[1].hw }, 354 354 + { .hw = &eic7700_early_clks[2].hw }, 355 355 + { .hw = &eic7700_fixed_rate_clks[10].hw }, 356 356 + }; 357 357 + 358 358 + static const struct clk_parent_data mux_bootspi_clk_2mux1_gfree_p[] = { 359 359 + { .hw = &eic7700_early_clks[4].hw }, 360 360 + { .index = 0 }, 361 361 + }; 362 362 + 363 363 + static const struct clk_parent_data mux_scpu_core_clk_2mux1_gfree_p[] = { 364 364 + { .hw = &eic7700_early_clks[5].hw }, 365 365 + { .index = 0 }, 366 366 + }; 367 367 + 368 368 + static const struct clk_parent_data mux_lpcpu_core_clk_2mux1_gfree_p[] = { 369 369 + { .hw = &eic7700_early_clks[6].hw }, 370 370 + { .index = 0 }, 371 371 + }; 372 372 + 373 373 + static const struct clk_parent_data mux_vo_mclk_2mux_ext_mclk_p[] = { 374 374 + { .hw = &eic7700_early_clks[7].hw }, 375 375 + { .hw = &eic7700_fixed_rate_clks[15].hw }, 376 376 + }; 377 377 + 378 378 + static const struct clk_parent_data mux_aondma_axi2mux1_gfree_p[] = { 379 379 + { .hw = &eic7700_early_clks[8].hw }, 380 380 + { .index = 0 }, 381 381 + }; 382 382 + 383 383 + static const struct clk_parent_data mux_rmii_ref_2mux1_p[] = { 384 384 + { .hw = &eic7700_early_clks[0].hw }, 385 385 + { .hw = &eic7700_fixed_rate_clks[16].hw }, 386 386 + }; 387 387 + 388 388 + static const struct clk_parent_data mux_eth_core_2mux1_p[] = { 389 389 + { .hw = &eic7700_fixed_rate_clks[6].hw }, 390 390 + { .hw = &eic7700_fixed_rate_clks[16].hw }, 391 391 + }; 392 392 + 393 393 + static const struct clk_parent_data mux_sata_phy_2mux1_p[] = { 394 394 + { .hw = &eic7700_early_clks[9].hw }, 395 395 + { .hw = &eic7700_fixed_rate_clks[16].hw }, 396 396 + }; 397 397 + 398 398 + static const struct clk_parent_data mux_syscfg_clk_root_2mux1_gfree_p[] = { 399 399 + { .hw = &eic7700_early_clks[10].hw }, 400 400 + { .index = 0 }, 401 401 + }; 402 402 + 403 403 + static const struct clk_parent_data mux_cpu_root_3mux1_gfree_p[] = { 404 404 + { .hw = &eic7700_pll_clks[1].hw }, 405 405 + { .hw = &eic7700_early_clks[11].hw }, 406 406 + { .index = 0 }, 407 407 + }; 408 408 + 409 409 + static struct eswin_mux_clock eic7700_mux_clks[] = { 410 410 + ESWIN_MUX(EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 411 411 + "mux_cpu_root_3mux1_gfree", mux_cpu_root_3mux1_gfree_p, 412 412 + ARRAY_SIZE(mux_cpu_root_3mux1_gfree_p), 413 413 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 0, 2, 414 414 + CLK_MUX_ROUND_CLOSEST), 415 415 + ESWIN_MUX(EIC7700_CLK_MUX_RMII_REF_2MUX, "mux_rmii_ref_2mux1", 416 416 + mux_rmii_ref_2mux1_p, ARRAY_SIZE(mux_rmii_ref_2mux1_p), 417 417 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 2, 1, 418 418 + CLK_MUX_ROUND_CLOSEST), 419 419 + ESWIN_MUX(EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 420 420 + "mux_dsp_aclk_root_2mux1_gfree", 421 421 + dsp_aclk_root_2mux1_gfree_mux_p, 422 422 + ARRAY_SIZE(dsp_aclk_root_2mux1_gfree_mux_p), 423 423 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_ACLK, 0, 1, 424 424 + CLK_MUX_ROUND_CLOSEST), 425 425 + ESWIN_MUX(EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 426 426 + "mux_d2d_aclk_root_2mux1_gfree", 427 427 + d2d_aclk_root_2mux1_gfree_mux_p, 428 428 + ARRAY_SIZE(d2d_aclk_root_2mux1_gfree_mux_p), 429 429 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_ACLK, 0, 1, 430 430 + CLK_MUX_ROUND_CLOSEST), 431 431 + ESWIN_MUX(EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 432 432 + "mux_ddr_aclk_root_2mux1_gfree", 433 433 + ddr_aclk_root_2mux1_gfree_mux_p, 434 434 + ARRAY_SIZE(ddr_aclk_root_2mux1_gfree_mux_p), 435 435 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 16, 1, 436 436 + CLK_MUX_ROUND_CLOSEST), 437 437 + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, 438 438 + "mux_mshcore_root_3mux1_0", mshcore_root_3mux1_0_mux_p, 439 439 + ARRAY_SIZE(mshcore_root_3mux1_0_mux_p), CLK_SET_RATE_PARENT, 440 440 + EIC7700_REG_OFFSET_MSHC0_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), 441 441 + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, 442 442 + "mux_mshcore_root_3mux1_1", mshcore_root_3mux1_1_mux_p, 443 443 + ARRAY_SIZE(mshcore_root_3mux1_1_mux_p), CLK_SET_RATE_PARENT, 444 444 + EIC7700_REG_OFFSET_MSHC1_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), 445 445 + ESWIN_MUX(EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, 446 446 + "mux_mshcore_root_3mux1_2", mshcore_root_3mux1_2_mux_p, 447 447 + ARRAY_SIZE(mshcore_root_3mux1_2_mux_p), CLK_SET_RATE_PARENT, 448 448 + EIC7700_REG_OFFSET_MSHC2_CORE, 0, 1, CLK_MUX_ROUND_CLOSEST), 449 449 + ESWIN_MUX(EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, 450 450 + "mux_npu_llclk_3mux1_gfree", npu_llclk_3mux1_gfree_mux_p, 451 451 + ARRAY_SIZE(npu_llclk_3mux1_gfree_mux_p), 452 452 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 0, 2, 453 453 + CLK_MUX_ROUND_CLOSEST), 454 454 + ESWIN_MUX(EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, 455 455 + "mux_npu_core_3mux1_gfree", npu_core_3mux1_gfree_mux_p, 456 456 + ARRAY_SIZE(npu_core_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, 457 457 + EIC7700_REG_OFFSET_NPU_CORE, 0, 2, CLK_MUX_ROUND_CLOSEST), 458 458 + ESWIN_MUX(EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 459 459 + "mux_npu_e31_3mux1_gfree", npu_e31_3mux1_gfree_mux_p, 460 460 + ARRAY_SIZE(npu_e31_3mux1_gfree_mux_p), CLK_SET_RATE_PARENT, 461 461 + EIC7700_REG_OFFSET_NPU_CORE, 8, 2, CLK_MUX_ROUND_CLOSEST), 462 462 + ESWIN_MUX(EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 463 463 + "mux_vi_aclk_root_2mux1_gfree", 464 464 + vi_aclk_root_2mux1_gfree_mux_p, 465 465 + ARRAY_SIZE(vi_aclk_root_2mux1_gfree_mux_p), 466 466 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 0, 1, 467 467 + CLK_MUX_ROUND_CLOSEST), 468 468 + ESWIN_MUX(EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, "mux_vi_dw_root_2mux1", 469 469 + mux_vi_dw_root_2mux1_p, ARRAY_SIZE(mux_vi_dw_root_2mux1_p), 470 470 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DWCLK, 0, 1, 471 471 + CLK_MUX_ROUND_CLOSEST), 472 472 + ESWIN_MUX(EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 473 473 + "mux_vi_dvp_root_2mux1_gfree", 474 474 + mux_vi_dvp_root_2mux1_gfree_p, 475 475 + ARRAY_SIZE(mux_vi_dvp_root_2mux1_gfree_p), 476 476 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DVP, 0, 1, 477 477 + CLK_MUX_ROUND_CLOSEST), 478 478 + ESWIN_MUX(EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 479 479 + "mux_vi_dig_isp_root_2mux1_gfree", 480 480 + mux_vi_dig_isp_root_2mux1_gfree_p, 481 481 + ARRAY_SIZE(mux_vi_dig_isp_root_2mux1_gfree_p), 482 482 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_DIG_ISP, 0, 1, 483 483 + CLK_MUX_ROUND_CLOSEST), 484 484 + ESWIN_MUX(EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 485 485 + "mux_vo_aclk_root_2mux1_gfree", 486 486 + mux_vo_aclk_root_2mux1_gfree_p, 487 487 + ARRAY_SIZE(mux_vo_aclk_root_2mux1_gfree_p), 488 488 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 0, 1, 489 489 + CLK_MUX_ROUND_CLOSEST), 490 490 + ESWIN_MUX(EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 491 491 + "mux_vo_pixel_root_2mux1", mux_vo_pixel_root_2mux1_p, 492 492 + ARRAY_SIZE(mux_vo_pixel_root_2mux1_p), CLK_SET_RATE_PARENT, 493 493 + EIC7700_REG_OFFSET_VO_PIXEL, 0, 1, CLK_MUX_ROUND_CLOSEST), 494 494 + ESWIN_MUX(EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 495 495 + "mux_vcdec_root_2mux1_gfree", mux_vcdec_root_2mux1_gfree_p, 496 496 + ARRAY_SIZE(mux_vcdec_root_2mux1_gfree_p), 497 497 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VCDEC_ROOT, 0, 1, 498 498 + CLK_MUX_ROUND_CLOSEST), 499 499 + ESWIN_MUX(EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 500 500 + "mux_vcaclk_root_2mux1_gfree", 501 501 + mux_vcaclk_root_2mux1_gfree_p, 502 502 + ARRAY_SIZE(mux_vcaclk_root_2mux1_gfree_p), 503 503 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_ACLK, 0, 1, 504 504 + CLK_MUX_ROUND_CLOSEST), 505 505 + ESWIN_MUX(EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 506 506 + "mux_syscfg_clk_root_2mux1_gfree", 507 507 + mux_syscfg_clk_root_2mux1_gfree_p, 508 508 + ARRAY_SIZE(mux_syscfg_clk_root_2mux1_gfree_p), 509 509 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SYSCFG, 0, 1, 510 510 + CLK_MUX_ROUND_CLOSEST), 511 511 + ESWIN_MUX(EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, 512 512 + "mux_bootspi_clk_2mux1_gfree", 513 513 + mux_bootspi_clk_2mux1_gfree_p, 514 514 + ARRAY_SIZE(mux_bootspi_clk_2mux1_gfree_p), 515 515 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 0, 1, 516 516 + CLK_MUX_ROUND_CLOSEST), 517 517 + ESWIN_MUX(EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 518 518 + "mux_scpu_core_clk_2mux1_gfree", 519 519 + mux_scpu_core_clk_2mux1_gfree_p, 520 520 + ARRAY_SIZE(mux_scpu_core_clk_2mux1_gfree_p), 521 521 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 0, 1, 522 522 + CLK_MUX_ROUND_CLOSEST), 523 523 + ESWIN_MUX(EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 524 524 + "mux_lpcpu_core_clk_2mux1_gfree", 525 525 + mux_lpcpu_core_clk_2mux1_gfree_p, 526 526 + ARRAY_SIZE(mux_lpcpu_core_clk_2mux1_gfree_p), 527 527 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 0, 1, 528 528 + CLK_MUX_ROUND_CLOSEST), 529 529 + ESWIN_MUX(EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, 530 530 + "mux_vo_mclk_2mux_ext_mclk", mux_vo_mclk_2mux_ext_mclk_p, 531 531 + ARRAY_SIZE(mux_vo_mclk_2mux_ext_mclk_p), 532 532 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 0, 1, 533 533 + CLK_MUX_ROUND_CLOSEST), 534 534 + ESWIN_MUX(EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, 535 535 + "mux_aondma_axi2mux1_gfree", mux_aondma_axi2mux1_gfree_p, 536 536 + ARRAY_SIZE(mux_aondma_axi2mux1_gfree_p), 537 537 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 0, 1, 538 538 + CLK_MUX_ROUND_CLOSEST), 539 539 + ESWIN_MUX(EIC7700_CLK_MUX_ETH_CORE_2MUX1, "mux_eth_core_2mux1", 540 540 + mux_eth_core_2mux1_p, ARRAY_SIZE(mux_eth_core_2mux1_p), 541 541 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_ETH0, 1, 1, 542 542 + CLK_MUX_ROUND_CLOSEST), 543 543 + ESWIN_MUX(EIC7700_CLK_MUX_SATA_PHY_2MUX1, "mux_sata_phy_2mux1", 544 544 + mux_sata_phy_2mux1_p, ARRAY_SIZE(mux_sata_phy_2mux1_p), 545 545 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 9, 1, 546 546 + CLK_MUX_ROUND_CLOSEST), 547 547 + }; 548 548 + 549 549 + static const struct clk_parent_data mux_cpu_aclk_2mux1_gfree_p[] = { 550 550 + { .hw = &eic7700_mux_clks[1].hw }, 551 551 + { .hw = &eic7700_mux_clks[0].hw }, 552 552 + }; 553 553 + 554 554 + static struct eswin_clk_info eic7700_clks[] = { 555 555 + ESWIN_MUX_TYPE(EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, 556 556 + "mux_cpu_aclk_2mux1_gfree", mux_cpu_aclk_2mux1_gfree_p, 557 557 + ARRAY_SIZE(mux_cpu_aclk_2mux1_gfree_p), 558 558 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 20, 1, 559 559 + CLK_MUX_ROUND_CLOSEST, NULL), 560 560 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_COM_CLK, 561 561 + "gate_clk_cpu_trace_com_clk", 562 562 + EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE, 563 563 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 23, 0), 564 564 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_CPU_DIV2, 565 565 + "fixed_factor_cpu_div2", 566 566 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 1, 2, 0), 567 567 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, 568 568 + "fixed_factor_mipi_txesc_div10", 569 569 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 10, 570 570 + 0), 571 571 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, 572 572 + "fixed_factor_scpu_bus_div2", 573 573 + EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0), 574 574 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, 575 575 + "fixed_factor_lpcpu_bus_div2", 576 576 + EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 1, 2, 0), 577 577 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, 578 578 + "fixed_factor_pcie_cr_div2", 579 579 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 2, 0), 580 580 + ESWIN_FACTOR_TYPE(EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, 581 581 + "fixed_factor_pcie_aux_div4", 582 582 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1, 4, 0), 583 583 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_D2D_ACLK_DYNM, 584 584 + "divider_d2d_aclk_div_dynm", 585 585 + EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE, 0, 586 586 + EIC7700_REG_OFFSET_D2D_ACLK, 4, 4, 0, 587 587 + ESWIN_PRIV_DIV_MIN_2), 588 588 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_ACLK_DYNM, 589 589 + "divider_dsp_aclk_div_dynm", 590 590 + EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0, 591 591 + EIC7700_REG_OFFSET_DSP_ACLK, 4, 4, 0, 592 592 + ESWIN_PRIV_DIV_MIN_2), 593 593 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DDR_ACLK_DYNM, 594 594 + "divider_ddr_aclk_div_dynm", 595 595 + EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE, 0, 596 596 + EIC7700_REG_OFFSET_DDR, 20, 4, 0, ESWIN_PRIV_DIV_MIN_2), 597 597 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, 598 598 + "divider_eth_txclk_div_dynm_0", 599 599 + EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0, 600 600 + EIC7700_REG_OFFSET_ETH0, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2), 601 601 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, 602 602 + "divider_eth_txclk_div_dynm_1", 603 603 + EIC7700_CLK_MUX_ETH_CORE_2MUX1, 0, 604 604 + EIC7700_REG_OFFSET_ETH1, 4, 7, 0, ESWIN_PRIV_DIV_MIN_2), 605 605 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, 606 606 + "divider_mshc_core_div_dynm_0", 607 607 + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0, 608 608 + 0, EIC7700_REG_OFFSET_MSHC0_CORE, 4, 12, 609 609 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 610 610 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, 611 611 + "divider_mshc_core_div_dynm_1", 612 612 + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1, 613 613 + 0, EIC7700_REG_OFFSET_MSHC1_CORE, 4, 12, 614 614 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 615 615 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, 616 616 + "divider_mshc_core_div_dynm_2", 617 617 + EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2, 618 618 + 0, EIC7700_REG_OFFSET_MSHC2_CORE, 4, 12, 619 619 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 620 620 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_CORECLK_DYNM, 621 621 + "divider_npu_coreclk_div_dynm", 622 622 + EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE, 623 623 + 0, EIC7700_REG_OFFSET_NPU_CORE, 4, 4, 624 624 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 625 625 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_E31_DYNM, "divider_npu_e31_div_dynm", 626 626 + EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE, 0, 627 627 + EIC7700_REG_OFFSET_NPU_CORE, 12, 4, 628 628 + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 0), 629 629 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_ACLK_DYNM, "divider_vi_aclk_div_dynm", 630 630 + EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE, 0, 631 631 + EIC7700_REG_OFFSET_VI_ACLK, 4, 4, 0, 632 632 + ESWIN_PRIV_DIV_MIN_2), 633 633 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DW_DYNM, "divider_vi_dw_div_dynm", 634 634 + EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1, 0, 635 635 + EIC7700_REG_OFFSET_VI_DWCLK, 4, 4, 0, 636 636 + ESWIN_PRIV_DIV_MIN_2), 637 637 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DVP_DYNM, "divider_vi_dvp_div_dynm", 638 638 + EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE, 0, 639 639 + EIC7700_REG_OFFSET_VI_DVP, 4, 4, 0, 640 640 + ESWIN_PRIV_DIV_MIN_2), 641 641 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, 642 642 + "divider_vi_dig_isp_div_dynm", 643 643 + EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE, 0, 644 644 + EIC7700_REG_OFFSET_VI_DIG_ISP, 4, 4, 0, 645 645 + ESWIN_PRIV_DIV_MIN_2), 646 646 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_ACLK_DYNM, "divider_vo_aclk_div_dynm", 647 647 + EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE, 0, 648 648 + EIC7700_REG_OFFSET_VO_ACLK, 4, 4, 0, 649 649 + ESWIN_PRIV_DIV_MIN_2), 650 650 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_PIXEL_DYNM, 651 651 + "divider_vo_pixel_div_dynm", 652 652 + EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1, 0, 653 653 + EIC7700_REG_OFFSET_VO_PIXEL, 4, 6, 0, 654 654 + ESWIN_PRIV_DIV_MIN_2), 655 655 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VC_ACLK_DYNM, "divider_vc_aclk_div_dynm", 656 656 + EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE, 0, 657 657 + EIC7700_REG_OFFSET_VC_ACLK, 4, 4, 0, 658 658 + ESWIN_PRIV_DIV_MIN_2), 659 659 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JD_DYNM, "divider_jd_div_dynm", 660 660 + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, 661 661 + EIC7700_REG_OFFSET_JD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 662 662 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_JE_DYNM, "divider_je_div_dynm", 663 663 + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, 664 664 + EIC7700_REG_OFFSET_JE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 665 665 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VE_DYNM, "divider_ve_div_dynm", 666 666 + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, 667 667 + EIC7700_REG_OFFSET_VE, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 668 668 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VD_DYNM, "divider_vd_div_dynm", 669 669 + EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE, 0, 670 670 + EIC7700_REG_OFFSET_VD, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 671 671 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_G2D_DYNM, "divider_g2d_div_dynm", 672 672 + EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE, 0, 673 673 + EIC7700_REG_OFFSET_G2D, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 674 674 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NOC_NSP_DYNM, "divider_noc_nsp_div_dynm", 675 675 + EIC7700_CLK_SPLL2_FOUT1, 0, EIC7700_REG_OFFSET_NOC, 0, 3, 676 676 + 0, ESWIN_PRIV_DIV_MIN_2), 677 677 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_GPU_ACLK_DYNM, 678 678 + "divider_gpu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, 679 679 + EIC7700_REG_OFFSET_GPU_ACLK, 4, 4, 0, 680 680 + ESWIN_PRIV_DIV_MIN_2), 681 681 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_HSP_ACLK_DYNM, 682 682 + "divider_hsp_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, 683 683 + EIC7700_REG_OFFSET_HSP_ACLK, 4, 4, 0, 684 684 + ESWIN_PRIV_DIV_MIN_2), 685 685 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_PCIE_ACLK_DYNM, 686 686 + "divider_pcie_aclk_div_dynm", EIC7700_CLK_SPLL2_FOUT2, 0, 687 687 + EIC7700_REG_OFFSET_PCIE_ACLK, 4, 4, 0, 688 688 + ESWIN_PRIV_DIV_MIN_2), 689 689 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_NPU_ACLK_DYNM, 690 690 + "divider_npu_aclk_div_dynm", EIC7700_CLK_SPLL0_FOUT1, 0, 691 691 + EIC7700_REG_OFFSET_NPU_ACLK, 4, 4, 0, 692 692 + ESWIN_PRIV_DIV_MIN_2), 693 693 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, 694 694 + "divider_vi_shutter_div_dynm_0", 695 695 + EIC7700_CLK_VPLL_FOUT2, 0, 696 696 + EIC7700_REG_OFFSET_VI_SHUTTER0, 4, 7, 0, 697 697 + ESWIN_PRIV_DIV_MIN_2), 698 698 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, 699 699 + "divider_vi_shutter_div_dynm_1", 700 700 + EIC7700_CLK_VPLL_FOUT2, 0, 701 701 + EIC7700_REG_OFFSET_VI_SHUTTER1, 4, 7, 0, 702 702 + ESWIN_PRIV_DIV_MIN_2), 703 703 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, 704 704 + "divider_vi_shutter_div_dynm_2", 705 705 + EIC7700_CLK_VPLL_FOUT2, 0, 706 706 + EIC7700_REG_OFFSET_VI_SHUTTER2, 4, 7, 0, 707 707 + ESWIN_PRIV_DIV_MIN_2), 708 708 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, 709 709 + "divider_vi_shutter_div_dynm_3", 710 710 + EIC7700_CLK_VPLL_FOUT2, 0, 711 711 + EIC7700_REG_OFFSET_VI_SHUTTER3, 4, 7, 0, 712 712 + ESWIN_PRIV_DIV_MIN_2), 713 713 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, 714 714 + "divider_vi_shutter_div_dynm_4", 715 715 + EIC7700_CLK_VPLL_FOUT2, 0, 716 716 + EIC7700_REG_OFFSET_VI_SHUTTER4, 4, 7, 0, 717 717 + ESWIN_PRIV_DIV_MIN_2), 718 718 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, 719 719 + "divider_vi_shutter_div_dynm_5", 720 720 + EIC7700_CLK_VPLL_FOUT2, 0, 721 721 + EIC7700_REG_OFFSET_VI_SHUTTER5, 4, 7, 0, 722 722 + ESWIN_PRIV_DIV_MIN_2), 723 723 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_IESMCLK_DYNM, "divider_iesmclk_div_dynm", 724 724 + EIC7700_CLK_SPLL0_FOUT3, 0, 725 725 + EIC7700_REG_OFFSET_VO_IESMCLK, 4, 4, 0, 726 726 + ESWIN_PRIV_DIV_MIN_2), 727 727 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_VO_CEC_DYNM, "divider_vo_cec_div_dynm", 728 728 + EIC7700_CLK_VPLL_FOUT2, 0, 729 729 + EIC7700_REG_OFFSET_VO_PHY_CLK, 16, 16, 0, 730 730 + ESWIN_PRIV_DIV_MIN_2), 731 731 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_CRYPTO_DYNM, "divider_crypto_div_dynm", 732 732 + EIC7700_CLK_SPLL0_FOUT1, 0, 733 733 + EIC7700_REG_OFFSET_SPACC, 4, 4, 0, ESWIN_PRIV_DIV_MIN_2), 734 734 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_AON_RTC_DYNM, "divider_aon_rtc_div_dynm", 735 735 + EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24, 0, 736 736 + EIC7700_REG_OFFSET_RTC, 21, 11, 0, 737 737 + ESWIN_PRIV_DIV_MIN_2), 738 738 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_ACLK, "gate_dspt_aclk", 739 739 + EIC7700_CLK_DIV_DSP_ACLK_DYNM, CLK_SET_RATE_PARENT, 740 740 + EIC7700_REG_OFFSET_DSP_ACLK, 31, 0), 741 741 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_0_ACLK_DYNM, 742 742 + "divider_dsp_0_aclk_div_dynm", 743 743 + EIC7700_CLK_GATE_DSPT_ACLK, 0, 744 744 + EIC7700_REG_OFFSET_DSP_CFG, 19, 1, 0, 0), 745 745 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_1_ACLK_DYNM, 746 746 + "divider_dsp_1_aclk_div_dynm", 747 747 + EIC7700_CLK_GATE_DSPT_ACLK, 0, 748 748 + EIC7700_REG_OFFSET_DSP_CFG, 20, 1, 0, 0), 749 749 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_2_ACLK_DYNM, 750 750 + "divider_dsp_2_aclk_div_dynm", 751 751 + EIC7700_CLK_GATE_DSPT_ACLK, 0, 752 752 + EIC7700_REG_OFFSET_DSP_CFG, 21, 1, 0, 0), 753 753 + ESWIN_DIV_TYPE(EIC7700_CLK_DIV_DSP_3_ACLK_DYNM, 754 754 + "divider_dsp_3_aclk_div_dynm", 755 755 + EIC7700_CLK_GATE_DSPT_ACLK, 0, 756 756 + EIC7700_REG_OFFSET_DSP_CFG, 22, 1, 0, 0), 757 757 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0, 758 758 + "gate_clk_cpu_ext_src_core_clk_0", 759 759 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 760 760 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 761 761 + EIC7700_REG_OFFSET_U84, 28, 0), 762 762 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1, 763 763 + "gate_clk_cpu_ext_src_core_clk_1", 764 764 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 765 765 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 766 766 + EIC7700_REG_OFFSET_U84, 29, 0), 767 767 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2, 768 768 + "gate_clk_cpu_ext_src_core_clk_2", 769 769 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 770 770 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 771 771 + EIC7700_REG_OFFSET_U84, 30, 0), 772 772 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3, 773 773 + "gate_clk_cpu_ext_src_core_clk_3", 774 774 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 775 775 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 776 776 + EIC7700_REG_OFFSET_U84, 31, 0), 777 777 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_0, 778 778 + "gate_clk_cpu_trace_clk_0", 779 779 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 780 780 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 24, 0), 781 781 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_1, 782 782 + "gate_clk_cpu_trace_clk_1", 783 783 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 784 784 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 25, 0), 785 785 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_2, 786 786 + "gate_clk_cpu_trace_clk_2", 787 787 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 788 788 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 26, 0), 789 789 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CPU_TRACE_CLK_3, 790 790 + "gate_clk_cpu_trace_clk_3", 791 791 + EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE, 792 792 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_U84, 27, 0), 793 793 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_NSP_CLK, "gate_noc_nsp_clk", 794 794 + EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT, 795 795 + EIC7700_REG_OFFSET_NOC, 31, 0), 796 796 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI, "gate_clk_bootspi", 797 797 + EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE, 798 798 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI, 31, 0), 799 799 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_BOOTSPI_CFG, "gate_clk_bootspi_cfg", 800 800 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 801 801 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_BOOTSPI_CFGCLK, 802 802 + 31, 0), 803 803 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_CORE, "gate_clk_scpu_core", 804 804 + EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE, 805 805 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_CORE, 31, 806 806 + 0), 807 807 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SCPU_BUS, "gate_clk_scpu_bus", 808 808 + EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2, 809 809 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SCPU_BUSCLK, 31, 810 810 + 0), 811 811 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_CORE, "gate_clk_lpcpu_core", 812 812 + EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE, 813 813 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_CORE, 31, 814 814 + 0), 815 815 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LPCPU_BUS, "gate_clk_lpcpu_bus", 816 816 + EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2, 817 817 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LPCPU_BUSCLK, 818 818 + 31, 0), 819 819 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_ACLK, "gate_gpu_aclk", 820 820 + EIC7700_CLK_DIV_GPU_ACLK_DYNM, CLK_SET_RATE_PARENT, 821 821 + EIC7700_REG_OFFSET_GPU_ACLK, 31, 0), 822 822 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_GPU_CFG_CLK, "gate_gpu_cfg_clk", 823 823 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 824 824 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_GPU_CFG, 31, 0), 825 825 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DSPT_CFG_CLK, "gate_dspt_cfg_clk", 826 826 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 827 827 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DSP_CFG, 31, 0), 828 828 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_ACLK, "gate_d2d_aclk", 829 829 + EIC7700_CLK_DIV_D2D_ACLK_DYNM, CLK_SET_RATE_PARENT, 830 830 + EIC7700_REG_OFFSET_D2D_ACLK, 31, 0), 831 831 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_D2D_CFG_CLK, "gate_d2d_cfg_clk", 832 832 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 833 833 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_D2D_CFG, 31, 0), 834 834 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_ACLK, "gate_tcu_aclk", 835 835 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, 836 836 + EIC7700_REG_OFFSET_TCU_ACLK, 31, 0), 837 837 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TCU_CFG_CLK, "gate_tcu_cfg_clk", 838 838 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 839 839 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TCU_CFG, 31, 0), 840 840 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT_CFG_CLK, "gate_ddrt_cfg_clk", 841 841 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 842 842 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_DDR, 9, 0), 843 843 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P0_ACLK, "gate_ddrt0_p0_aclk", 844 844 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 845 845 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 846 846 + EIC7700_REG_OFFSET_DDR, 4, 0), 847 847 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P1_ACLK, "gate_ddrt0_p1_aclk", 848 848 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 849 849 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 850 850 + EIC7700_REG_OFFSET_DDR, 5, 0), 851 851 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P2_ACLK, "gate_ddrt0_p2_aclk", 852 852 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 853 853 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 854 854 + EIC7700_REG_OFFSET_DDR, 6, 0), 855 855 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P3_ACLK, "gate_ddrt0_p3_aclk", 856 856 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 857 857 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 858 858 + EIC7700_REG_OFFSET_DDR, 7, 0), 859 859 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT0_P4_ACLK, "gate_ddrt0_p4_aclk", 860 860 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 861 861 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 862 862 + EIC7700_REG_OFFSET_DDR, 8, 0), 863 863 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P0_ACLK, "gate_ddrt1_p0_aclk", 864 864 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 865 865 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 866 866 + EIC7700_REG_OFFSET_DDR1, 4, 0), 867 867 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P1_ACLK, "gate_ddrt1_p1_aclk", 868 868 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 869 869 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 870 870 + EIC7700_REG_OFFSET_DDR1, 5, 0), 871 871 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P2_ACLK, "gate_ddrt1_p2_aclk", 872 872 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 873 873 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 874 874 + EIC7700_REG_OFFSET_DDR1, 6, 0), 875 875 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P3_ACLK, "gate_ddrt1_p3_aclk", 876 876 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 877 877 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 878 878 + EIC7700_REG_OFFSET_DDR1, 7, 0), 879 879 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDRT1_P4_ACLK, "gate_ddrt1_p4_aclk", 880 880 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, 881 881 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 882 882 + EIC7700_REG_OFFSET_DDR1, 8, 0), 883 883 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ACLK, "gate_clk_hsp_aclk", 884 884 + EIC7700_CLK_DIV_HSP_ACLK_DYNM, CLK_SET_RATE_PARENT, 885 885 + EIC7700_REG_OFFSET_HSP_ACLK, 31, 0), 886 886 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_CFG_CLK, "gate_clk_hsp_cfg_clk", 887 887 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 888 888 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_CFG, 31, 0), 889 889 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_ACLK, "gate_pciet_aclk", 890 890 + EIC7700_CLK_DIV_PCIE_ACLK_DYNM, CLK_SET_RATE_PARENT, 891 891 + EIC7700_REG_OFFSET_PCIE_ACLK, 31, 0), 892 892 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CFG_CLK, "gate_pciet_cfg_clk", 893 893 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 894 894 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 31, 895 895 + 0), 896 896 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_CR_CLK, "gate_pciet_cr_clk", 897 897 + EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2, 898 898 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 0, 0), 899 899 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PCIET_AUX_CLK, "gate_pciet_aux_clk", 900 900 + EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4, 901 901 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PCIE_CFG, 1, 0), 902 902 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_ACLK, "gate_npu_aclk", 903 903 + EIC7700_CLK_DIV_NPU_ACLK_DYNM, CLK_SET_RATE_PARENT, 904 904 + EIC7700_REG_OFFSET_NPU_ACLK, 31, 0), 905 905 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CFG_CLK, "gate_npu_cfg_clk", 906 906 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 907 907 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_ACLK, 30, 908 908 + 0), 909 909 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_LLC_ACLK, "gate_npu_llc_aclk", 910 910 + EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE, 911 911 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_NPU_LLC, 31, 0), 912 912 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_CLK, "gate_npu_clk", 913 913 + EIC7700_CLK_DIV_NPU_CORECLK_DYNM, CLK_SET_RATE_PARENT, 914 914 + EIC7700_REG_OFFSET_NPU_CORE, 31, 0), 915 915 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NPU_E31_CLK, "gate_npu_e31_clk", 916 916 + EIC7700_CLK_DIV_NPU_E31_DYNM, CLK_SET_RATE_PARENT, 917 917 + EIC7700_REG_OFFSET_NPU_CORE, 30, 0), 918 918 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_ACLK, "gate_vi_aclk", 919 919 + EIC7700_CLK_DIV_VI_ACLK_DYNM, CLK_SET_RATE_PARENT, 920 920 + EIC7700_REG_OFFSET_VI_ACLK, 31, 0), 921 921 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_CFG_CLK, "gate_vi_cfg_clk", 922 922 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 923 923 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_ACLK, 30, 0), 924 924 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_DW_CLK, "gate_vi_dig_dw_clk", 925 925 + EIC7700_CLK_DIV_VI_DW_DYNM, CLK_SET_RATE_PARENT, 926 926 + EIC7700_REG_OFFSET_VI_DWCLK, 31, 0), 927 927 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DVP_CLK, "gate_vi_dvp_clk", 928 928 + EIC7700_CLK_DIV_VI_DVP_DYNM, CLK_SET_RATE_PARENT, 929 929 + EIC7700_REG_OFFSET_VI_DVP, 31, 0), 930 930 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_DIG_ISP_CLK, "gate_vi_dig_isp_clk", 931 931 + EIC7700_CLK_DIV_VI_DIG_ISP_DYNM, CLK_SET_RATE_PARENT, 932 932 + EIC7700_REG_OFFSET_VI_DIG_ISP, 31, 0), 933 933 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_0, "gate_vi_shutter_0", 934 934 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0, CLK_SET_RATE_PARENT, 935 935 + EIC7700_REG_OFFSET_VI_SHUTTER0, 31, 0), 936 936 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_1, "gate_vi_shutter_1", 937 937 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1, CLK_SET_RATE_PARENT, 938 938 + EIC7700_REG_OFFSET_VI_SHUTTER1, 31, 0), 939 939 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_2, "gate_vi_shutter_2", 940 940 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2, CLK_SET_RATE_PARENT, 941 941 + EIC7700_REG_OFFSET_VI_SHUTTER2, 31, 0), 942 942 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_3, "gate_vi_shutter_3", 943 943 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3, CLK_SET_RATE_PARENT, 944 944 + EIC7700_REG_OFFSET_VI_SHUTTER3, 31, 0), 945 945 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_4, "gate_vi_shutter_4", 946 946 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4, CLK_SET_RATE_PARENT, 947 947 + EIC7700_REG_OFFSET_VI_SHUTTER4, 31, 0), 948 948 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_SHUTTER_5, "gate_vi_shutter_5", 949 949 + EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5, CLK_SET_RATE_PARENT, 950 950 + EIC7700_REG_OFFSET_VI_SHUTTER5, 31, 0), 951 951 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VI_PHY_TXCLKESC, 952 952 + "gate_vi_phy_txclkesc", 953 953 + EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, 954 954 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VI_PHY, 0, 0), 955 955 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_ACLK, "gate_vo_aclk", 956 956 + EIC7700_CLK_DIV_VO_ACLK_DYNM, CLK_SET_RATE_PARENT, 957 957 + EIC7700_REG_OFFSET_VO_ACLK, 31, 0), 958 958 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CFG_CLK, "gate_vo_cfg_clk", 959 959 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 960 960 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_ACLK, 30, 0), 961 961 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_HDMI_IESMCLK, 962 962 + "gate_vo_hdmi_iesmclk", EIC7700_CLK_DIV_IESMCLK_DYNM, 963 963 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_IESMCLK, 31, 964 964 + 0), 965 965 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_PIXEL_CLK, "gate_vo_pixel_clk", 966 966 + EIC7700_CLK_DIV_VO_PIXEL_DYNM, CLK_SET_RATE_PARENT, 967 967 + EIC7700_REG_OFFSET_VO_PIXEL, 31, 0), 968 968 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_I2S_MCLK, "gate_vo_i2s_mclk", 969 969 + EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK, 970 970 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_MCLK, 31, 0), 971 971 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VO_CR_CLK, "gate_vo_cr_clk", 972 972 + EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10, 973 973 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VO_PHY_CLK, 1, 974 974 + 0), 975 975 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_ACLK, "gate_vc_aclk", 976 976 + EIC7700_CLK_DIV_VC_ACLK_DYNM, CLK_SET_RATE_PARENT, 977 977 + EIC7700_REG_OFFSET_VC_ACLK, 31, 0), 978 978 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_CFG_CLK, "gate_vc_cfg_clk", 979 979 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 980 980 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 0, 0), 981 981 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_CLK, "gate_vc_je_clk", 982 982 + EIC7700_CLK_DIV_JE_DYNM, CLK_SET_RATE_PARENT, 983 983 + EIC7700_REG_OFFSET_JE, 31, 0), 984 984 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_CLK, "gate_vc_jd_clk", 985 985 + EIC7700_CLK_DIV_JD_DYNM, CLK_SET_RATE_PARENT, 986 986 + EIC7700_REG_OFFSET_JD, 31, 0), 987 987 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_CLK, "gate_vc_ve_clk", 988 988 + EIC7700_CLK_DIV_VE_DYNM, CLK_SET_RATE_PARENT, 989 989 + EIC7700_REG_OFFSET_VE, 31, 0), 990 990 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_CLK, "gate_vc_vd_clk", 991 991 + EIC7700_CLK_DIV_VD_DYNM, CLK_SET_RATE_PARENT, 992 992 + EIC7700_REG_OFFSET_VD, 31, 0), 993 993 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CFG_CLK, "gate_g2d_cfg_clk", 994 994 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 995 995 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_G2D, 28, 0), 996 996 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_CLK, "gate_g2d_clk", 997 997 + EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT, 998 998 + EIC7700_REG_OFFSET_G2D, 30, 0), 999 999 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_G2D_ACLK, "gate_g2d_aclk", 1000 1000 + EIC7700_CLK_DIV_G2D_DYNM, CLK_SET_RATE_PARENT, 1001 1001 + EIC7700_REG_OFFSET_G2D, 31, 0), 1002 1002 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_CFG, "gate_clk_aondma_cfg", 1003 1003 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1004 1004 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 30, 0), 1005 1005 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AONDMA_ACLK, "gate_aondma_aclk", 1006 1006 + EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, 1007 1007 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 31, 0), 1008 1008 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_ACLK, "gate_aon_aclk", 1009 1009 + EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE, 1010 1010 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_AON_DMA, 29, 0), 1011 1011 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_0, "gate_timer_pclk_0", 1012 1012 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1013 1013 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 4, 0), 1014 1014 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_1, "gate_timer_pclk_1", 1015 1015 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1016 1016 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 5, 0), 1017 1017 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_2, "gate_timer_pclk_2", 1018 1018 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1019 1019 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 6, 0), 1020 1020 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER_PCLK_3, "gate_timer_pclk_3", 1021 1021 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1022 1022 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TIMER, 7, 0), 1023 1023 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TIMER3_CLK8, "gate_timer3_clk8", 1024 1024 + EIC7700_CLK_VPLL_FOUT3, CLK_SET_RATE_PARENT, 1025 1025 + EIC7700_REG_OFFSET_TIMER, 8, 0), 1026 1026 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC_CFG, "gate_clk_rtc_cfg", 1027 1027 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1028 1028 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_RTC, 2, 0), 1029 1029 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RTC, "gate_clk_rtc", 1030 1030 + EIC7700_CLK_DIV_AON_RTC_DYNM, CLK_SET_RATE_PARENT, 1031 1031 + EIC7700_REG_OFFSET_RTC, 1, 0), 1032 1032 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_0, "gate_hsp_rmii_ref_0", 1033 1033 + EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT, 1034 1034 + EIC7700_REG_OFFSET_ETH0, 31, 0), 1035 1035 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_RMII_REF_1, "gate_hsp_rmii_ref_1", 1036 1036 + EIC7700_CLK_MUX_RMII_REF_2MUX, CLK_SET_RATE_PARENT, 1037 1037 + EIC7700_REG_OFFSET_ETH1, 31, 0), 1038 1038 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_PKA_CFG, "gate_clk_pka_cfg", 1039 1039 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1040 1040 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_PKA, 31, 0), 1041 1041 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_SPACC_CFG, "gate_clk_spacc_cfg", 1042 1042 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1043 1043 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SPACC, 31, 0), 1044 1044 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_CRYPTO, "gate_clk_crypto", 1045 1045 + EIC7700_CLK_DIV_CRYPTO_DYNM, CLK_SET_RATE_PARENT, 1046 1046 + EIC7700_REG_OFFSET_SPACC, 30, 0), 1047 1047 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_TRNG_CFG, "gate_clk_trng_cfg", 1048 1048 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1049 1049 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_TRNG, 31, 0), 1050 1050 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_OTP_CFG, "gate_clk_otp_cfg", 1051 1051 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1052 1052 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_OTP, 31, 0), 1053 1053 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_0, "gate_clk_mailbox_0", 1054 1054 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1055 1055 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 0, 0), 1056 1056 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_1, "gate_clk_mailbox_1", 1057 1057 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1058 1058 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 1, 0), 1059 1059 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_2, "gate_clk_mailbox_2", 1060 1060 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1061 1061 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 2, 0), 1062 1062 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_3, "gate_clk_mailbox_3", 1063 1063 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1064 1064 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 3, 0), 1065 1065 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_4, "gate_clk_mailbox_4", 1066 1066 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1067 1067 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 4, 0), 1068 1068 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_5, "gate_clk_mailbox_5", 1069 1069 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1070 1070 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 5, 0), 1071 1071 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_6, "gate_clk_mailbox_6", 1072 1072 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1073 1073 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 6, 0), 1074 1074 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_7, "gate_clk_mailbox_7", 1075 1075 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1076 1076 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 7, 0), 1077 1077 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_8, "gate_clk_mailbox_8", 1078 1078 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1079 1079 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 8, 0), 1080 1080 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_9, "gate_clk_mailbox_9", 1081 1081 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1082 1082 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 9, 0), 1083 1083 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_10, "gate_clk_mailbox_10", 1084 1084 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1085 1085 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 10, 0), 1086 1086 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_11, "gate_clk_mailbox_11", 1087 1087 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1088 1088 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 11, 0), 1089 1089 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_12, "gate_clk_mailbox_12", 1090 1090 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1091 1091 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 12, 0), 1092 1092 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_13, "gate_clk_mailbox_13", 1093 1093 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1094 1094 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 13, 0), 1095 1095 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_14, "gate_clk_mailbox_14", 1096 1096 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1097 1097 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 14, 0), 1098 1098 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_MAILBOX_15, "gate_clk_mailbox_15", 1099 1099 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1100 1100 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN1, 15, 0), 1101 1101 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C0_PCLK, "gate_i2c0_pclk", 1102 1102 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1103 1103 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 7, 0), 1104 1104 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C1_PCLK, "gate_i2c1_pclk", 1105 1105 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1106 1106 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 8, 0), 1107 1107 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C2_PCLK, "gate_i2c2_pclk", 1108 1108 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1109 1109 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 9, 0), 1110 1110 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C3_PCLK, "gate_i2c3_pclk", 1111 1111 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1112 1112 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 10, 0), 1113 1113 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C4_PCLK, "gate_i2c4_pclk", 1114 1114 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1115 1115 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 11, 0), 1116 1116 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C5_PCLK, "gate_i2c5_pclk", 1117 1117 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1118 1118 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 12, 0), 1119 1119 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C6_PCLK, "gate_i2c6_pclk", 1120 1120 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1121 1121 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 13, 0), 1122 1122 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C7_PCLK, "gate_i2c7_pclk", 1123 1123 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1124 1124 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 14, 0), 1125 1125 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C8_PCLK, "gate_i2c8_pclk", 1126 1126 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1127 1127 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 15, 0), 1128 1128 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_I2C9_PCLK, "gate_i2c9_pclk", 1129 1129 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1130 1130 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 16, 0), 1131 1131 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT0_PCLK, "gate_lsp_wdt0_pclk", 1132 1132 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1133 1133 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 28, 0), 1134 1134 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT1_PCLK, "gate_lsp_wdt1_pclk", 1135 1135 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1136 1136 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 29, 0), 1137 1137 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT2_PCLK, "gate_lsp_wdt2_pclk", 1138 1138 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1139 1139 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 30, 0), 1140 1140 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_WDT3_PCLK, "gate_lsp_wdt3_pclk", 1141 1141 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1142 1142 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 31, 0), 1143 1143 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI0_PCLK, "gate_lsp_ssi0_pclk", 1144 1144 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1145 1145 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 26, 0), 1146 1146 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_SSI1_PCLK, "gate_lsp_ssi1_pclk", 1147 1147 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1148 1148 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 27, 0), 1149 1149 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART0_PCLK, "gate_lsp_uart0_pclk", 1150 1150 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1151 1151 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1152 1152 + EIC7700_REG_OFFSET_LSP_EN0, 17, 0), 1153 1153 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART1_PCLK, "gate_lsp_uart1_pclk", 1154 1154 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1155 1155 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 18, 0), 1156 1156 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART2_PCLK, "gate_lsp_uart2_pclk", 1157 1157 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1158 1158 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1159 1159 + EIC7700_REG_OFFSET_LSP_EN0, 19, 0), 1160 1160 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART3_PCLK, "gate_lsp_uart3_pclk", 1161 1161 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1162 1162 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 20, 0), 1163 1163 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_UART4_PCLK, "gate_lsp_uart4_pclk", 1164 1164 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1165 1165 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 21, 0), 1166 1166 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_TIMER_PCLK, "gate_lsp_timer_pclk", 1167 1167 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1168 1168 + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1169 1169 + EIC7700_REG_OFFSET_LSP_EN0, 25, 0), 1170 1170 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_FAN_PCLK, "gate_lsp_fan_pclk", 1171 1171 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1172 1172 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 0, 0), 1173 1173 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT_PCLK, "gate_lsp_pvt_pclk", 1174 1174 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1175 1175 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_LSP_EN0, 1, 0), 1176 1176 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT0_CLK, "gate_pvt0_clk", 1177 1177 + EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT, 1178 1178 + EIC7700_REG_OFFSET_LSP_EN1, 16, 0), 1179 1179 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_LSP_PVT1_CLK, "gate_pvt1_clk", 1180 1180 + EIC7700_CLK_FIXED_FACTOR_PVT_DIV20, CLK_SET_RATE_PARENT, 1181 1181 + EIC7700_REG_OFFSET_LSP_EN1, 17, 0), 1182 1182 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JE_PCLK, "gate_vc_je_pclk", 1183 1183 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1184 1184 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 2, 0), 1185 1185 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_JD_PCLK, "gate_vc_jd_pclk", 1186 1186 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1187 1187 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 1, 0), 1188 1188 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VE_PCLK, "gate_vc_ve_pclk", 1189 1189 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1190 1190 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 5, 0), 1191 1191 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_VD_PCLK, "gate_vc_vd_pclk", 1192 1192 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1193 1193 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 4, 0), 1194 1194 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_VC_MON_PCLK, "gate_vc_mon_pclk", 1195 1195 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1196 1196 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_VC_CLKEN, 3, 0), 1197 1197 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK, 1198 1198 + "gate_hsp_mshc0_core_clk", 1199 1199 + EIC7700_CLK_DIV_MSHC_CORE_DYNM_0, CLK_SET_RATE_PARENT, 1200 1200 + EIC7700_REG_OFFSET_MSHC0_CORE, 16, 0), 1201 1201 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK, 1202 1202 + "gate_hsp_mshc1_core_clk", 1203 1203 + EIC7700_CLK_DIV_MSHC_CORE_DYNM_1, CLK_SET_RATE_PARENT, 1204 1204 + EIC7700_REG_OFFSET_MSHC1_CORE, 16, 0), 1205 1205 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK, 1206 1206 + "gate_hsp_mshc2_core_clk", 1207 1207 + EIC7700_CLK_DIV_MSHC_CORE_DYNM_2, CLK_SET_RATE_PARENT, 1208 1208 + EIC7700_REG_OFFSET_MSHC2_CORE, 16, 0), 1209 1209 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_RBC_CLK, 1210 1210 + "gate_hsp_sata_rbc_clk", EIC7700_CLK_SPLL1_FOUT2, 1211 1211 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_RBC, 1212 1212 + 0, 0), 1213 1213 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_SATA_OOB_CLK, 1214 1214 + "gate_hsp_sata_oob_clk", EIC7700_CLK_MUX_SATA_PHY_2MUX1, 1215 1215 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_SATA_OOB, 31, 1216 1216 + 0), 1217 1217 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST, 1218 1218 + "gate_hsp_dma0_clk_test", EIC7700_CLK_GATE_HSP_ACLK, 1219 1219 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_HSP_ACLK, 1, 0), 1220 1220 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_DMA0_CLK, "gate_hsp_dma0_clk", 1221 1221 + EIC7700_CLK_GATE_HSP_ACLK, CLK_SET_RATE_PARENT, 1222 1222 + EIC7700_REG_OFFSET_HSP_ACLK, 0, 0), 1223 1223 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK, 1224 1224 + "gate_hsp_eth0_core_clk", 1225 1225 + EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0, CLK_SET_RATE_PARENT, 1226 1226 + EIC7700_REG_OFFSET_ETH0, 0, 0), 1227 1227 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK, 1228 1228 + "gate_hsp_eth1_core_clk", 1229 1229 + EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1, CLK_SET_RATE_PARENT, 1230 1230 + EIC7700_REG_OFFSET_ETH1, 0, 0), 1231 1231 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C0_PCLK, "gate_aon_i2c0_pclk", 1232 1232 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1233 1233 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C0, 31, 0), 1234 1234 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_AON_I2C1_PCLK, "gate_aon_i2c1_pclk", 1235 1235 + EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE, 1236 1236 + CLK_SET_RATE_PARENT, EIC7700_REG_OFFSET_I2C1, 31, 0), 1237 1237 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR0_TRACE, "gate_ddr0_trace", 1238 1238 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, 1239 1239 + EIC7700_REG_OFFSET_DDR, 0, 0), 1240 1240 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_DDR1_TRACE, "gate_ddr1_trace", 1241 1241 + EIC7700_CLK_DIV_DDR_ACLK_DYNM, CLK_SET_RATE_PARENT, 1242 1242 + EIC7700_REG_OFFSET_DDR1, 0, 0), 1243 1243 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_RNOC_NSP, "gate_rnoc_nsp", 1244 1244 + EIC7700_CLK_DIV_NOC_NSP_DYNM, CLK_SET_RATE_PARENT, 1245 1245 + EIC7700_REG_OFFSET_NOC, 29, 0), 1246 1246 + ESWIN_GATE_TYPE(EIC7700_CLK_GATE_NOC_WDREF, "gate_noc_wdref", 1247 1247 + EIC7700_CLK_DIV_NOC_WDREF_DYNM, CLK_SET_RATE_PARENT, 1248 1248 + EIC7700_REG_OFFSET_NOC, 30, 0), 1249 1249 + }; 1250 1250 + 1251 1251 + /* 1252 1252 + * This clock notifier is called when the rate of clk_pll_cpu clock is to be 1253 1253 + * changed. The mux_cpu_root_3mux1_gfree clock should save the current parent 1254 1254 + * clock and switch its parent clock to fixed_factor_u84_core_lp_div2 before 1255 1255 + * clk_pll_cpu rate will be changed. Then switch its parent clock back after 1256 1256 + * the clk_pll_cpu rate is completed. 1257 1257 + */ 1258 1258 + static int eic7700_clk_pll_cpu_notifier_cb(struct notifier_block *nb, 1259 1259 + unsigned long action, void *data) 1260 1260 + { 1261 1261 + struct eswin_clock_data *pdata; 1262 1262 + struct clk_hw *mux_clk; 1263 1263 + struct clk_hw *lp_clk; 1264 1264 + int ret = 0; 1265 1265 + 1266 1266 + pdata = container_of(nb, struct eswin_clock_data, pll_nb); 1267 1267 + 1268 1268 + mux_clk = &eic7700_mux_clks[0].hw; 1269 1269 + lp_clk = &eic7700_early_clks[11].hw; 1270 1270 + 1271 1271 + if (action == PRE_RATE_CHANGE) { 1272 1272 + pdata->original_clk = clk_hw_get_parent(mux_clk); 1273 1273 + ret = clk_hw_set_parent(mux_clk, lp_clk); 1274 1274 + } else if (action == POST_RATE_CHANGE) { 1275 1275 + ret = clk_hw_set_parent(mux_clk, pdata->original_clk); 1276 1276 + } 1277 1277 + 1278 1278 + return notifier_from_errno(ret); 1279 1279 + } 1280 1280 + 1281 1281 + static int eic7700_clk_probe(struct platform_device *pdev) 1282 1282 + { 1283 1283 + struct eswin_clock_data *clk_data; 1284 1284 + struct device *dev = &pdev->dev; 1285 1285 + struct clk *pll_clk; 1286 1286 + int ret; 1287 1287 + 1288 1288 + clk_data = eswin_clk_init(pdev, EIC7700_NR_CLKS); 1289 1289 + if (IS_ERR(clk_data)) 1290 1290 + return dev_err_probe(dev, PTR_ERR(clk_data), 1291 1291 + "failed to get clk data!\n"); 1292 1292 + 1293 1293 + ret = eswin_clk_register_fixed_rate(dev, eic7700_fixed_rate_clks, 1294 1294 + ARRAY_SIZE(eic7700_fixed_rate_clks), 1295 1295 + clk_data); 1296 1296 + if (ret) 1297 1297 + return dev_err_probe(dev, ret, 1298 1298 + "failed to register fixed rate clock\n"); 1299 1299 + 1300 1300 + ret = eswin_clk_register_pll(dev, eic7700_pll_clks, 1301 1301 + ARRAY_SIZE(eic7700_pll_clks), 1302 1302 + clk_data); 1303 1303 + if (ret) 1304 1304 + return dev_err_probe(dev, ret, 1305 1305 + "failed to register pll clock\n"); 1306 1306 + 1307 1307 + pll_clk = devm_clk_hw_get_clk(dev, &eic7700_pll_clks[1].hw, 1308 1308 + "clk_pll_cpu"); 1309 1309 + if (IS_ERR(pll_clk)) 1310 1310 + return dev_err_probe(dev, PTR_ERR(pll_clk), 1311 1311 + "failed to get clk_pll_cpu\n"); 1312 1312 + 1313 1313 + clk_data->pll_nb.notifier_call = eic7700_clk_pll_cpu_notifier_cb; 1314 1314 + ret = devm_clk_notifier_register(dev, pll_clk, &clk_data->pll_nb); 1315 1315 + if (ret) 1316 1316 + return ret; 1317 1317 + 1318 1318 + ret = eswin_clk_register_fixed_factor(dev, eic7700_factor_clks, 1319 1319 + ARRAY_SIZE(eic7700_factor_clks), 1320 1320 + clk_data); 1321 1321 + if (ret) 1322 1322 + return dev_err_probe(dev, ret, 1323 1323 + "failed to register fixed factor clock\n"); 1324 1324 + 1325 1325 + ret = eswin_clk_register_divider(dev, eic7700_div_clks, 1326 1326 + ARRAY_SIZE(eic7700_div_clks), 1327 1327 + clk_data); 1328 1328 + if (ret) 1329 1329 + return dev_err_probe(dev, ret, 1330 1330 + "failed to register divider clock\n"); 1331 1331 + 1332 1332 + ret = eswin_clk_register_gate(dev, eic7700_gate_clks, 1333 1333 + ARRAY_SIZE(eic7700_gate_clks), clk_data); 1334 1334 + if (ret) 1335 1335 + return dev_err_probe(dev, ret, 1336 1336 + "failed to register gate clock\n"); 1337 1337 + 1338 1338 + ret = eswin_clk_register_clks(dev, eic7700_early_clks, 1339 1339 + ARRAY_SIZE(eic7700_early_clks), clk_data); 1340 1340 + if (ret) 1341 1341 + return dev_err_probe(dev, ret, "failed to register clock\n"); 1342 1342 + 1343 1343 + ret = eswin_clk_register_mux(dev, eic7700_mux_clks, 1344 1344 + ARRAY_SIZE(eic7700_mux_clks), clk_data); 1345 1345 + if (ret) 1346 1346 + return dev_err_probe(dev, ret, 1347 1347 + "failed to register mux clock\n"); 1348 1348 + 1349 1349 + ret = eswin_clk_register_clks(dev, eic7700_clks, 1350 1350 + ARRAY_SIZE(eic7700_clks), clk_data); 1351 1351 + if (ret) 1352 1352 + return dev_err_probe(dev, ret, "failed to register clock\n"); 1353 1353 + 1354 1354 + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1355 1355 + &clk_data->clk_data); 1356 1356 + } 1357 1357 + 1358 1358 + static const struct of_device_id eic7700_clock_dt_ids[] = { 1359 1359 + { .compatible = "eswin,eic7700-clock", }, 1360 1360 + { /* sentinel */ } 1361 1361 + }; 1362 1362 + MODULE_DEVICE_TABLE(of, eic7700_clock_dt_ids); 1363 1363 + 1364 1364 + static struct platform_driver eic7700_clock_driver = { 1365 1365 + .probe = eic7700_clk_probe, 1366 1366 + .driver = { 1367 1367 + .name = "eic7700-clock", 1368 1368 + .of_match_table = eic7700_clock_dt_ids, 1369 1369 + }, 1370 1370 + }; 1371 1371 + module_platform_driver(eic7700_clock_driver); 1372 1372 + 1373 1373 + MODULE_LICENSE("GPL"); 1374 1374 + MODULE_AUTHOR("Yifeng Huang <huangyifeng@eswincomputing.com>"); 1375 1375 + MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>"); 1376 1376 + MODULE_DESCRIPTION("ESWIN EIC7700 clock controller driver");

+586

drivers/clk/eswin/clk.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4 4 + * All rights reserved. 5 5 + * 6 6 + * Authors: 7 7 + * Yifeng Huang <huangyifeng@eswincomputing.com> 8 8 + * Xuyang Dong <dongxuyang@eswincomputing.com> 9 9 + */ 10 10 + 11 11 + #include <linux/bitfield.h> 12 12 + #include <linux/clk-provider.h> 13 13 + #include <linux/iopoll.h> 14 14 + #include <linux/math.h> 15 15 + #include <linux/platform_device.h> 16 16 + #include <linux/slab.h> 17 17 + 18 18 + #include "common.h" 19 19 + 20 20 + #define PLL_EN_MASK GENMASK(1, 0) 21 21 + #define PLL_REFDIV_MASK GENMASK(17, 12) 22 22 + #define PLL_FBDIV_MASK GENMASK(31, 20) 23 23 + #define PLL_FRAC_MASK GENMASK(27, 4) 24 24 + #define PLL_POSTDIV1_MASK GENMASK(10, 8) 25 25 + #define PLL_POSTDIV2_MASK GENMASK(18, 16) 26 26 + 27 27 + struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev, 28 28 + size_t nr_clks) 29 29 + { 30 30 + struct eswin_clock_data *eclk_data; 31 31 + 32 32 + eclk_data = devm_kzalloc(&pdev->dev, 33 33 + struct_size(eclk_data, clk_data.hws, nr_clks), 34 34 + GFP_KERNEL); 35 35 + if (!eclk_data) 36 36 + return ERR_PTR(-ENOMEM); 37 37 + 38 38 + eclk_data->base = devm_platform_ioremap_resource(pdev, 0); 39 39 + if (IS_ERR(eclk_data->base)) 40 40 + return ERR_PTR(-EINVAL); 41 41 + 42 42 + eclk_data->clk_data.num = nr_clks; 43 43 + spin_lock_init(&eclk_data->lock); 44 44 + 45 45 + return eclk_data; 46 46 + } 47 47 + EXPORT_SYMBOL_GPL(eswin_clk_init); 48 48 + 49 49 + /** 50 50 + * eswin_calc_pll - calculate PLL values 51 51 + * @frac_val: fractional divider 52 52 + * @fbdiv_val: feedback divider 53 53 + * @rate: reference rate 54 54 + * @parent_rate: parent rate 55 55 + * 56 56 + * Calculate PLL values for frac and fbdiv: 57 57 + * fbdiv = rate * 4 / parent_rate 58 58 + * frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate 59 59 + */ 60 60 + static void eswin_calc_pll(u32 *frac_val, u32 *fbdiv_val, unsigned long rate, 61 61 + unsigned long parent_rate) 62 62 + { 63 63 + u32 rem; 64 64 + u64 tmp; 65 65 + 66 66 + /* step 1: rate * 4 */ 67 67 + tmp = rate * 4; 68 68 + /* step 2: use do_div() to get the quotient(tmp) and remainder(rem) */ 69 69 + rem = do_div(tmp, (u32)parent_rate); 70 70 + /* fbdiv = rate * 4 / parent_rate */ 71 71 + *fbdiv_val = (u32)tmp; 72 72 + /* 73 73 + * step 3: rem << 24 74 74 + * 24: 24-bit fractional accuracy 75 75 + */ 76 76 + tmp = (u64)rem << 24; 77 77 + /* step 4: use do_div() to get the quotient(tmp) */ 78 78 + do_div(tmp, (u32)parent_rate); 79 79 + /* frac = (rate * 4 % parent_rate * (2 ^ 24)) / parent_rate */ 80 80 + *frac_val = (u32)tmp; 81 81 + } 82 82 + 83 83 + static inline struct eswin_clk_pll *to_pll_clk(struct clk_hw *hw) 84 84 + { 85 85 + return container_of(hw, struct eswin_clk_pll, hw); 86 86 + } 87 87 + 88 88 + static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 89 89 + unsigned long parent_rate) 90 90 + { 91 91 + struct eswin_clk_pll *clk = to_pll_clk(hw); 92 92 + u32 frac_val, fbdiv_val, val, mask; 93 93 + int ret; 94 94 + 95 95 + eswin_calc_pll(&frac_val, &fbdiv_val, rate, parent_rate); 96 96 + 97 97 + /* First, disable pll */ 98 98 + val = readl_relaxed(clk->ctrl_reg0); 99 99 + val &= ~PLL_EN_MASK; 100 100 + val |= FIELD_PREP(PLL_EN_MASK, 0); 101 101 + writel_relaxed(val, clk->ctrl_reg0); 102 102 + 103 103 + val = readl_relaxed(clk->ctrl_reg0); 104 104 + val &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK); 105 105 + val |= FIELD_PREP(PLL_FBDIV_MASK, fbdiv_val); 106 106 + val |= FIELD_PREP(PLL_REFDIV_MASK, 1); 107 107 + writel_relaxed(val, clk->ctrl_reg0); 108 108 + 109 109 + val = readl_relaxed(clk->ctrl_reg1); 110 110 + val &= ~PLL_FRAC_MASK; 111 111 + val |= FIELD_PREP(PLL_FRAC_MASK, frac_val); 112 112 + writel_relaxed(val, clk->ctrl_reg1); 113 113 + 114 114 + val = readl_relaxed(clk->ctrl_reg2); 115 115 + val &= ~(PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK); 116 116 + val |= FIELD_PREP(PLL_POSTDIV1_MASK, 1); 117 117 + val |= FIELD_PREP(PLL_POSTDIV2_MASK, 1); 118 118 + writel_relaxed(val, clk->ctrl_reg2); 119 119 + 120 120 + /* Last, enable pll */ 121 121 + val = readl_relaxed(clk->ctrl_reg0); 122 122 + val &= ~PLL_EN_MASK; 123 123 + val |= FIELD_PREP(PLL_EN_MASK, 1); 124 124 + writel_relaxed(val, clk->ctrl_reg0); 125 125 + 126 126 + /* Usually the pll will lock in 50us */ 127 127 + mask = GENMASK(clk->lock_shift + clk->lock_width - 1, clk->lock_shift); 128 128 + ret = readl_poll_timeout(clk->status_reg, val, val & mask, 1, 50 * 2); 129 129 + if (ret) 130 130 + pr_err("failed to lock the pll!\n"); 131 131 + 132 132 + return ret; 133 133 + } 134 134 + 135 135 + static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 136 136 + unsigned long parent_rate) 137 137 + { 138 138 + struct eswin_clk_pll *clk = to_pll_clk(hw); 139 139 + u64 fbdiv_val, frac_val, tmp; 140 140 + u32 rem, val; 141 141 + 142 142 + val = readl_relaxed(clk->ctrl_reg0); 143 143 + val &= PLL_FBDIV_MASK; 144 144 + fbdiv_val = (val >> clk->fbdiv_shift); 145 145 + 146 146 + val = readl_relaxed(clk->ctrl_reg1); 147 147 + val &= PLL_FRAC_MASK; 148 148 + frac_val = (val >> clk->frac_shift); 149 149 + 150 150 + /* rate = 24000000 * (fbdiv + frac / (2 ^ 24)) / 4 */ 151 151 + tmp = parent_rate * frac_val; 152 152 + rem = do_div(tmp, BIT(24)); 153 153 + if (rem) 154 154 + tmp = parent_rate * fbdiv_val + tmp + 1; 155 155 + else 156 156 + tmp = parent_rate * fbdiv_val + tmp; 157 157 + 158 158 + do_div(tmp, 4); 159 159 + 160 160 + return tmp; 161 161 + } 162 162 + 163 163 + static int clk_pll_determine_rate(struct clk_hw *hw, 164 164 + struct clk_rate_request *req) 165 165 + { 166 166 + struct eswin_clk_pll *clk = to_pll_clk(hw); 167 167 + 168 168 + req->rate = clamp(req->rate, clk->min_rate, clk->max_rate); 169 169 + req->min_rate = clk->min_rate; 170 170 + req->max_rate = clk->max_rate; 171 171 + 172 172 + return 0; 173 173 + } 174 174 + 175 175 + int eswin_clk_register_fixed_rate(struct device *dev, 176 176 + struct eswin_fixed_rate_clock *clks, 177 177 + int nums, struct eswin_clock_data *data) 178 178 + { 179 179 + struct clk_hw *clk_hw; 180 180 + int i; 181 181 + 182 182 + for (i = 0; i < nums; i++) { 183 183 + clk_hw = devm_clk_hw_register_fixed_rate(dev, clks[i].name, 184 184 + NULL, clks[i].flags, 185 185 + clks[i].rate); 186 186 + if (IS_ERR(clk_hw)) 187 187 + return PTR_ERR(clk_hw); 188 188 + 189 189 + clks[i].hw = *clk_hw; 190 190 + data->clk_data.hws[clks[i].id] = clk_hw; 191 191 + } 192 192 + 193 193 + return 0; 194 194 + } 195 195 + EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_rate); 196 196 + 197 197 + static const struct clk_ops eswin_clk_pll_ops = { 198 198 + .set_rate = clk_pll_set_rate, 199 199 + .recalc_rate = clk_pll_recalc_rate, 200 200 + .determine_rate = clk_pll_determine_rate, 201 201 + }; 202 202 + 203 203 + int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks, 204 204 + int nums, struct eswin_clock_data *data) 205 205 + { 206 206 + struct eswin_clk_pll *p_clk = NULL; 207 207 + struct clk_init_data init; 208 208 + struct clk_hw *clk_hw; 209 209 + int i, ret; 210 210 + 211 211 + p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); 212 212 + if (!p_clk) 213 213 + return -ENOMEM; 214 214 + 215 215 + for (i = 0; i < nums; i++) { 216 216 + p_clk->id = clks[i].id; 217 217 + p_clk->ctrl_reg0 = data->base + clks[i].ctrl_reg0; 218 218 + p_clk->fbdiv_shift = clks[i].fbdiv_shift; 219 219 + 220 220 + p_clk->ctrl_reg1 = data->base + clks[i].ctrl_reg1; 221 221 + p_clk->frac_shift = clks[i].frac_shift; 222 222 + 223 223 + p_clk->ctrl_reg2 = data->base + clks[i].ctrl_reg2; 224 224 + 225 225 + p_clk->status_reg = data->base + clks[i].status_reg; 226 226 + p_clk->lock_shift = clks[i].lock_shift; 227 227 + p_clk->lock_width = clks[i].lock_width; 228 228 + 229 229 + p_clk->max_rate = clks[i].max_rate; 230 230 + p_clk->min_rate = clks[i].min_rate; 231 231 + 232 232 + init.name = clks[i].name; 233 233 + init.flags = 0; 234 234 + init.parent_data = clks[i].parent_data; 235 235 + init.num_parents = 1; 236 236 + init.ops = &eswin_clk_pll_ops; 237 237 + p_clk->hw.init = &init; 238 238 + 239 239 + clk_hw = &p_clk->hw; 240 240 + 241 241 + ret = devm_clk_hw_register(dev, clk_hw); 242 242 + if (ret) 243 243 + return ret; 244 244 + 245 245 + clks[i].hw = *clk_hw; 246 246 + data->clk_data.hws[clks[i].id] = clk_hw; 247 247 + p_clk++; 248 248 + } 249 249 + 250 250 + return 0; 251 251 + } 252 252 + EXPORT_SYMBOL_GPL(eswin_clk_register_pll); 253 253 + 254 254 + int eswin_clk_register_fixed_factor(struct device *dev, 255 255 + struct eswin_fixed_factor_clock *clks, 256 256 + int nums, struct eswin_clock_data *data) 257 257 + { 258 258 + struct clk_hw *clk_hw; 259 259 + int i; 260 260 + 261 261 + for (i = 0; i < nums; i++) { 262 262 + clk_hw = devm_clk_hw_register_fixed_factor_index(dev, clks[i].name, 263 263 + clks[i].parent_data->index, 264 264 + clks[i].flags, clks[i].mult, 265 265 + clks[i].div); 266 266 + 267 267 + if (IS_ERR(clk_hw)) 268 268 + return PTR_ERR(clk_hw); 269 269 + 270 270 + clks[i].hw = *clk_hw; 271 271 + data->clk_data.hws[clks[i].id] = clk_hw; 272 272 + } 273 273 + 274 274 + return 0; 275 275 + } 276 276 + EXPORT_SYMBOL_GPL(eswin_clk_register_fixed_factor); 277 277 + 278 278 + int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks, 279 279 + int nums, struct eswin_clock_data *data) 280 280 + { 281 281 + struct clk_hw *clk_hw; 282 282 + int i; 283 283 + 284 284 + for (i = 0; i < nums; i++) { 285 285 + clk_hw = devm_clk_hw_register_mux_parent_data_table(dev, clks[i].name, 286 286 + clks[i].parent_data, 287 287 + clks[i].num_parents, 288 288 + clks[i].flags, 289 289 + data->base + clks[i].reg, 290 290 + clks[i].shift, clks[i].width, 291 291 + clks[i].mux_flags, 292 292 + clks[i].table, &data->lock); 293 293 + 294 294 + if (IS_ERR(clk_hw)) 295 295 + return PTR_ERR(clk_hw); 296 296 + 297 297 + clks[i].hw = *clk_hw; 298 298 + data->clk_data.hws[clks[i].id] = clk_hw; 299 299 + } 300 300 + 301 301 + return 0; 302 302 + } 303 303 + EXPORT_SYMBOL_GPL(eswin_clk_register_mux); 304 304 + 305 305 + static unsigned int _eswin_get_val(unsigned int div, unsigned long flags, 306 306 + u8 width) 307 307 + { 308 308 + unsigned int maxdiv; 309 309 + 310 310 + maxdiv = clk_div_mask(width); 311 311 + div = div > maxdiv ? maxdiv : div; 312 312 + 313 313 + if (flags & ESWIN_PRIV_DIV_MIN_2) 314 314 + return (div < 2) ? 2 : div; 315 315 + 316 316 + return div; 317 317 + } 318 318 + 319 319 + static unsigned int eswin_div_get_val(unsigned long rate, 320 320 + unsigned long parent_rate, u8 width, 321 321 + unsigned long flags) 322 322 + { 323 323 + unsigned int div; 324 324 + 325 325 + div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 326 326 + 327 327 + return _eswin_get_val(div, flags, width); 328 328 + } 329 329 + 330 330 + static inline struct eswin_divider_clock *to_div_clk(struct clk_hw *hw) 331 331 + { 332 332 + return container_of(hw, struct eswin_divider_clock, hw); 333 333 + } 334 334 + 335 335 + static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 336 336 + unsigned long parent_rate) 337 337 + { 338 338 + struct eswin_divider_clock *dclk = to_div_clk(hw); 339 339 + unsigned long flags; 340 340 + unsigned int value; 341 341 + u32 val; 342 342 + 343 343 + value = eswin_div_get_val(rate, parent_rate, dclk->width, 344 344 + dclk->priv_flag); 345 345 + 346 346 + spin_lock_irqsave(dclk->lock, flags); 347 347 + 348 348 + val = readl_relaxed(dclk->ctrl_reg); 349 349 + val &= ~(clk_div_mask(dclk->width) << dclk->shift); 350 350 + val |= (u32)value << dclk->shift; 351 351 + writel_relaxed(val, dclk->ctrl_reg); 352 352 + 353 353 + spin_unlock_irqrestore(dclk->lock, flags); 354 354 + 355 355 + return 0; 356 356 + } 357 357 + 358 358 + static unsigned long clk_div_recalc_rate(struct clk_hw *hw, 359 359 + unsigned long parent_rate) 360 360 + { 361 361 + struct eswin_divider_clock *dclk = to_div_clk(hw); 362 362 + unsigned int div, val; 363 363 + 364 364 + val = readl_relaxed(dclk->ctrl_reg) >> dclk->shift; 365 365 + val &= clk_div_mask(dclk->width); 366 366 + div = _eswin_get_val(val, dclk->priv_flag, dclk->width); 367 367 + 368 368 + return DIV_ROUND_UP_ULL((u64)parent_rate, div); 369 369 + } 370 370 + 371 371 + static int eswin_clk_bestdiv(unsigned long rate, 372 372 + unsigned long best_parent_rate, u8 width, 373 373 + unsigned long flags) 374 374 + { 375 375 + unsigned long bestdiv, up_rate, down_rate; 376 376 + int up, down; 377 377 + 378 378 + if (!rate) 379 379 + rate = 1; 380 380 + 381 381 + /* closest round */ 382 382 + up = DIV_ROUND_UP_ULL((u64)best_parent_rate, rate); 383 383 + down = best_parent_rate / rate; 384 384 + 385 385 + up_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, up); 386 386 + down_rate = DIV_ROUND_UP_ULL((u64)best_parent_rate, down); 387 387 + 388 388 + bestdiv = (rate - up_rate) <= (down_rate - rate) ? up : down; 389 389 + 390 390 + return bestdiv; 391 391 + } 392 392 + 393 393 + static int clk_div_determine_rate(struct clk_hw *hw, 394 394 + struct clk_rate_request *req) 395 395 + { 396 396 + struct eswin_divider_clock *dclk = to_div_clk(hw); 397 397 + int div; 398 398 + 399 399 + div = eswin_clk_bestdiv(req->rate, req->best_parent_rate, dclk->width, 400 400 + dclk->priv_flag); 401 401 + div = _eswin_get_val(div, dclk->priv_flag, dclk->width); 402 402 + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); 403 403 + 404 404 + return 0; 405 405 + } 406 406 + 407 407 + static const struct clk_ops eswin_clk_div_ops = { 408 408 + .set_rate = clk_div_set_rate, 409 409 + .recalc_rate = clk_div_recalc_rate, 410 410 + .determine_rate = clk_div_determine_rate, 411 411 + }; 412 412 + 413 413 + struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id, 414 414 + const char *name, 415 415 + const struct clk_hw *parent_hw, 416 416 + unsigned long flags, void __iomem *reg, 417 417 + u8 shift, u8 width, 418 418 + unsigned long clk_divider_flags, 419 419 + unsigned long priv_flag, spinlock_t *lock) 420 420 + { 421 421 + struct eswin_divider_clock *dclk; 422 422 + struct clk_init_data init; 423 423 + struct clk_hw *clk_hw; 424 424 + int ret; 425 425 + 426 426 + dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); 427 427 + if (!dclk) 428 428 + return ERR_PTR(-ENOMEM); 429 429 + 430 430 + init.name = name; 431 431 + init.ops = &eswin_clk_div_ops; 432 432 + init.flags = flags; 433 433 + init.parent_hws = &parent_hw; 434 434 + init.num_parents = 1; 435 435 + 436 436 + /* struct clk_divider assignments */ 437 437 + dclk->id = id; 438 438 + dclk->ctrl_reg = reg; 439 439 + dclk->shift = shift; 440 440 + dclk->width = width; 441 441 + dclk->div_flags = clk_divider_flags; 442 442 + dclk->priv_flag = priv_flag; 443 443 + dclk->lock = lock; 444 444 + dclk->hw.init = &init; 445 445 + 446 446 + /* register the clock */ 447 447 + clk_hw = &dclk->hw; 448 448 + ret = devm_clk_hw_register(dev, clk_hw); 449 449 + if (ret) { 450 450 + dev_err(dev, "failed to register divider clock!\n"); 451 451 + return ERR_PTR(ret); 452 452 + } 453 453 + 454 454 + return clk_hw; 455 455 + } 456 456 + EXPORT_SYMBOL_GPL(eswin_register_clkdiv); 457 457 + 458 458 + int eswin_clk_register_divider(struct device *dev, 459 459 + struct eswin_divider_clock *clks, 460 460 + int nums, struct eswin_clock_data *data) 461 461 + { 462 462 + struct clk_hw *clk_hw; 463 463 + int i; 464 464 + 465 465 + for (i = 0; i < nums; i++) { 466 466 + clk_hw = devm_clk_hw_register_divider_parent_data(dev, clks[i].name, 467 467 + clks[i].parent_data, 468 468 + clks[i].flags, 469 469 + data->base + clks[i].reg, 470 470 + clks[i].shift, clks[i].width, 471 471 + clks[i].div_flags, &data->lock); 472 472 + 473 473 + if (IS_ERR(clk_hw)) 474 474 + return PTR_ERR(clk_hw); 475 475 + 476 476 + clks[i].hw = *clk_hw; 477 477 + data->clk_data.hws[clks[i].id] = clk_hw; 478 478 + } 479 479 + 480 480 + return 0; 481 481 + } 482 482 + EXPORT_SYMBOL_GPL(eswin_clk_register_divider); 483 483 + 484 484 + int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks, 485 485 + int nums, struct eswin_clock_data *data) 486 486 + { 487 487 + struct clk_hw *clk_hw; 488 488 + int i; 489 489 + 490 490 + for (i = 0; i < nums; i++) { 491 491 + clk_hw = devm_clk_hw_register_gate_parent_data(dev, clks[i].name, 492 492 + clks[i].parent_data, 493 493 + clks[i].flags, 494 494 + data->base + clks[i].reg, 495 495 + clks[i].bit_idx, clks[i].gate_flags, 496 496 + &data->lock); 497 497 + 498 498 + if (IS_ERR(clk_hw)) 499 499 + return PTR_ERR(clk_hw); 500 500 + 501 501 + clks[i].hw = *clk_hw; 502 502 + data->clk_data.hws[clks[i].id] = clk_hw; 503 503 + } 504 504 + 505 505 + return 0; 506 506 + } 507 507 + EXPORT_SYMBOL_GPL(eswin_clk_register_gate); 508 508 + 509 509 + int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks, 510 510 + int nums, struct eswin_clock_data *data) 511 511 + { 512 512 + struct eswin_clk_info *info; 513 513 + const struct clk_hw *phw = NULL; 514 514 + struct clk_hw *hw; 515 515 + int i; 516 516 + 517 517 + for (i = 0; i < nums; i++) { 518 518 + info = &clks[i]; 519 519 + switch (info->type) { 520 520 + case CLK_FIXED_FACTOR: { 521 521 + const struct eswin_fixed_factor_clock *factor; 522 522 + 523 523 + factor = &info->data.factor; 524 524 + phw = data->clk_data.hws[info->pid]; 525 525 + hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, factor->name, phw, 526 526 + factor->flags, 527 527 + factor->mult, 528 528 + factor->div); 529 529 + break; 530 530 + } 531 531 + case CLK_MUX: { 532 532 + const struct eswin_mux_clock *mux = &info->data.mux; 533 533 + 534 534 + hw = devm_clk_hw_register_mux_parent_data_table(dev, mux->name, 535 535 + mux->parent_data, 536 536 + mux->num_parents, 537 537 + mux->flags, 538 538 + data->base + mux->reg, 539 539 + mux->shift, mux->width, 540 540 + mux->mux_flags, 541 541 + mux->table, &data->lock); 542 542 + break; 543 543 + } 544 544 + case CLK_DIVIDER: { 545 545 + const struct eswin_divider_clock *div = &info->data.div; 546 546 + 547 547 + phw = data->clk_data.hws[info->pid]; 548 548 + if (div->priv_flag) 549 549 + hw = eswin_register_clkdiv(dev, div->id, div->name, phw, 550 550 + div->flags, data->base + div->reg, 551 551 + div->shift, div->width, div->div_flags, 552 552 + div->priv_flag, &data->lock); 553 553 + else 554 554 + hw = devm_clk_hw_register_divider_parent_hw(dev, div->name, phw, 555 555 + div->flags, 556 556 + data->base + div->reg, 557 557 + div->shift, div->width, 558 558 + div->div_flags, 559 559 + &data->lock); 560 560 + break; 561 561 + } 562 562 + case CLK_GATE: { 563 563 + const struct eswin_gate_clock *gate = &info->data.gate; 564 564 + 565 565 + phw = data->clk_data.hws[info->pid]; 566 566 + hw = devm_clk_hw_register_gate_parent_hw(dev, gate->name, phw, 567 567 + gate->flags, 568 568 + data->base + gate->reg, 569 569 + gate->bit_idx, gate->gate_flags, 570 570 + &data->lock); 571 571 + break; 572 572 + } 573 573 + default: 574 574 + dev_err(dev, "Unidentifiable clock type!\n"); 575 575 + return -EINVAL; 576 576 + } 577 577 + if (IS_ERR(hw)) 578 578 + return PTR_ERR(hw); 579 579 + 580 580 + info->hw = *hw; 581 581 + data->clk_data.hws[info->id] = hw; 582 582 + } 583 583 + 584 584 + return 0; 585 585 + } 586 586 + EXPORT_SYMBOL_GPL(eswin_clk_register_clks);

+340

drivers/clk/eswin/common.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 + /* 3 3 + * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 4 4 + * All rights reserved. 5 5 + * 6 6 + * Authors: 7 7 + * Yifeng Huang <huangyifeng@eswincomputing.com> 8 8 + * Xuyang Dong <dongxuyang@eswincomputing.com> 9 9 + */ 10 10 + 11 11 + #ifndef __ESWIN_COMMON_H__ 12 12 + #define __ESWIN_COMMON_H__ 13 13 + 14 14 + #define APLL_HIGH_FREQ 983040000 15 15 + #define APLL_LOW_FREQ 225792000 16 16 + #define PLL_HIGH_FREQ 1800000000 17 17 + #define PLL_LOW_FREQ 24000000 18 18 + 19 19 + /* 20 20 + * ESWIN_PRIV_DIV_MIN_2: If ESWIN_PRIV_DIV_MIN_2 is set, the minimum value of 21 21 + * the register is 2, i.e. the minimum division ratio is 2. 22 22 + */ 23 23 + #define ESWIN_PRIV_DIV_MIN_2 BIT(0) 24 24 + 25 25 + enum eswin_clk_type { 26 26 + CLK_FIXED_FACTOR, 27 27 + CLK_MUX, 28 28 + CLK_DIVIDER, 29 29 + CLK_GATE, 30 30 + }; 31 31 + 32 32 + struct eswin_clock_data { 33 33 + void __iomem *base; 34 34 + struct clk_hw *original_clk; 35 35 + struct notifier_block pll_nb; 36 36 + spinlock_t lock; /* protect register read-modify-write cycle */ 37 37 + struct clk_hw_onecell_data clk_data; 38 38 + }; 39 39 + 40 40 + struct eswin_divider_clock { 41 41 + struct clk_hw hw; 42 42 + unsigned int id; 43 43 + const char *name; 44 44 + const struct clk_parent_data *parent_data; 45 45 + void __iomem *ctrl_reg; /* register address of the divider clock */ 46 46 + unsigned long flags; 47 47 + unsigned long reg; /* register offset */ 48 48 + u8 shift; 49 49 + u8 width; 50 50 + unsigned long div_flags; 51 51 + unsigned long priv_flag; 52 52 + spinlock_t *lock; /* protect register read-modify-write cycle */ 53 53 + }; 54 54 + 55 55 + struct eswin_fixed_rate_clock { 56 56 + struct clk_hw hw; 57 57 + unsigned int id; 58 58 + const char *name; 59 59 + unsigned long flags; 60 60 + unsigned long rate; 61 61 + }; 62 62 + 63 63 + struct eswin_fixed_factor_clock { 64 64 + struct clk_hw hw; 65 65 + unsigned int id; 66 66 + const char *name; 67 67 + const struct clk_parent_data *parent_data; 68 68 + unsigned long mult; 69 69 + unsigned long div; 70 70 + unsigned long flags; 71 71 + }; 72 72 + 73 73 + struct eswin_gate_clock { 74 74 + struct clk_hw hw; 75 75 + unsigned int id; 76 76 + const char *name; 77 77 + const struct clk_parent_data *parent_data; 78 78 + unsigned long flags; 79 79 + unsigned long reg; 80 80 + u8 bit_idx; 81 81 + u8 gate_flags; 82 82 + }; 83 83 + 84 84 + struct eswin_mux_clock { 85 85 + struct clk_hw hw; 86 86 + unsigned int id; 87 87 + const char *name; 88 88 + const struct clk_parent_data *parent_data; 89 89 + u8 num_parents; 90 90 + unsigned long flags; 91 91 + unsigned long reg; 92 92 + u8 shift; 93 93 + u8 width; 94 94 + u8 mux_flags; 95 95 + u32 *table; 96 96 + }; 97 97 + 98 98 + struct eswin_pll_clock { 99 99 + struct clk_hw hw; 100 100 + u32 id; 101 101 + const char *name; 102 102 + const struct clk_parent_data *parent_data; 103 103 + const u32 ctrl_reg0; 104 104 + const u8 fbdiv_shift; 105 105 + 106 106 + const u32 ctrl_reg1; 107 107 + const u8 frac_shift; 108 108 + 109 109 + const u32 ctrl_reg2; 110 110 + 111 111 + const u32 status_reg; 112 112 + const u8 lock_shift; 113 113 + const u8 lock_width; 114 114 + 115 115 + const u64 max_rate; 116 116 + const u64 min_rate; 117 117 + }; 118 118 + 119 119 + struct eswin_clk_pll { 120 120 + struct clk_hw hw; 121 121 + u32 id; 122 122 + void __iomem *ctrl_reg0; 123 123 + u8 fbdiv_shift; 124 124 + 125 125 + void __iomem *ctrl_reg1; 126 126 + u8 frac_shift; 127 127 + 128 128 + void __iomem *ctrl_reg2; 129 129 + 130 130 + void __iomem *status_reg; 131 131 + u8 lock_shift; 132 132 + u8 lock_width; 133 133 + 134 134 + u64 max_rate; 135 135 + u64 min_rate; 136 136 + }; 137 137 + 138 138 + struct eswin_clk_info { 139 139 + unsigned int type; 140 140 + unsigned int pid; 141 141 + unsigned int id; 142 142 + struct clk_hw hw; 143 143 + union { 144 144 + struct eswin_divider_clock div; 145 145 + struct eswin_fixed_factor_clock factor; 146 146 + struct eswin_gate_clock gate; 147 147 + struct eswin_mux_clock mux; 148 148 + } data; 149 149 + }; 150 150 + 151 151 + struct eswin_clock_data *eswin_clk_init(struct platform_device *pdev, 152 152 + size_t nr_clks); 153 153 + int eswin_clk_register_fixed_rate(struct device *dev, 154 154 + struct eswin_fixed_rate_clock *clks, 155 155 + int nums, struct eswin_clock_data *data); 156 156 + int eswin_clk_register_pll(struct device *dev, struct eswin_pll_clock *clks, 157 157 + int nums, struct eswin_clock_data *data); 158 158 + int eswin_clk_register_fixed_factor(struct device *dev, 159 159 + struct eswin_fixed_factor_clock *clks, 160 160 + int nums, struct eswin_clock_data *data); 161 161 + int eswin_clk_register_mux(struct device *dev, struct eswin_mux_clock *clks, 162 162 + int nums, struct eswin_clock_data *data); 163 163 + int eswin_clk_register_divider(struct device *dev, 164 164 + struct eswin_divider_clock *clks, 165 165 + int nums, struct eswin_clock_data *data); 166 166 + int eswin_clk_register_gate(struct device *dev, struct eswin_gate_clock *clks, 167 167 + int nums, struct eswin_clock_data *data); 168 168 + int eswin_clk_register_clks(struct device *dev, struct eswin_clk_info *clks, 169 169 + int nums, struct eswin_clock_data *data); 170 170 + struct clk_hw *eswin_register_clkdiv(struct device *dev, unsigned int id, 171 171 + const char *name, 172 172 + const struct clk_hw *parent_hw, 173 173 + unsigned long flags, void __iomem *reg, 174 174 + u8 shift, u8 width, 175 175 + unsigned long clk_divider_flags, 176 176 + unsigned long priv_flag, spinlock_t *lock); 177 177 + 178 178 + #define ESWIN_DIV(_id, _name, _pdata, _flags, _reg, _shift, _width, \ 179 179 + _dflags, _pflag) \ 180 180 + { \ 181 181 + .id = _id, \ 182 182 + .name = _name, \ 183 183 + .parent_data = _pdata, \ 184 184 + .flags = _flags, \ 185 185 + .reg = _reg, \ 186 186 + .shift = _shift, \ 187 187 + .width = _width, \ 188 188 + .div_flags = _dflags, \ 189 189 + .priv_flag = _pflag, \ 190 190 + } 191 191 + 192 192 + #define ESWIN_DIV_TYPE(_id, _name, _pid, _flags, _reg, _shift, _width, \ 193 193 + _dflags, _pflag) \ 194 194 + { \ 195 195 + .type = CLK_DIVIDER, \ 196 196 + .pid = _pid, \ 197 197 + .id = _id, \ 198 198 + .data = { \ 199 199 + .div = { \ 200 200 + .name = _name, \ 201 201 + .flags = _flags, \ 202 202 + .reg = _reg, \ 203 203 + .shift = _shift, \ 204 204 + .width = _width, \ 205 205 + .div_flags = _dflags, \ 206 206 + .priv_flag = _pflag, \ 207 207 + }, \ 208 208 + }, \ 209 209 + } 210 210 + 211 211 + #define ESWIN_FACTOR(_id, _name, _pdata, _mult, _div, _flags) \ 212 212 + { \ 213 213 + .id = _id, \ 214 214 + .name = _name, \ 215 215 + .parent_data = _pdata, \ 216 216 + .mult = _mult, \ 217 217 + .div = _div, \ 218 218 + .flags = _flags, \ 219 219 + } 220 220 + 221 221 + #define ESWIN_FACTOR_TYPE(_id, _name, _pid, _mult, _div, _flags) \ 222 222 + { \ 223 223 + .type = CLK_FIXED_FACTOR, \ 224 224 + .pid = _pid, \ 225 225 + .id = _id, \ 226 226 + .data = { \ 227 227 + .factor = { \ 228 228 + .name = _name, \ 229 229 + .mult = _mult, \ 230 230 + .div = _div, \ 231 231 + .flags = _flags, \ 232 232 + }, \ 233 233 + }, \ 234 234 + } 235 235 + 236 236 + #define ESWIN_FIXED(_id, _name, _flags, _rate) \ 237 237 + { \ 238 238 + .id = _id, \ 239 239 + .name = _name, \ 240 240 + .flags = _flags, \ 241 241 + .rate = _rate, \ 242 242 + } 243 243 + 244 244 + #define ESWIN_GATE(_id, _name, _pdata, _flags, _reg, _idx, _gflags) \ 245 245 + { \ 246 246 + .id = _id, \ 247 247 + .name = _name, \ 248 248 + .parent_data = _pdata, \ 249 249 + .flags = _flags, \ 250 250 + .reg = _reg, \ 251 251 + .bit_idx = _idx, \ 252 252 + .gate_flags = _gflags, \ 253 253 + } 254 254 + 255 255 + #define ESWIN_GATE_TYPE(_id, _name, _pid, _flags, _reg, _idx, _gflags) \ 256 256 + { \ 257 257 + .type = CLK_GATE, \ 258 258 + .pid = _pid, \ 259 259 + .id = _id, \ 260 260 + .data = { \ 261 261 + .gate = { \ 262 262 + .name = _name, \ 263 263 + .flags = _flags, \ 264 264 + .reg = _reg, \ 265 265 + .bit_idx = _idx, \ 266 266 + .gate_flags = _gflags, \ 267 267 + }, \ 268 268 + }, \ 269 269 + } 270 270 + 271 271 + #define ESWIN_MUX(_id, _name, _pdata, _num_parents, _flags, _reg, \ 272 272 + _shift, _width, _mflags) \ 273 273 + { \ 274 274 + .id = _id, \ 275 275 + .name = _name, \ 276 276 + .parent_data = _pdata, \ 277 277 + .num_parents = _num_parents, \ 278 278 + .flags = _flags, \ 279 279 + .reg = _reg, \ 280 280 + .shift = _shift, \ 281 281 + .width = _width, \ 282 282 + .mux_flags = _mflags, \ 283 283 + .table = NULL, \ 284 284 + } 285 285 + 286 286 + #define ESWIN_MUX_TBL(_id, _name, _pdata, _num_parents, _flags, _reg, \ 287 287 + _shift, _width, _mflags, _table) \ 288 288 + { \ 289 289 + .id = _id, \ 290 290 + .name = _name, \ 291 291 + .parent_data = _pdata, \ 292 292 + .num_parents = _num_parents, \ 293 293 + .flags = _flags, \ 294 294 + .reg = _reg, \ 295 295 + .shift = _shift, \ 296 296 + .width = _width, \ 297 297 + .mux_flags = _mflags, \ 298 298 + .table = _table, \ 299 299 + } 300 300 + 301 301 + #define ESWIN_MUX_TYPE(_id, _name, _pdata, _num_parents, _flags, _reg, \ 302 302 + _shift, _width, _mflags, _table) \ 303 303 + { \ 304 304 + .type = CLK_MUX, \ 305 305 + .id = _id, \ 306 306 + .data = { \ 307 307 + .mux = { \ 308 308 + .name = _name, \ 309 309 + .parent_data = _pdata, \ 310 310 + .num_parents = _num_parents, \ 311 311 + .flags = _flags, \ 312 312 + .reg = _reg, \ 313 313 + .shift = _shift, \ 314 314 + .width = _width, \ 315 315 + .mux_flags = _mflags, \ 316 316 + .table = _table, \ 317 317 + }, \ 318 318 + }, \ 319 319 + } 320 320 + 321 321 + #define ESWIN_PLL(_id, _name, _pdata, _reg0, _fb_shift, _reg1, \ 322 322 + _frac_shift, _reg2, _reg, _lock_shift, _lock_width, \ 323 323 + _max_rate, _min_rate) \ 324 324 + { \ 325 325 + .id = _id, \ 326 326 + .name = _name, \ 327 327 + .parent_data = _pdata, \ 328 328 + .ctrl_reg0 = _reg0, \ 329 329 + .fbdiv_shift = _fb_shift, \ 330 330 + .ctrl_reg1 = _reg1, \ 331 331 + .frac_shift = _frac_shift, \ 332 332 + .ctrl_reg2 = _reg2, \ 333 333 + .status_reg = _reg, \ 334 334 + .lock_shift = _lock_shift, \ 335 335 + .lock_width = _lock_width, \ 336 336 + .max_rate = _max_rate, \ 337 337 + .min_rate = _min_rate, \ 338 338 + } 339 339 + 340 340 + #endif /* __ESWIN_COMMON_H__ */