Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- avoid excessive rejections from seccomp RET_ERRNO rules
- compressed jal/jalr decoding fix
- fixes for independent irq/softirq stacks on kernels built with
CONFIG_FRAME_POINTER=n
- avoid a hang handling uaccess fixups
- another build fix for toolchain ISA strings, this time for Zicsr and
Zifenci on old GNU toolchains
* tag 'riscv-for-linus-6.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Handle zicsr/zifencei issue between gcc and binutils
riscv: uaccess: Return the number of bytes effectively not copied
riscv: stack: Fixup independent softirq stack for CONFIG_FRAME_POINTER=n
riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=n
riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr()
riscv: entry: set a0 = -ENOSYS only when syscall != -1
+53
-21
+17
-11
arch/riscv/Kconfig
+17
-11
arch/riscv/Kconfig
···
570
570
config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
571
571
def_bool y
572
572
# https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
573
-
depends on AS_IS_GNU && AS_VERSION >= 23800
573
+
# https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
574
+
depends on AS_IS_GNU && AS_VERSION >= 23600
574
575
help
575
-
Newer binutils versions default to ISA spec version 20191213 which
576
-
moves some instructions from the I extension to the Zicsr and Zifencei
577
-
extensions.
576
+
Binutils-2.38 and GCC-12.1.0 bumped the default ISA spec to the newer
577
+
20191213 version, which moves some instructions from the I extension to
578
+
the Zicsr and Zifencei extensions. This requires explicitly specifying
579
+
Zicsr and Zifencei when binutils >= 2.38 or GCC >= 12.1.0. Zicsr
580
+
and Zifencei are supported in binutils from version 2.36 onwards.
581
+
To make life easier, and avoid forcing toolchains that default to a
582
+
newer ISA spec to version 2.2, relax the check to binutils >= 2.36.
583
+
For clang < 17 or GCC < 11.1.0, for which this is not possible, this is
584
+
dealt with in CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.
578
585
579
586
config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
580
587
def_bool y
581
588
depends on TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
582
589
# https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d4498694e15bf8a16
583
-
depends on CC_IS_CLANG && CLANG_VERSION < 170000
590
+
# https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49
591
+
depends on (CC_IS_CLANG && CLANG_VERSION < 170000) || (CC_IS_GCC && GCC_VERSION < 110100)
584
592
help
585
-
Certain versions of clang do not support zicsr and zifencei via -march
586
-
but newer versions of binutils require it for the reasons noted in the
587
-
help text of CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. This
588
-
option causes an older ISA spec compatible with these older versions
589
-
of clang to be passed to GAS, which has the same result as passing zicsr
590
-
and zifencei to -march.
593
+
Certain versions of clang and GCC do not support zicsr and zifencei via
594
+
-march. This option causes an older ISA spec compatible with these older
595
+
versions of clang and GCC to be passed to GAS, which has the same result
596
+
as passing zicsr and zifencei to -march.
591
597
592
598
config FPU
593
599
bool "FPU support"
+13
-2
arch/riscv/include/asm/insn.h
+13
-2
arch/riscv/include/asm/insn.h
···
110
110
#define RVC_INSN_FUNCT4_OPOFF 12
111
111
#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
112
112
#define RVC_INSN_FUNCT3_OPOFF 13
113
+
#define RVC_INSN_J_RS1_MASK GENMASK(11, 7)
113
114
#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
114
115
#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
115
116
#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
···
246
245
__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
247
246
__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
248
247
__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
249
-
__RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)
250
-
__RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)
251
248
__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
252
249
__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
253
250
__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
···
270
271
static __always_inline bool riscv_insn_is_branch(u32 code)
271
272
{
272
273
return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
274
+
}
275
+
276
+
static __always_inline bool riscv_insn_is_c_jr(u32 code)
277
+
{
278
+
return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
279
+
(code & RVC_INSN_J_RS1_MASK) != 0;
280
+
}
281
+
282
+
static __always_inline bool riscv_insn_is_c_jalr(u32 code)
283
+
{
284
+
return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
285
+
(code & RVC_INSN_J_RS1_MASK) != 0;
273
286
}
274
287
275
288
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
+7
-1
arch/riscv/kernel/compat_vdso/Makefile
+7
-1
arch/riscv/kernel/compat_vdso/Makefile
···
11
11
COMPAT_CC := $(CC)
12
12
COMPAT_LD := $(LD)
13
13
14
-
COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
14
+
# binutils 2.35 does not support the zifencei extension, but in the ISA
15
+
# spec 20191213, G stands for IMAFD_ZICSR_ZIFENCEI.
16
+
ifdef CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI
17
+
COMPAT_CC_FLAGS := -march=rv32g -mabi=ilp32
18
+
else
19
+
COMPAT_CC_FLAGS := -march=rv32imafd -mabi=ilp32
20
+
endif
15
21
COMPAT_LD_FLAGS := -melf32lriscv
16
22
17
23
# Disable attributes, as they're useless and break the build.
+3
arch/riscv/kernel/irq.c
+3
arch/riscv/kernel/irq.c
+6
-3
arch/riscv/kernel/traps.c
+6
-3
arch/riscv/kernel/traps.c
···
297
297
asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
298
298
{
299
299
if (user_mode(regs)) {
300
-
ulong syscall = regs->a7;
300
+
long syscall = regs->a7;
301
301
302
302
regs->epc += 4;
303
303
regs->orig_a0 = regs->a0;
···
306
306
307
307
syscall = syscall_enter_from_user_mode(regs, syscall);
308
308
309
-
if (syscall < NR_syscalls)
309
+
if (syscall >= 0 && syscall < NR_syscalls)
310
310
syscall_handler(regs, syscall);
311
-
else
311
+
else if (syscall != -1)
312
312
regs->a0 = -ENOSYS;
313
313
314
314
syscall_exit_to_user_mode(regs);
···
372
372
: [sp] "r" (sp), [regs] "r" (regs)
373
373
: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
374
374
"t0", "t1", "t2", "t3", "t4", "t5", "t6",
375
+
#ifndef CONFIG_FRAME_POINTER
376
+
"s0",
377
+
#endif
375
378
"memory");
376
379
} else
377
380
#endif
+7
-4
arch/riscv/lib/uaccess.S
+7
-4
arch/riscv/lib/uaccess.S
···
17
17
li t6, SR_SUM
18
18
csrs CSR_STATUS, t6
19
19
20
-
/* Save for return value */
21
-
mv t5, a2
20
+
/*
21
+
* Save the terminal address which will be used to compute the number
22
+
* of bytes copied in case of a fixup exception.
23
+
*/
24
+
add t5, a0, a2
22
25
23
26
/*
24
27
* Register allocation for code below:
···
179
176
10:
180
177
/* Disable access to user memory */
181
178
csrc CSR_STATUS, t6
182
-
mv a0, t5
179
+
sub a0, t5, a0
183
180
ret
184
181
ENDPROC(__asm_copy_to_user)
185
182
ENDPROC(__asm_copy_from_user)
···
231
228
11:
232
229
/* Disable access to user memory */
233
230
csrc CSR_STATUS, t6
234
-
mv a0, a1
231
+
sub a0, a3, a0
235
232
ret
236
233
ENDPROC(__clear_user)
237
234
EXPORT_SYMBOL(__clear_user)