tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"All over the map..

- nouveau:
disable MSI, needs more work, will try again next merge window
- radeon:
audio + uvd regression fixes, dpm fixes, reset fixes
- i915:
the dpms fix might fix your haswell

And one pain in the ass revert, so we have VGA arbitration that when
implemented 4-5 years ago really hoped that GPUs could remove
themselves from arbitration completely once they had a kernel driver.

It seems Intel hw designers decided that was too nice a facility to
allow us to have so they removed it when they went on-die (so since
Ironlake at least). Now Alex Williamson added support for VGA
arbitration for newer GPUs however this now exposes itself to
userspace as requireing arbitration of GPU VGA regions and the X
server gets involved and disables things that it can't handle when VGA
access is possibly required around every operation.

So in order to not break userspace we just reverted things back to the
old known broken status so maybe we can try and design out way out.

Ville also had a patch to use stop machine for the two times Intel
needs to access VGA space, that might be acceptable with some rework,
but for now myself and Daniel agreed to just go back"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (23 commits)
Revert "i915: Update VGA arbiter support for newer devices"
Revert "drm/i915: Delay disabling of VGA memory until vgacon->fbcon handoff is done"
drm/radeon: re-enable sw ACR support on pre-DCE4
drm/radeon/dpm: disable bapm on TN asics
drm/radeon: improve soft reset on CIK
drm/radeon: improve soft reset on SI
drm/radeon/dpm: off by one in si_set_mc_special_registers()
drm/radeon/dpm/btc: off by one in btc_set_mc_special_registers()
drm/radeon: forever loop on error in radeon_do_test_moves()
drm/radeon: fix hw contexts for SUMO2 asics
drm/radeon: fix typo in CP DMA register headers
drm/radeon/dpm: disable multiple UVD states
drm/radeon: use hw generated CTS/N values for audio
drm/radeon: fix N/CTS clock matching for audio
drm/radeon: use 64-bit math to calculate CTS values for audio (v2)
drm/edid: catch kmalloc failure in drm_edid_to_speaker_allocation
Revert "drm/fb-helper: don't sleep for screen unblank when an oops is in progress"
drm/gma500: fix things after get/put page helpers
drm/nouveau/mc: disable msi support by default, it's busted in tons of places
drm/i915: Only apply DPMS to the encoder if enabled
...

Linus Torvalds cd4edf7a 2fe80d3b

+74 -93
+2
drivers/gpu/drm/drm_edid.c
··· 2925 2925 /* Speaker Allocation Data Block */ 2926 2926 if (dbl == 3) { 2927 2927 *sadb = kmalloc(dbl, GFP_KERNEL); 2928 + if (!*sadb) 2929 + return -ENOMEM; 2928 2930 memcpy(*sadb, &db[1], dbl); 2929 2931 count = dbl; 2930 2932 break;
-8
drivers/gpu/drm/drm_fb_helper.c
··· 416 416 return; 417 417 418 418 /* 419 - * fbdev->blank can be called from irq context in case of a panic. 420 - * Since we already have our own special panic handler which will 421 - * restore the fbdev console mode completely, just bail out early. 422 - */ 423 - if (oops_in_progress) 424 - return; 425 - 426 - /* 427 419 * For each CRTC in this fb, turn the connectors on/off. 428 420 */ 429 421 drm_modeset_lock_all(dev);
+1
drivers/gpu/drm/gma500/gtt.c
··· 204 204 if (IS_ERR(pages)) 205 205 return PTR_ERR(pages); 206 206 207 + gt->npage = gt->gem.size / PAGE_SIZE; 207 208 gt->pages = pages; 208 209 209 210 return 0;
+3 -12
drivers/gpu/drm/i915/i915_dma.c
··· 1290 1290 * then we do not take part in VGA arbitration and the 1291 1291 * vga_client_register() fails with -ENODEV. 1292 1292 */ 1293 - if (!HAS_PCH_SPLIT(dev)) { 1294 - ret = vga_client_register(dev->pdev, dev, NULL, 1295 - i915_vga_set_decode); 1296 - if (ret && ret != -ENODEV) 1297 - goto out; 1298 - } 1293 + ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1294 + if (ret && ret != -ENODEV) 1295 + goto out; 1299 1296 1300 1297 intel_register_dsm_handler(); 1301 1298 ··· 1347 1350 * tiny window where we will loose hotplug notifactions. 1348 1351 */ 1349 1352 intel_fbdev_initial_config(dev); 1350 - 1351 - /* 1352 - * Must do this after fbcon init so that 1353 - * vgacon_save_screen() works during the handover. 1354 - */ 1355 - i915_disable_vga_mem(dev); 1356 1353 1357 1354 /* Only enable hotplug handling once the fbdev is fully set up. */ 1358 1355 dev_priv->enable_hotplug_processing = true;
+6
drivers/gpu/drm/i915/i915_reg.h
··· 3881 3881 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 3882 3882 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 3883 3883 3884 + #define HSW_SCRATCH1 0xb038 3885 + #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 3886 + 3884 3887 #define HSW_FUSE_STRAP 0x42014 3885 3888 #define HSW_CDCLK_LIMIT (1 << 24) 3886 3889 ··· 4730 4727 #define GEN7_ROW_CHICKEN2 0xe4f4 4731 4728 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 4732 4729 #define DOP_CLOCK_GATING_DISABLE (1<<0) 4730 + 4731 + #define HSW_ROW_CHICKEN3 0xe49c 4732 + #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 4733 4733 4734 4734 #define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) 4735 4735 #define INTEL_AUDIO_DEVCL 0x808629FB
+2 -36
drivers/gpu/drm/i915/intel_display.c
··· 3941 3941 * consider. */ 3942 3942 void intel_connector_dpms(struct drm_connector *connector, int mode) 3943 3943 { 3944 - struct intel_encoder *encoder = intel_attached_encoder(connector); 3945 - 3946 3944 /* All the simple cases only support two dpms states. */ 3947 3945 if (mode != DRM_MODE_DPMS_ON) 3948 3946 mode = DRM_MODE_DPMS_OFF; ··· 3951 3953 connector->dpms = mode; 3952 3954 3953 3955 /* Only need to change hw state when actually enabled */ 3954 - if (encoder->base.crtc) 3955 - intel_encoder_dpms(encoder, mode); 3956 - else 3957 - WARN_ON(encoder->connectors_active != false); 3956 + if (connector->encoder) 3957 + intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); 3958 3958 3959 3959 intel_modeset_check_state(connector->dev); 3960 3960 } ··· 10045 10049 POSTING_READ(vga_reg); 10046 10050 } 10047 10051 10048 - static void i915_enable_vga_mem(struct drm_device *dev) 10049 - { 10050 - /* Enable VGA memory on Intel HD */ 10051 - if (HAS_PCH_SPLIT(dev)) { 10052 - vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 10053 - outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE); 10054 - vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | 10055 - VGA_RSRC_LEGACY_MEM | 10056 - VGA_RSRC_NORMAL_IO | 10057 - VGA_RSRC_NORMAL_MEM); 10058 - vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 10059 - } 10060 - } 10061 - 10062 - void i915_disable_vga_mem(struct drm_device *dev) 10063 - { 10064 - /* Disable VGA memory on Intel HD */ 10065 - if (HAS_PCH_SPLIT(dev)) { 10066 - vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 10067 - outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE); 10068 - vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | 10069 - VGA_RSRC_NORMAL_IO | 10070 - VGA_RSRC_NORMAL_MEM); 10071 - vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 10072 - } 10073 - } 10074 - 10075 10052 void intel_modeset_init_hw(struct drm_device *dev) 10076 10053 { 10077 10054 intel_init_power_well(dev); ··· 10323 10354 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { 10324 10355 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 10325 10356 i915_disable_vga(dev); 10326 - i915_disable_vga_mem(dev); 10327 10357 } 10328 10358 } 10329 10359 ··· 10535 10567 } 10536 10568 10537 10569 intel_disable_fbc(dev); 10538 - 10539 - i915_enable_vga_mem(dev); 10540 10570 10541 10571 intel_disable_gt_powersave(dev); 10542 10572
+1 -1
drivers/gpu/drm/i915/intel_dp.c
··· 1467 1467 1468 1468 /* Avoid continuous PSR exit by masking memup and hpd */ 1469 1469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP | 1470 - EDP_PSR_DEBUG_MASK_HPD); 1470 + EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1471 1471 1472 1472 intel_dp->psr_setup_done = true; 1473 1473 }
-1
drivers/gpu/drm/i915/intel_drv.h
··· 793 793 extern void hsw_pc8_restore_interrupts(struct drm_device *dev); 794 794 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); 795 795 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); 796 - extern void i915_disable_vga_mem(struct drm_device *dev); 797 796 798 797 #endif /* __INTEL_DRV_H__ */
+7 -2
drivers/gpu/drm/i915/intel_pm.c
··· 3864 3864 dev_priv->rps.rpe_delay), 3865 3865 dev_priv->rps.rpe_delay); 3866 3866 3867 - INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); 3868 - 3869 3867 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); 3870 3868 3871 3869 gen6_enable_rps_interrupts(dev); ··· 4953 4955 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 4954 4956 GEN7_WA_L3_CHICKEN_MODE); 4955 4957 4958 + /* L3 caching of data atomics doesn't work -- disable it. */ 4959 + I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 4960 + I915_WRITE(HSW_ROW_CHICKEN3, 4961 + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 4962 + 4956 4963 /* This is required by WaCatErrorRejectionIssue:hsw */ 4957 4964 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 4958 4965 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | ··· 5684 5681 5685 5682 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 5686 5683 intel_gen6_powersave_work); 5684 + 5685 + INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); 5687 5686 } 5688 5687
+1 -1
drivers/gpu/drm/nouveau/core/subdev/mc/base.c
··· 113 113 pmc->use_msi = false; 114 114 break; 115 115 default: 116 - pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", true); 116 + pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", false); 117 117 if (pmc->use_msi) { 118 118 pmc->use_msi = pci_enable_msi(device->pdev) == 0; 119 119 if (pmc->use_msi) {
+3 -3
drivers/gpu/drm/radeon/btc_dpm.c
··· 1930 1930 } 1931 1931 j++; 1932 1932 1933 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1933 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1934 1934 return -EINVAL; 1935 1935 1936 1936 tmp = RREG32(MC_PMG_CMD_MRS); ··· 1945 1945 } 1946 1946 j++; 1947 1947 1948 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1948 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1949 1949 return -EINVAL; 1950 1950 break; 1951 1951 case MC_SEQ_RESERVE_M >> 2: ··· 1959 1959 } 1960 1960 j++; 1961 1961 1962 - if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1962 + if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE) 1963 1963 return -EINVAL; 1964 1964 break; 1965 1965 default:
+6
drivers/gpu/drm/radeon/cik.c
··· 77 77 static void cik_program_aspm(struct radeon_device *rdev); 78 78 static void cik_init_pg(struct radeon_device *rdev); 79 79 static void cik_init_cg(struct radeon_device *rdev); 80 + static void cik_fini_pg(struct radeon_device *rdev); 81 + static void cik_fini_cg(struct radeon_device *rdev); 80 82 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev, 81 83 bool enable); 82 84 ··· 4186 4184 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 4187 4185 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 4188 4186 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 4187 + 4188 + /* disable CG/PG */ 4189 + cik_fini_pg(rdev); 4190 + cik_fini_cg(rdev); 4189 4191 4190 4192 /* stop the rlc */ 4191 4193 cik_rlc_stop(rdev);
+1 -1
drivers/gpu/drm/radeon/evergreen.c
··· 3131 3131 rdev->config.evergreen.sx_max_export_size = 256; 3132 3132 rdev->config.evergreen.sx_max_export_pos_size = 64; 3133 3133 rdev->config.evergreen.sx_max_export_smx_size = 192; 3134 - rdev->config.evergreen.max_hw_contexts = 8; 3134 + rdev->config.evergreen.max_hw_contexts = 4; 3135 3135 rdev->config.evergreen.sq_num_cf_insts = 2; 3136 3136 3137 3137 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
+1 -2
drivers/gpu/drm/radeon/evergreen_hdmi.c
··· 288 288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 289 289 290 290 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 291 - HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 292 - HDMI_ACR_SOURCE); /* select SW CTS value */ 291 + HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 293 292 294 293 evergreen_hdmi_update_ACR(encoder, mode->clock); 295 294
+2 -2
drivers/gpu/drm/radeon/evergreend.h
··· 1501 1501 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1502 1502 */ 1503 1503 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1504 - /* 0 - SRC_ADDR 1504 + /* 0 - DST_ADDR 1505 1505 * 1 - GDS 1506 1506 */ 1507 1507 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) ··· 1516 1516 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1517 1517 /* COMMAND */ 1518 1518 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1519 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1519 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1520 1520 /* 0 - none 1521 1521 * 1 - 8 in 16 1522 1522 * 2 - 8 in 32
+14 -7
drivers/gpu/drm/radeon/r600_hdmi.c
··· 57 57 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { 58 58 /* 32kHz 44.1kHz 48kHz */ 59 59 /* Clock N CTS N CTS N CTS */ 60 - { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 60 + { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ 61 61 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ 62 62 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ 63 63 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ 64 64 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ 65 65 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ 66 - { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 66 + { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ 67 67 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ 68 - { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 68 + { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ 69 69 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ 70 70 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ 71 71 }; ··· 75 75 */ 76 76 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) 77 77 { 78 - if (*CTS == 0) 79 - *CTS = clock * N / (128 * freq) * 1000; 78 + u64 n; 79 + u32 d; 80 + 81 + if (*CTS == 0) { 82 + n = (u64)clock * (u64)N * 1000ULL; 83 + d = 128 * freq; 84 + do_div(n, d); 85 + *CTS = n; 86 + } 80 87 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", 81 88 N, *CTS, freq); 82 89 } ··· 451 444 } 452 445 453 446 WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 454 - HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 455 - HDMI0_ACR_SOURCE); /* select SW CTS value */ 447 + HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */ 448 + HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ 456 449 457 450 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 458 451 HDMI0_NULL_SEND | /* send null packets when required */
+1 -1
drivers/gpu/drm/radeon/r600d.h
··· 1523 1523 */ 1524 1524 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1525 1525 /* COMMAND */ 1526 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1526 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1527 1527 /* 0 - none 1528 1528 * 1 - 8 in 16 1529 1529 * 2 - 8 in 32
+3
drivers/gpu/drm/radeon/radeon_pm.c
··· 945 945 if (enable) { 946 946 mutex_lock(&rdev->pm.mutex); 947 947 rdev->pm.dpm.uvd_active = true; 948 + /* disable this for now */ 949 + #if 0 948 950 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 949 951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 950 952 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) ··· 956 954 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 957 955 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 958 956 else 957 + #endif 959 958 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 960 959 rdev->pm.dpm.state = dpm_state; 961 960 mutex_unlock(&rdev->pm.mutex);
+2 -2
drivers/gpu/drm/radeon/radeon_test.c
··· 36 36 struct radeon_bo *vram_obj = NULL; 37 37 struct radeon_bo **gtt_obj = NULL; 38 38 uint64_t gtt_addr, vram_addr; 39 - unsigned i, n, size; 40 - int r, ring; 39 + unsigned n, size; 40 + int i, r, ring; 41 41 42 42 switch (flag) { 43 43 case RADEON_TEST_COPY_DMA:
+2 -1
drivers/gpu/drm/radeon/radeon_uvd.c
··· 798 798 (rdev->pm.dpm.hd != hd)) { 799 799 rdev->pm.dpm.sd = sd; 800 800 rdev->pm.dpm.hd = hd; 801 - streams_changed = true; 801 + /* disable this for now */ 802 + /*streams_changed = true;*/ 802 803 } 803 804 } 804 805
+10
drivers/gpu/drm/radeon/si.c
··· 85 85 uint32_t incr, uint32_t flags); 86 86 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev, 87 87 bool enable); 88 + static void si_fini_pg(struct radeon_device *rdev); 89 + static void si_fini_cg(struct radeon_device *rdev); 90 + static void si_rlc_stop(struct radeon_device *rdev); 88 91 89 92 static const u32 verde_rlc_save_restore_register_list[] = 90 93 { ··· 3610 3607 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3611 3608 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3612 3609 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3610 + 3611 + /* disable PG/CG */ 3612 + si_fini_pg(rdev); 3613 + si_fini_cg(rdev); 3614 + 3615 + /* stop the rlc */ 3616 + si_rlc_stop(rdev); 3613 3617 3614 3618 /* Disable CP parsing/prefetching */ 3615 3619 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+3 -3
drivers/gpu/drm/radeon/si_dpm.c
··· 5208 5208 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5209 5209 } 5210 5210 j++; 5211 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5211 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5212 5212 return -EINVAL; 5213 5213 5214 5214 if (!pi->mem_gddr5) { ··· 5218 5218 table->mc_reg_table_entry[k].mc_data[j] = 5219 5219 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5220 5220 j++; 5221 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5221 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5222 5222 return -EINVAL; 5223 5223 } 5224 5224 break; ··· 5231 5231 (temp_reg & 0xffff0000) | 5232 5232 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5233 5233 j++; 5234 - if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5234 + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5235 5235 return -EINVAL; 5236 5236 break; 5237 5237 default:
+2 -2
drivers/gpu/drm/radeon/sid.h
··· 1553 1553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1554 1554 */ 1555 1555 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1556 - /* 0 - SRC_ADDR 1556 + /* 0 - DST_ADDR 1557 1557 * 1 - GDS 1558 1558 */ 1559 1559 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) ··· 1568 1568 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1569 1569 /* COMMAND */ 1570 1570 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1571 - # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1571 + # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1572 1572 /* 0 - none 1573 1573 * 1 - 8 in 16 1574 1574 * 2 - 8 in 32
+1 -1
drivers/gpu/drm/radeon/trinity_dpm.c
··· 1868 1868 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 1869 1869 pi->at[i] = TRINITY_AT_DFLT; 1870 1870 1871 - pi->enable_bapm = true; 1871 + pi->enable_bapm = false; 1872 1872 pi->enable_nbps_policy = true; 1873 1873 pi->enable_sclk_ds = true; 1874 1874 pi->enable_gfx_power_gating = true;
-7
include/linux/vgaarb.h
··· 65 65 * out of the arbitration process (and can be safe to take 66 66 * interrupts at any time. 67 67 */ 68 - #if defined(CONFIG_VGA_ARB) 69 68 extern void vga_set_legacy_decoding(struct pci_dev *pdev, 70 69 unsigned int decodes); 71 - #else 72 - static inline void vga_set_legacy_decoding(struct pci_dev *pdev, 73 - unsigned int decodes) 74 - { 75 - } 76 - #endif 77 70 78 71 /** 79 72 * vga_get - acquire & locks VGA resources