Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
fbdev: au1100fb: Fold au1100fb.h into its only user
This gets rid of a header that is only used once. The copyrights and
license specifications are all already covered in the au1100fb.c file.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Helge Deller <deller@gmx.de>
authored by
Uwe Kleine-König
and committed by
Helge Deller
cd849d26
bcf4373e
+338
-373
+338
-1
drivers/video/fbdev/au1100fb.c
+338
-1
drivers/video/fbdev/au1100fb.c
···
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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-
#include "au1100fb.h"
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#if defined(__BIG_ENDIAN)
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
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#else
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#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
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#endif
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#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
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/********************************************************************/
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/* LCD controller restrictions */
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#define AU1100_LCD_MAX_XRES 800
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#define AU1100_LCD_MAX_YRES 600
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#define AU1100_LCD_MAX_BPP 16
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#define AU1100_LCD_MAX_CLK 48000000
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#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
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/* Default number of visible screen buffer to allocate */
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#define AU1100FB_NBR_VIDEO_BUFFERS 4
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/********************************************************************/
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struct au1100fb_panel
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{
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const char name[25]; /* Full name <vendor>_<model> */
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u32 control_base; /* Mode-independent control values */
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u32 clkcontrol_base; /* Panel pixclock preferences */
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u32 horztiming;
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u32 verttiming;
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u32 xres; /* Maximum horizontal resolution */
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u32 yres; /* Maximum vertical resolution */
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u32 bpp; /* Maximum depth supported */
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};
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struct au1100fb_regs
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{
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u32 lcd_control;
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u32 lcd_intstatus;
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u32 lcd_intenable;
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u32 lcd_horztiming;
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u32 lcd_verttiming;
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u32 lcd_clkcontrol;
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u32 lcd_dmaaddr0;
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u32 lcd_dmaaddr1;
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u32 lcd_words;
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u32 lcd_pwmdiv;
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u32 lcd_pwmhi;
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u32 reserved[(0x0400-0x002C)/4];
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u32 lcd_palettebase[256];
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};
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struct au1100fb_device {
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struct fb_info info; /* FB driver info record */
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struct au1100fb_panel *panel; /* Panel connected to this device */
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struct au1100fb_regs* regs; /* Registers memory map */
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size_t regs_len;
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unsigned int regs_phys;
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#ifdef CONFIG_PM
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/* stores the register values during suspend */
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struct au1100fb_regs pm_regs;
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#endif
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unsigned char* fb_mem; /* FrameBuffer memory map */
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size_t fb_len;
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dma_addr_t fb_phys;
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int panel_idx;
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struct clk *lcdclk;
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struct device *dev;
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};
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/********************************************************************/
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#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
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#define LCD_CONTROL_SBB_BIT 21
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#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
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#define LCD_CONTROL_SBPPF_BIT 18
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#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
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#define LCD_CONTROL_WP (1<<17)
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#define LCD_CONTROL_WD (1<<16)
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#define LCD_CONTROL_C (1<<15)
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#define LCD_CONTROL_SM_BIT 13
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#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
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#define LCD_CONTROL_DB (1<<12)
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#define LCD_CONTROL_CCO (1<<11)
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#define LCD_CONTROL_DP (1<<10)
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#define LCD_CONTROL_PO_BIT 8
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#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
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#define LCD_CONTROL_MPI (1<<7)
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#define LCD_CONTROL_PT (1<<6)
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#define LCD_CONTROL_PC (1<<5)
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#define LCD_CONTROL_BPP_BIT 1
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#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
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#define LCD_CONTROL_GO (1<<0)
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#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
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#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
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#define LCD_INT_SD (1<<7)
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#define LCD_INT_OF (1<<6)
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#define LCD_INT_UF (1<<5)
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#define LCD_INT_SA (1<<3)
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#define LCD_INT_SS (1<<2)
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#define LCD_INT_S1 (1<<1)
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#define LCD_INT_S0 (1<<0)
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#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
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#define LCD_HORZTIMING_HN2_BIT 24
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#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
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#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
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#define LCD_HORZTIMING_HN1_BIT 16
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#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
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#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
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#define LCD_HORZTIMING_HPW_BIT 10
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#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
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#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
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#define LCD_HORZTIMING_PPL_BIT 0
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#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
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#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
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#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
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#define LCD_VERTTIMING_VN2_BIT 24
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#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
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#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
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#define LCD_VERTTIMING_VN1_BIT 16
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#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
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#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
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#define LCD_VERTTIMING_VPW_BIT 10
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#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
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#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
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#define LCD_VERTTIMING_LPP_BIT 0
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#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
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#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
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#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
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#define LCD_CLKCONTROL_IB (1<<18)
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#define LCD_CLKCONTROL_IC (1<<17)
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#define LCD_CLKCONTROL_IH (1<<16)
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#define LCD_CLKCONTROL_IV (1<<15)
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#define LCD_CLKCONTROL_BF_BIT 10
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#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
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#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
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#define LCD_CLKCONTROL_PCD_BIT 0
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#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
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#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
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#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
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#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
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#define LCD_DMA_SA_BIT 5
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#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
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#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
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#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
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#define LCD_WRD_WRDS_BIT 0
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#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
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#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
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#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
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#define LCD_PWMDIV_EN (1<<12)
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#define LCD_PWMDIV_PWMDIV_BIT 0
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#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
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#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
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#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
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#define LCD_PWMHI_PWMHI1_BIT 12
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#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
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#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
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#define LCD_PWMHI_PWMHI0_BIT 0
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#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
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#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
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#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
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#define LCD_PALLETTE_MONO_MI_BIT 0
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#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
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#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
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#define LCD_PALLETTE_COLOR_RI_BIT 8
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#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
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#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
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#define LCD_PALLETTE_COLOR_GI_BIT 4
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#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
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#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
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#define LCD_PALLETTE_COLOR_BI_BIT 0
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#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
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#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
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+
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#define LCD_PALLETTE_TFT_DC_BIT 0
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#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
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#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
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/********************************************************************/
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/* List of panels known to work with the AU1100 LCD controller.
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* To add a new panel, enter the same specifications as the
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* Generic_TFT one, and MAKE SURE that it doesn't conflicts
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* with the controller restrictions. Restrictions are:
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*
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* STN color panels: max_bpp <= 12
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* STN mono panels: max_bpp <= 4
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* TFT panels: max_bpp <= 16
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* max_xres <= 800
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* max_yres <= 600
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*/
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static struct au1100fb_panel known_lcd_panels[] =
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{
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/* 800x600x16bpp CRT */
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[0] = {
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.name = "CRT_800x600_16",
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.xres = 800,
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.yres = 600,
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.bpp = 16,
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.control_base = 0x0004886A |
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LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
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LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
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.clkcontrol_base = 0x00020000,
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.horztiming = 0x005aff1f,
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.verttiming = 0x16000e57,
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},
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/* just the standard LCD */
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[1] = {
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.name = "WWPC LCD",
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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.control_base = 0x0006806A,
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.horztiming = 0x0A1010EF,
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.verttiming = 0x0301013F,
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.clkcontrol_base = 0x00018001,
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},
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/* Sharp 320x240 TFT panel */
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[2] = {
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.name = "Sharp_LQ038Q5DR01",
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.xres = 320,
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.yres = 240,
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.bpp = 16,
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.control_base =
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( LCD_CONTROL_SBPPF_565
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| LCD_CONTROL_C
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| LCD_CONTROL_SM_0
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| LCD_CONTROL_DEFAULT_PO
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| LCD_CONTROL_PT
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| LCD_CONTROL_PC
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| LCD_CONTROL_BPP_16 ),
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.horztiming =
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( LCD_HORZTIMING_HN2_N(8)
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| LCD_HORZTIMING_HN1_N(60)
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| LCD_HORZTIMING_HPW_N(12)
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| LCD_HORZTIMING_PPL_N(320) ),
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.verttiming =
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( LCD_VERTTIMING_VN2_N(5)
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| LCD_VERTTIMING_VN1_N(17)
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| LCD_VERTTIMING_VPW_N(1)
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| LCD_VERTTIMING_LPP_N(240) ),
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
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},
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+
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/* Hitachi SP14Q005 and possibly others */
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[3] = {
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.name = "Hitachi_SP14Qxxx",
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.xres = 320,
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.yres = 240,
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.bpp = 4,
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.control_base =
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( LCD_CONTROL_C
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| LCD_CONTROL_BPP_4 ),
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.horztiming =
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( LCD_HORZTIMING_HN2_N(1)
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| LCD_HORZTIMING_HN1_N(1)
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| LCD_HORZTIMING_HPW_N(1)
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| LCD_HORZTIMING_PPL_N(320) ),
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.verttiming =
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+
( LCD_VERTTIMING_VN2_N(1)
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| LCD_VERTTIMING_VN1_N(1)
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| LCD_VERTTIMING_VPW_N(1)
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| LCD_VERTTIMING_LPP_N(240) ),
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
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+
},
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+
368
+
/* Generic 640x480 TFT panel */
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[4] = {
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.name = "TFT_640x480_16",
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.xres = 640,
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+
.yres = 480,
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.bpp = 16,
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.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
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+
.horztiming = 0x3434d67f,
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+
.verttiming = 0x0e0e39df,
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.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
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+
},
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+
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/* Pb1100 LCDB 640x480 PrimeView TFT panel */
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[5] = {
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.name = "PrimeView_640x480_16",
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+
.xres = 640,
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.yres = 480,
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.bpp = 16,
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.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
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.horztiming = 0x0e4bfe7f,
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+
.verttiming = 0x210805df,
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.clkcontrol_base = 0x00038001,
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+
},
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+
};
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+
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/********************************************************************/
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+
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+
/* Inline helpers */
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+
397
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#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
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+
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
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+
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
400
+
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
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401
65
402
#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_MIPS)
66
403
/* This is only defined to be able to compile this driver on non-mips platforms */
-372
drivers/video/fbdev/au1100fb.h
-372
drivers/video/fbdev/au1100fb.h
···
1
-
/*
2
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* BRIEF MODULE DESCRIPTION
3
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* Hardware definitions for the Au1100 LCD controller
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*
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* Copyright 2002 MontaVista Software
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* Copyright 2002 Alchemy Semiconductor
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* Author: Alchemy Semiconductor, MontaVista Software
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
11
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* Free Software Foundation; either version 2 of the License, or (at your
12
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21
-
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22
-
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23
-
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24
-
*
25
-
* You should have received a copy of the GNU General Public License along
26
-
* with this program; if not, write to the Free Software Foundation, Inc.,
27
-
* 675 Mass Ave, Cambridge, MA 02139, USA.
28
-
*/
29
-
30
-
#ifndef _AU1100LCD_H
31
-
#define _AU1100LCD_H
32
-
33
-
#if defined(__BIG_ENDIAN)
34
-
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
35
-
#else
36
-
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
37
-
#endif
38
-
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
39
-
40
-
/********************************************************************/
41
-
42
-
/* LCD controller restrictions */
43
-
#define AU1100_LCD_MAX_XRES 800
44
-
#define AU1100_LCD_MAX_YRES 600
45
-
#define AU1100_LCD_MAX_BPP 16
46
-
#define AU1100_LCD_MAX_CLK 48000000
47
-
#define AU1100_LCD_NBR_PALETTE_ENTRIES 256
48
-
49
-
/* Default number of visible screen buffer to allocate */
50
-
#define AU1100FB_NBR_VIDEO_BUFFERS 4
51
-
52
-
/********************************************************************/
53
-
54
-
struct au1100fb_panel
55
-
{
56
-
const char name[25]; /* Full name <vendor>_<model> */
57
-
58
-
u32 control_base; /* Mode-independent control values */
59
-
u32 clkcontrol_base; /* Panel pixclock preferences */
60
-
61
-
u32 horztiming;
62
-
u32 verttiming;
63
-
64
-
u32 xres; /* Maximum horizontal resolution */
65
-
u32 yres; /* Maximum vertical resolution */
66
-
u32 bpp; /* Maximum depth supported */
67
-
};
68
-
69
-
struct au1100fb_regs
70
-
{
71
-
u32 lcd_control;
72
-
u32 lcd_intstatus;
73
-
u32 lcd_intenable;
74
-
u32 lcd_horztiming;
75
-
u32 lcd_verttiming;
76
-
u32 lcd_clkcontrol;
77
-
u32 lcd_dmaaddr0;
78
-
u32 lcd_dmaaddr1;
79
-
u32 lcd_words;
80
-
u32 lcd_pwmdiv;
81
-
u32 lcd_pwmhi;
82
-
u32 reserved[(0x0400-0x002C)/4];
83
-
u32 lcd_palettebase[256];
84
-
};
85
-
86
-
struct au1100fb_device {
87
-
88
-
struct fb_info info; /* FB driver info record */
89
-
90
-
struct au1100fb_panel *panel; /* Panel connected to this device */
91
-
92
-
struct au1100fb_regs* regs; /* Registers memory map */
93
-
size_t regs_len;
94
-
unsigned int regs_phys;
95
-
96
-
#ifdef CONFIG_PM
97
-
/* stores the register values during suspend */
98
-
struct au1100fb_regs pm_regs;
99
-
#endif
100
-
101
-
unsigned char* fb_mem; /* FrameBuffer memory map */
102
-
size_t fb_len;
103
-
dma_addr_t fb_phys;
104
-
int panel_idx;
105
-
struct clk *lcdclk;
106
-
struct device *dev;
107
-
};
108
-
109
-
/********************************************************************/
110
-
111
-
#define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
112
-
#define LCD_CONTROL_SBB_BIT 21
113
-
#define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
114
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#define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
115
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#define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
116
-
#define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
117
-
#define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
118
-
#define LCD_CONTROL_SBPPF_BIT 18
119
-
#define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
120
-
#define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
121
-
#define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
122
-
#define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
123
-
#define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
124
-
#define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
125
-
#define LCD_CONTROL_WP (1<<17)
126
-
#define LCD_CONTROL_WD (1<<16)
127
-
#define LCD_CONTROL_C (1<<15)
128
-
#define LCD_CONTROL_SM_BIT 13
129
-
#define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
130
-
#define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
131
-
#define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
132
-
#define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
133
-
#define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
134
-
#define LCD_CONTROL_DB (1<<12)
135
-
#define LCD_CONTROL_CCO (1<<11)
136
-
#define LCD_CONTROL_DP (1<<10)
137
-
#define LCD_CONTROL_PO_BIT 8
138
-
#define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
139
-
#define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
140
-
#define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
141
-
#define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
142
-
#define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
143
-
#define LCD_CONTROL_MPI (1<<7)
144
-
#define LCD_CONTROL_PT (1<<6)
145
-
#define LCD_CONTROL_PC (1<<5)
146
-
#define LCD_CONTROL_BPP_BIT 1
147
-
#define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
148
-
#define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
149
-
#define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
150
-
#define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
151
-
#define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
152
-
#define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
153
-
#define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
154
-
#define LCD_CONTROL_GO (1<<0)
155
-
156
-
#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
157
-
#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
158
-
#define LCD_INT_SD (1<<7)
159
-
#define LCD_INT_OF (1<<6)
160
-
#define LCD_INT_UF (1<<5)
161
-
#define LCD_INT_SA (1<<3)
162
-
#define LCD_INT_SS (1<<2)
163
-
#define LCD_INT_S1 (1<<1)
164
-
#define LCD_INT_S0 (1<<0)
165
-
166
-
#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
167
-
#define LCD_HORZTIMING_HN2_BIT 24
168
-
#define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
169
-
#define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
170
-
#define LCD_HORZTIMING_HN1_BIT 16
171
-
#define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
172
-
#define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
173
-
#define LCD_HORZTIMING_HPW_BIT 10
174
-
#define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
175
-
#define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
176
-
#define LCD_HORZTIMING_PPL_BIT 0
177
-
#define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
178
-
#define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
179
-
180
-
#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
181
-
#define LCD_VERTTIMING_VN2_BIT 24
182
-
#define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
183
-
#define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
184
-
#define LCD_VERTTIMING_VN1_BIT 16
185
-
#define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
186
-
#define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
187
-
#define LCD_VERTTIMING_VPW_BIT 10
188
-
#define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
189
-
#define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
190
-
#define LCD_VERTTIMING_LPP_BIT 0
191
-
#define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
192
-
#define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
193
-
194
-
#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
195
-
#define LCD_CLKCONTROL_IB (1<<18)
196
-
#define LCD_CLKCONTROL_IC (1<<17)
197
-
#define LCD_CLKCONTROL_IH (1<<16)
198
-
#define LCD_CLKCONTROL_IV (1<<15)
199
-
#define LCD_CLKCONTROL_BF_BIT 10
200
-
#define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
201
-
#define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
202
-
#define LCD_CLKCONTROL_PCD_BIT 0
203
-
#define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
204
-
#define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
205
-
206
-
#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
207
-
#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
208
-
#define LCD_DMA_SA_BIT 5
209
-
#define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
210
-
#define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
211
-
212
-
#define LCD_WORDS (AU1100_LCD_BASE + 0x20)
213
-
#define LCD_WRD_WRDS_BIT 0
214
-
#define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
215
-
#define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
216
-
217
-
#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
218
-
#define LCD_PWMDIV_EN (1<<12)
219
-
#define LCD_PWMDIV_PWMDIV_BIT 0
220
-
#define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
221
-
#define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
222
-
223
-
#define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
224
-
#define LCD_PWMHI_PWMHI1_BIT 12
225
-
#define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
226
-
#define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
227
-
#define LCD_PWMHI_PWMHI0_BIT 0
228
-
#define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
229
-
#define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
230
-
231
-
#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
232
-
#define LCD_PALLETTE_MONO_MI_BIT 0
233
-
#define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
234
-
#define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
235
-
236
-
#define LCD_PALLETTE_COLOR_RI_BIT 8
237
-
#define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
238
-
#define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
239
-
#define LCD_PALLETTE_COLOR_GI_BIT 4
240
-
#define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
241
-
#define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
242
-
#define LCD_PALLETTE_COLOR_BI_BIT 0
243
-
#define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
244
-
#define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
245
-
246
-
#define LCD_PALLETTE_TFT_DC_BIT 0
247
-
#define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
248
-
#define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
249
-
250
-
/********************************************************************/
251
-
252
-
/* List of panels known to work with the AU1100 LCD controller.
253
-
* To add a new panel, enter the same specifications as the
254
-
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
255
-
* with the controller restrictions. Restrictions are:
256
-
*
257
-
* STN color panels: max_bpp <= 12
258
-
* STN mono panels: max_bpp <= 4
259
-
* TFT panels: max_bpp <= 16
260
-
* max_xres <= 800
261
-
* max_yres <= 600
262
-
*/
263
-
static struct au1100fb_panel known_lcd_panels[] =
264
-
{
265
-
/* 800x600x16bpp CRT */
266
-
[0] = {
267
-
.name = "CRT_800x600_16",
268
-
.xres = 800,
269
-
.yres = 600,
270
-
.bpp = 16,
271
-
.control_base = 0x0004886A |
272
-
LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
273
-
LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
274
-
.clkcontrol_base = 0x00020000,
275
-
.horztiming = 0x005aff1f,
276
-
.verttiming = 0x16000e57,
277
-
},
278
-
/* just the standard LCD */
279
-
[1] = {
280
-
.name = "WWPC LCD",
281
-
.xres = 240,
282
-
.yres = 320,
283
-
.bpp = 16,
284
-
.control_base = 0x0006806A,
285
-
.horztiming = 0x0A1010EF,
286
-
.verttiming = 0x0301013F,
287
-
.clkcontrol_base = 0x00018001,
288
-
},
289
-
/* Sharp 320x240 TFT panel */
290
-
[2] = {
291
-
.name = "Sharp_LQ038Q5DR01",
292
-
.xres = 320,
293
-
.yres = 240,
294
-
.bpp = 16,
295
-
.control_base =
296
-
( LCD_CONTROL_SBPPF_565
297
-
| LCD_CONTROL_C
298
-
| LCD_CONTROL_SM_0
299
-
| LCD_CONTROL_DEFAULT_PO
300
-
| LCD_CONTROL_PT
301
-
| LCD_CONTROL_PC
302
-
| LCD_CONTROL_BPP_16 ),
303
-
.horztiming =
304
-
( LCD_HORZTIMING_HN2_N(8)
305
-
| LCD_HORZTIMING_HN1_N(60)
306
-
| LCD_HORZTIMING_HPW_N(12)
307
-
| LCD_HORZTIMING_PPL_N(320) ),
308
-
.verttiming =
309
-
( LCD_VERTTIMING_VN2_N(5)
310
-
| LCD_VERTTIMING_VN1_N(17)
311
-
| LCD_VERTTIMING_VPW_N(1)
312
-
| LCD_VERTTIMING_LPP_N(240) ),
313
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
314
-
},
315
-
316
-
/* Hitachi SP14Q005 and possibly others */
317
-
[3] = {
318
-
.name = "Hitachi_SP14Qxxx",
319
-
.xres = 320,
320
-
.yres = 240,
321
-
.bpp = 4,
322
-
.control_base =
323
-
( LCD_CONTROL_C
324
-
| LCD_CONTROL_BPP_4 ),
325
-
.horztiming =
326
-
( LCD_HORZTIMING_HN2_N(1)
327
-
| LCD_HORZTIMING_HN1_N(1)
328
-
| LCD_HORZTIMING_HPW_N(1)
329
-
| LCD_HORZTIMING_PPL_N(320) ),
330
-
.verttiming =
331
-
( LCD_VERTTIMING_VN2_N(1)
332
-
| LCD_VERTTIMING_VN1_N(1)
333
-
| LCD_VERTTIMING_VPW_N(1)
334
-
| LCD_VERTTIMING_LPP_N(240) ),
335
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
336
-
},
337
-
338
-
/* Generic 640x480 TFT panel */
339
-
[4] = {
340
-
.name = "TFT_640x480_16",
341
-
.xres = 640,
342
-
.yres = 480,
343
-
.bpp = 16,
344
-
.control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
345
-
.horztiming = 0x3434d67f,
346
-
.verttiming = 0x0e0e39df,
347
-
.clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
348
-
},
349
-
350
-
/* Pb1100 LCDB 640x480 PrimeView TFT panel */
351
-
[5] = {
352
-
.name = "PrimeView_640x480_16",
353
-
.xres = 640,
354
-
.yres = 480,
355
-
.bpp = 16,
356
-
.control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
357
-
.horztiming = 0x0e4bfe7f,
358
-
.verttiming = 0x210805df,
359
-
.clkcontrol_base = 0x00038001,
360
-
},
361
-
};
362
-
363
-
/********************************************************************/
364
-
365
-
/* Inline helpers */
366
-
367
-
#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
368
-
#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
369
-
#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
370
-
#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
371
-
372
-
#endif /* _AU1100LCD_H */