Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch '20231123064735.2979802-2-quic_imrashai@quicinc.com' into clk-for-6.8
Merge the ECPI clock controller through a topic branch to make it
possible to merge the clock constants into the DeviceTree branch as
well.
+215
+68
Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml
+68
Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Imran Shaik <quic_imrashai@quicinc.com>
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description: |
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Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
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module which supports the clocks, resets on QDU1000 and QRU1000
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See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
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properties:
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compatible:
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enum:
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- qcom,qdu1000-ecpricc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: GPLL1 source from GCC
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- description: GPLL2 source from GCC
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- description: GPLL3 source from GCC
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- description: GPLL4 source from GCC
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- description: GPLL5 source from GCC
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,qdu1000-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@280000 {
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compatible = "qcom,qdu1000-ecpricc";
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reg = <0x00280000 0x31c00>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
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<&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
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include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
···
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
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#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
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/* ECPRI_CC clocks */
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#define ECPRI_CC_PLL0 0
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#define ECPRI_CC_PLL1 1
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#define ECPRI_CC_ECPRI_CG_CLK 2
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#define ECPRI_CC_ECPRI_CLK_SRC 3
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#define ECPRI_CC_ECPRI_DMA_CLK 4
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#define ECPRI_CC_ECPRI_DMA_CLK_SRC 5
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#define ECPRI_CC_ECPRI_DMA_NOC_CLK 6
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#define ECPRI_CC_ECPRI_FAST_CLK 7
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#define ECPRI_CC_ECPRI_FAST_CLK_SRC 8
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#define ECPRI_CC_ECPRI_FAST_DIV2_CLK 9
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#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 10
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#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 11
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#define ECPRI_CC_ECPRI_FR_CLK 12
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#define ECPRI_CC_ECPRI_ORAN_CLK_SRC 13
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#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 14
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#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 15
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#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 16
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#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 17
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#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 18
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#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 19
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#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 20
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#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 21
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#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 22
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#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 23
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#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 24
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#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 25
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#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 26
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#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 27
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#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 28
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#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 29
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#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 30
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#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 31
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#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 32
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#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 33
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#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 34
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#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 35
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 36
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 37
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 38
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 39
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 40
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 41
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 42
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#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 43
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#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 44
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 45
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 46
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 47
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 48
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 49
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 50
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 51
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#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 52
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#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 53
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 54
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 55
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 56
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 57
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 58
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 59
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 60
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#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 61
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#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 62
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#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 63
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#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 64
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#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 65
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#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 66
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#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 67
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#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 68
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#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 69
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#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 70
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#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 71
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#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 72
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#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 73
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#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 74
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#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 75
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#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 76
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#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 77
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#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 78
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#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 79
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#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80
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#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 81
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#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 82
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#define ECPRI_CC_MSS_EMAC_CLK 83
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#define ECPRI_CC_MSS_EMAC_CLK_SRC 84
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#define ECPRI_CC_MSS_ORAN_CLK 85
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#define ECPRI_CC_PHY0_LANE0_RX_CLK 86
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#define ECPRI_CC_PHY0_LANE0_TX_CLK 87
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#define ECPRI_CC_PHY0_LANE1_RX_CLK 88
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#define ECPRI_CC_PHY0_LANE1_TX_CLK 89
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#define ECPRI_CC_PHY0_LANE2_RX_CLK 90
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#define ECPRI_CC_PHY0_LANE2_TX_CLK 91
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#define ECPRI_CC_PHY0_LANE3_RX_CLK 92
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#define ECPRI_CC_PHY0_LANE3_TX_CLK 93
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#define ECPRI_CC_PHY1_LANE0_RX_CLK 94
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#define ECPRI_CC_PHY1_LANE0_TX_CLK 95
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#define ECPRI_CC_PHY1_LANE1_RX_CLK 96
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#define ECPRI_CC_PHY1_LANE1_TX_CLK 97
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#define ECPRI_CC_PHY1_LANE2_RX_CLK 98
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#define ECPRI_CC_PHY1_LANE2_TX_CLK 99
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#define ECPRI_CC_PHY1_LANE3_RX_CLK 100
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#define ECPRI_CC_PHY1_LANE3_TX_CLK 101
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#define ECPRI_CC_PHY2_LANE0_RX_CLK 102
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#define ECPRI_CC_PHY2_LANE0_TX_CLK 103
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#define ECPRI_CC_PHY2_LANE1_RX_CLK 104
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#define ECPRI_CC_PHY2_LANE1_TX_CLK 105
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#define ECPRI_CC_PHY2_LANE2_RX_CLK 106
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#define ECPRI_CC_PHY2_LANE2_TX_CLK 107
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#define ECPRI_CC_PHY2_LANE3_RX_CLK 108
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#define ECPRI_CC_PHY2_LANE3_TX_CLK 109
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#define ECPRI_CC_PHY3_LANE0_RX_CLK 110
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#define ECPRI_CC_PHY3_LANE0_TX_CLK 111
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#define ECPRI_CC_PHY3_LANE1_RX_CLK 112
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#define ECPRI_CC_PHY3_LANE1_TX_CLK 113
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#define ECPRI_CC_PHY3_LANE2_RX_CLK 114
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#define ECPRI_CC_PHY3_LANE2_TX_CLK 115
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#define ECPRI_CC_PHY3_LANE3_RX_CLK 116
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#define ECPRI_CC_PHY3_LANE3_TX_CLK 117
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#define ECPRI_CC_PHY4_LANE0_RX_CLK 118
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#define ECPRI_CC_PHY4_LANE0_TX_CLK 119
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#define ECPRI_CC_PHY4_LANE1_RX_CLK 120
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#define ECPRI_CC_PHY4_LANE1_TX_CLK 121
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#define ECPRI_CC_PHY4_LANE2_RX_CLK 122
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#define ECPRI_CC_PHY4_LANE2_TX_CLK 123
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#define ECPRI_CC_PHY4_LANE3_RX_CLK 124
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#define ECPRI_CC_PHY4_LANE3_TX_CLK 125
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/* ECPRI_CC resets */
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6
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#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7
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#endif