Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
+71
-62
+71
-62
arch/ia64/kernel/ivt.S
+71
-62
arch/ia64/kernel/ivt.S
···
91
91
* (the "original") TLB miss, which may either be caused by an instruction
92
92
* fetch or a data access (or non-access).
93
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*
94
-
* What we do here is normal TLB miss handing for the _original_ miss, followed
95
-
* by inserting the TLB entry for the virtual page table page that the VHPT
96
-
* walker was attempting to access. The latter gets inserted as long
97
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* as both L1 and L2 have valid mappings for the faulting address.
98
-
* The TLB entry for the original miss gets inserted only if
99
-
* the L3 entry indicates that the page is present.
94
+
* What we do here is normal TLB miss handing for the _original_ miss,
95
+
* followed by inserting the TLB entry for the virtual page table page
96
+
* that the VHPT walker was attempting to access. The latter gets
97
+
* inserted as long as page table entry above pte level have valid
98
+
* mappings for the faulting address. The TLB entry for the original
99
+
* miss gets inserted only if the pte entry indicates that the page is
100
+
* present.
100
101
*
101
102
* do_page_fault gets invoked in the following cases:
102
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* - the faulting virtual address uses unimplemented address bits
103
-
* - the faulting virtual address has no L1, L2, or L3 mapping
104
+
* - the faulting virtual address has no valid page table mapping
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*/
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mov r16=cr.ifa // get address that caused the TLB miss
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#ifdef CONFIG_HUGETLB_PAGE
···
127
126
#endif
128
127
;;
129
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cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
130
-
shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
129
+
shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
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;;
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(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
133
132
···
138
137
(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
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(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
140
139
;;
141
-
(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
142
-
(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
140
+
(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
141
+
(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
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cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
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#ifdef CONFIG_PGTABLE_4
145
-
shr.u r28=r22,PUD_SHIFT // shift L2 index into position
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+
shr.u r28=r22,PUD_SHIFT // shift pud index into position
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#else
147
-
shr.u r18=r22,PMD_SHIFT // shift L3 index into position
146
+
shr.u r18=r22,PMD_SHIFT // shift pmd index into position
148
147
#endif
149
148
;;
150
-
ld8 r17=[r17] // fetch the L1 entry (may be 0)
149
+
ld8 r17=[r17] // get *pgd (may be 0)
151
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;;
152
-
(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
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+
(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
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#ifdef CONFIG_PGTABLE_4
154
-
dep r28=r28,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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+
dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
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154
;;
156
-
shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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-
(p7) ld8 r29=[r28] // fetch the L2 entry (may be 0)
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+
shr.u r18=r22,PMD_SHIFT // shift pmd index into position
156
+
(p7) ld8 r29=[r28] // get *pud (may be 0)
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157
;;
159
-
(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was L2 entry NULL?
160
-
dep r17=r18,r29,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
158
+
(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL?
159
+
dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
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#else
162
-
dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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+
dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
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#endif
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;;
165
-
(p7) ld8 r20=[r17] // fetch the L3 entry (may be 0)
166
-
shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
164
+
(p7) ld8 r20=[r17] // get *pmd (may be 0)
165
+
shr.u r19=r22,PAGE_SHIFT // shift pte index into position
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166
;;
168
-
(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L3 entry NULL?
169
-
dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
167
+
(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL?
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+
dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr)
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;;
171
-
(p7) ld8 r18=[r21] // read the L4 PTE
172
-
mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
170
+
(p7) ld8 r18=[r21] // read *pte
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+
mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss
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172
;;
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(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
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mov r22=cr.iha // get the VHPT address that caused the TLB miss
···
203
202
dv_serialize_data
204
203
205
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/*
206
-
* Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
205
+
* Re-check pagetable entry. If they changed, we may have received a ptc.g
207
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* between reading the pagetable and the "itc". If so, flush the entry we
208
-
* inserted and retry.
207
+
* inserted and retry. At this point, we have:
208
+
*
209
+
* r28 = equivalent of pud_offset(pgd, ifa)
210
+
* r17 = equivalent of pmd_offset(pud, ifa)
211
+
* r21 = equivalent of pte_offset(pmd, ifa)
212
+
*
213
+
* r29 = *pud
214
+
* r20 = *pmd
215
+
* r18 = *pte
209
216
*/
210
-
ld8 r25=[r21] // read L4 entry again
211
-
ld8 r26=[r17] // read L3 PTE again
217
+
ld8 r25=[r21] // read *pte again
218
+
ld8 r26=[r17] // read *pmd again
212
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#ifdef CONFIG_PGTABLE_4
213
-
ld8 r18=[r28] // read L2 entry again
220
+
ld8 r19=[r28] // read *pud again
214
221
#endif
215
222
cmp.ne p6,p7=r0,r0
216
223
;;
217
-
cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change
224
+
cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change
218
225
#ifdef CONFIG_PGTABLE_4
219
-
cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change
226
+
cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change
220
227
#endif
221
228
mov r27=PAGE_SHIFT<<2
222
229
;;
223
230
(p6) ptc.l r22,r27 // purge PTE page translation
224
-
(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L4 PTE change
231
+
(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
225
232
;;
226
233
(p6) ptc.l r16,r27 // purge translation
227
234
#endif
···
244
235
ENTRY(itlb_miss)
245
236
DBG_FAULT(1)
246
237
/*
247
-
* The ITLB handler accesses the L3 PTE via the virtually mapped linear
238
+
* The ITLB handler accesses the PTE via the virtually mapped linear
248
239
* page table. If a nested TLB miss occurs, we switch into physical
249
-
* mode, walk the page table, and then re-execute the L3 PTE read
250
-
* and go on normally after that.
240
+
* mode, walk the page table, and then re-execute the PTE read and
241
+
* go on normally after that.
251
242
*/
252
243
mov r16=cr.ifa // get virtual address
253
244
mov r29=b0 // save b0
254
245
mov r31=pr // save predicates
255
246
.itlb_fault:
256
-
mov r17=cr.iha // get virtual address of L3 PTE
247
+
mov r17=cr.iha // get virtual address of PTE
257
248
movl r30=1f // load nested fault continuation point
258
249
;;
259
-
1: ld8 r18=[r17] // read L3 PTE
250
+
1: ld8 r18=[r17] // read *pte
260
251
;;
261
252
mov b0=r29
262
253
tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
···
271
262
*/
272
263
dv_serialize_data
273
264
274
-
ld8 r19=[r17] // read L3 PTE again and see if same
265
+
ld8 r19=[r17] // read *pte again and see if same
275
266
mov r20=PAGE_SHIFT<<2 // setup page size for purge
276
267
;;
277
268
cmp.ne p7,p0=r18,r19
···
288
279
ENTRY(dtlb_miss)
289
280
DBG_FAULT(2)
290
281
/*
291
-
* The DTLB handler accesses the L3 PTE via the virtually mapped linear
282
+
* The DTLB handler accesses the PTE via the virtually mapped linear
292
283
* page table. If a nested TLB miss occurs, we switch into physical
293
-
* mode, walk the page table, and then re-execute the L3 PTE read
294
-
* and go on normally after that.
284
+
* mode, walk the page table, and then re-execute the PTE read and
285
+
* go on normally after that.
295
286
*/
296
287
mov r16=cr.ifa // get virtual address
297
288
mov r29=b0 // save b0
298
289
mov r31=pr // save predicates
299
290
dtlb_fault:
300
-
mov r17=cr.iha // get virtual address of L3 PTE
291
+
mov r17=cr.iha // get virtual address of PTE
301
292
movl r30=1f // load nested fault continuation point
302
293
;;
303
-
1: ld8 r18=[r17] // read L3 PTE
294
+
1: ld8 r18=[r17] // read *pte
304
295
;;
305
296
mov b0=r29
306
297
tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
···
315
306
*/
316
307
dv_serialize_data
317
308
318
-
ld8 r19=[r17] // read L3 PTE again and see if same
309
+
ld8 r19=[r17] // read *pte again and see if same
319
310
mov r20=PAGE_SHIFT<<2 // setup page size for purge
320
311
;;
321
312
cmp.ne p7,p0=r18,r19
···
429
420
* r30: continuation address
430
421
* r31: saved pr
431
422
*
432
-
* Output: r17: physical address of L3 PTE of faulting address
423
+
* Output: r17: physical address of PTE of faulting address
433
424
* r29: saved b0
434
425
* r30: continuation address
435
426
* r31: saved pr
···
459
450
(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
460
451
(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
461
452
;;
462
-
(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
463
-
(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
453
+
(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
454
+
(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
464
455
cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
465
456
#ifdef CONFIG_PGTABLE_4
466
-
shr.u r18=r22,PUD_SHIFT // shift L2 index into position
457
+
shr.u r18=r22,PUD_SHIFT // shift pud index into position
467
458
#else
468
-
shr.u r18=r22,PMD_SHIFT // shift L3 index into position
459
+
shr.u r18=r22,PMD_SHIFT // shift pmd index into position
469
460
#endif
470
461
;;
471
-
ld8 r17=[r17] // fetch the L1 entry (may be 0)
462
+
ld8 r17=[r17] // get *pgd (may be 0)
472
463
;;
473
-
(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
474
-
dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
464
+
(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
465
+
dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
475
466
;;
476
467
#ifdef CONFIG_PGTABLE_4
477
-
(p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
478
-
shr.u r18=r22,PMD_SHIFT // shift L3 index into position
468
+
(p7) ld8 r17=[r17] // get *pud (may be 0)
469
+
shr.u r18=r22,PMD_SHIFT // shift pmd index into position
479
470
;;
480
-
(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
481
-
dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
471
+
(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
472
+
dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
482
473
;;
483
474
#endif
484
-
(p7) ld8 r17=[r17] // fetch the L3 entry (may be 0)
485
-
shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
475
+
(p7) ld8 r17=[r17] // get *pmd (may be 0)
476
+
shr.u r19=r22,PAGE_SHIFT // shift pte index into position
486
477
;;
487
-
(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L3 entry NULL?
488
-
dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
478
+
(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
479
+
dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
489
480
(p6) br.cond.spnt page_fault
490
481
mov b0=r30
491
482
br.sptk.many b0 // return to continuation point