+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c

reviewed

··· 291 291 enum smu_clk_type clk_type, 292 292 char *buf) 293 293 { 294 294 - int ret = 0, size = 0; 294 294 + int ret = 0, size = 0, start_offset = 0; 295 295 uint32_t cur_value = 0; 296 296 int i; 297 297 298 298 smu_cmn_get_sysfs_buf(&buf, &size); 299 299 + start_offset = size; 299 300 300 301 switch (clk_type) { 301 302 case SMU_OD_SCLK: ··· 354 353 return ret; 355 354 } 356 355 357 357 - return size; 356 356 + return size - start_offset; 358 357 } 359 358 360 359 static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)

+8 -7

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

reviewed

··· 1469 1469 enum smu_clk_type clk_type, char *buf) 1470 1470 { 1471 1471 uint16_t *curve_settings; 1472 1472 - int i, levels, size = 0, ret = 0; 1472 1472 + int i, levels, size = 0, ret = 0, start_offset = 0; 1473 1473 uint32_t cur_value = 0, value = 0, count = 0; 1474 1474 uint32_t freq_values[3] = {0}; 1475 1475 uint32_t mark_index = 0; ··· 1484 1484 uint32_t min_value, max_value; 1485 1485 1486 1486 smu_cmn_get_sysfs_buf(&buf, &size); 1487 1487 + start_offset = size; 1487 1488 1488 1489 switch (clk_type) { 1489 1490 case SMU_GFXCLK: ··· 1498 1497 case SMU_DCEFCLK: 1499 1498 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); 1500 1499 if (ret) 1501 1501 - return size; 1500 1500 + return size - start_offset; 1502 1501 1503 1502 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); 1504 1503 if (ret) 1505 1505 - return size; 1504 1504 + return size - start_offset; 1506 1505 1507 1506 ret = navi10_is_support_fine_grained_dpm(smu, clk_type); 1508 1507 if (ret < 0) ··· 1512 1511 for (i = 0; i < count; i++) { 1513 1512 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); 1514 1513 if (ret) 1515 1515 - return size; 1514 1514 + return size - start_offset; 1516 1515 1517 1516 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 1518 1517 cur_value == value ? "*" : ""); ··· 1520 1519 } else { 1521 1520 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); 1522 1521 if (ret) 1523 1523 - return size; 1522 1522 + return size - start_offset; 1524 1523 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); 1525 1524 if (ret) 1526 1526 - return size; 1525 1525 + return size - start_offset; 1527 1526 1528 1527 freq_values[1] = cur_value; 1529 1528 mark_index = cur_value == freq_values[0] ? 0 : ··· 1654 1653 break; 1655 1654 } 1656 1655 1657 1657 - return size; 1656 1656 + return size - start_offset; 1658 1657 } 1659 1658 1660 1659 static int navi10_force_clk_levels(struct smu_context *smu,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

reviewed

··· 1281 1281 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; 1282 1282 OverDriveTable_t *od_table = 1283 1283 (OverDriveTable_t *)table_context->overdrive_table; 1284 1284 - int i, size = 0, ret = 0; 1284 1284 + int i, size = 0, ret = 0, start_offset = 0; 1285 1285 uint32_t cur_value = 0, value = 0, count = 0; 1286 1286 uint32_t freq_values[3] = {0}; 1287 1287 uint32_t mark_index = 0; ··· 1289 1289 uint32_t min_value, max_value; 1290 1290 1291 1291 smu_cmn_get_sysfs_buf(&buf, &size); 1292 1292 + start_offset = size; 1292 1293 1293 1294 switch (clk_type) { 1294 1295 case SMU_GFXCLK: ··· 1435 1434 } 1436 1435 1437 1436 print_clk_out: 1438 1438 - return size; 1437 1437 + return size - start_offset; 1439 1438 } 1440 1439 1441 1440 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,

+6 -4

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

reviewed

··· 565 565 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 566 566 SmuMetrics_legacy_t metrics; 567 567 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 568 568 - int i, idx, size = 0, ret = 0; 568 568 + int i, idx, size = 0, ret = 0, start_offset = 0; 569 569 uint32_t cur_value = 0, value = 0, count = 0; 570 570 bool cur_value_match_level = false; 571 571 ··· 576 576 return ret; 577 577 578 578 smu_cmn_get_sysfs_buf(&buf, &size); 579 579 + start_offset = size; 579 580 580 581 switch (clk_type) { 581 582 case SMU_OD_SCLK: ··· 659 658 break; 660 659 } 661 660 662 662 - return size; 661 661 + return size - start_offset; 663 662 } 664 663 665 664 static int vangogh_print_clk_levels(struct smu_context *smu, ··· 667 666 { 668 667 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 669 668 SmuMetrics_t metrics; 670 670 - int i, idx, size = 0, ret = 0; 669 669 + int i, idx, size = 0, ret = 0, start_offset = 0; 671 670 uint32_t cur_value = 0, value = 0, count = 0; 672 671 bool cur_value_match_level = false; 673 672 uint32_t min, max; ··· 679 678 return ret; 680 679 681 680 smu_cmn_get_sysfs_buf(&buf, &size); 681 681 + start_offset = size; 682 682 683 683 switch (clk_type) { 684 684 case SMU_OD_SCLK: ··· 781 779 break; 782 780 } 783 781 784 784 - return size; 782 782 + return size - start_offset; 785 783 } 786 784 787 785 static int vangogh_common_print_clk_levels(struct smu_context *smu,

+4 -3

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

reviewed

··· 494 494 static int renoir_print_clk_levels(struct smu_context *smu, 495 495 enum smu_clk_type clk_type, char *buf) 496 496 { 497 497 - int i, idx, size = 0, ret = 0; 497 497 + int i, idx, size = 0, ret = 0, start_offset = 0; 498 498 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; 499 499 SmuMetrics_t metrics; 500 500 bool cur_value_match_level = false; ··· 506 506 return ret; 507 507 508 508 smu_cmn_get_sysfs_buf(&buf, &size); 509 509 + start_offset = size; 509 510 510 511 switch (clk_type) { 511 512 case SMU_OD_RANGE: ··· 551 550 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 552 551 i == 2 ? "*" : ""); 553 552 } 554 554 - return size; 553 553 + return size - start_offset; 555 554 case SMU_SOCCLK: 556 555 count = NUM_SOCCLK_DPM_LEVELS; 557 556 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; ··· 608 607 break; 609 608 } 610 609 611 611 - return size; 610 610 + return size - start_offset; 612 611 } 613 612 614 613 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)

+4 -3

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

reviewed

··· 1195 1195 struct smu_13_0_dpm_table *single_dpm_table; 1196 1196 struct smu_13_0_pcie_table *pcie_table; 1197 1197 uint32_t gen_speed, lane_width; 1198 1198 - int i, curr_freq, size = 0; 1198 1198 + int i, curr_freq, size = 0, start_offset = 0; 1199 1199 int32_t min_value, max_value; 1200 1200 int ret = 0; 1201 1201 1202 1202 smu_cmn_get_sysfs_buf(&buf, &size); 1203 1203 + start_offset = size; 1203 1204 1204 1205 if (amdgpu_ras_intr_triggered()) { 1205 1206 size += sysfs_emit_at(buf, size, "unavailable\n"); 1206 1206 - return size; 1207 1207 + return size - start_offset; 1207 1208 } 1208 1209 1209 1210 switch (clk_type) { ··· 1535 1534 break; 1536 1535 } 1537 1536 1538 1538 - return size; 1537 1537 + return size - start_offset; 1539 1538 } 1540 1539 1541 1540

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c

reviewed

··· 497 497 static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, 498 498 enum smu_clk_type clk_type, char *buf) 499 499 { 500 500 - int i, idx, size = 0, ret = 0; 500 500 + int i, idx, size = 0, ret = 0, start_offset = 0; 501 501 uint32_t cur_value = 0, value = 0, count = 0; 502 502 uint32_t min, max; 503 503 504 504 smu_cmn_get_sysfs_buf(&buf, &size); 505 505 + start_offset = size; 505 506 506 507 switch (clk_type) { 507 508 case SMU_OD_SCLK: ··· 566 565 break; 567 566 } 568 567 569 569 - return size; 568 568 + return size - start_offset; 570 569 } 571 570 572 571 static int smu_v13_0_4_read_sensor(struct smu_context *smu,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c

reviewed

··· 861 861 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, 862 862 enum smu_clk_type clk_type, char *buf) 863 863 { 864 864 - int i, idx, size = 0, ret = 0; 864 864 + int i, idx, size = 0, ret = 0, start_offset = 0; 865 865 uint32_t cur_value = 0, value = 0, count = 0; 866 866 uint32_t min = 0, max = 0; 867 867 868 868 smu_cmn_get_sysfs_buf(&buf, &size); 869 869 + start_offset = size; 869 870 870 871 switch (clk_type) { 871 872 case SMU_OD_SCLK: ··· 929 928 } 930 929 931 930 print_clk_out: 932 932 - return size; 931 931 + return size - start_offset; 933 932 } 934 933 935 934

+4 -3

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

reviewed

··· 1428 1428 static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, 1429 1429 enum smu_clk_type type, char *buf) 1430 1430 { 1431 1431 - int now, size = 0; 1431 1431 + int now, size = 0, start_offset = 0; 1432 1432 int ret = 0; 1433 1433 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; 1434 1434 struct smu_13_0_dpm_table *single_dpm_table; ··· 1437 1437 uint32_t min_clk, max_clk; 1438 1438 1439 1439 smu_cmn_get_sysfs_buf(&buf, &size); 1440 1440 + start_offset = size; 1440 1441 1441 1442 if (amdgpu_ras_intr_triggered()) { 1442 1443 size += sysfs_emit_at(buf, size, "unavailable\n"); 1443 1443 - return size; 1444 1444 + return size - start_offset; 1444 1445 } 1445 1446 1446 1447 dpm_context = smu_dpm->dpm_context; ··· 1576 1575 break; 1577 1576 } 1578 1577 1579 1579 - return size; 1578 1578 + return size - start_offset; 1580 1579 } 1581 1580 1582 1581 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,

+4 -3

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c

reviewed

··· 1184 1184 struct smu_13_0_dpm_table *single_dpm_table; 1185 1185 struct smu_13_0_pcie_table *pcie_table; 1186 1186 uint32_t gen_speed, lane_width; 1187 1187 - int i, curr_freq, size = 0; 1187 1187 + int i, curr_freq, size = 0, start_offset = 0; 1188 1188 int32_t min_value, max_value; 1189 1189 int ret = 0; 1190 1190 1191 1191 smu_cmn_get_sysfs_buf(&buf, &size); 1192 1192 + start_offset = size; 1192 1193 1193 1194 if (amdgpu_ras_intr_triggered()) { 1194 1195 size += sysfs_emit_at(buf, size, "unavailable\n"); 1195 1195 - return size; 1196 1196 + return size - start_offset; 1196 1197 } 1197 1198 1198 1199 switch (clk_type) { ··· 1524 1523 break; 1525 1524 } 1526 1525 1527 1527 - return size; 1526 1526 + return size - start_offset; 1528 1527 } 1529 1528 1530 1529 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

reviewed

··· 1041 1041 static int yellow_carp_print_clk_levels(struct smu_context *smu, 1042 1042 enum smu_clk_type clk_type, char *buf) 1043 1043 { 1044 1044 - int i, idx, size = 0, ret = 0; 1044 1044 + int i, idx, size = 0, ret = 0, start_offset = 0; 1045 1045 uint32_t cur_value = 0, value = 0, count = 0; 1046 1046 uint32_t min, max; 1047 1047 uint32_t clk_limit = 0; 1048 1048 1049 1049 smu_cmn_get_sysfs_buf(&buf, &size); 1050 1050 + start_offset = size; 1050 1051 1051 1052 switch (clk_type) { 1052 1053 case SMU_OD_SCLK: ··· 1112 1111 } 1113 1112 1114 1113 print_clk_out: 1115 1115 - return size; 1114 1114 + return size - start_offset; 1116 1115 } 1117 1116 1118 1117 static int yellow_carp_force_clk_levels(struct smu_context *smu,

+3 -2

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

reviewed

··· 1132 1132 static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, 1133 1133 enum smu_clk_type clk_type, char *buf) 1134 1134 { 1135 1135 - int i, idx, ret = 0, size = 0; 1135 1135 + int i, idx, ret = 0, size = 0, start_offset = 0; 1136 1136 uint32_t cur_value = 0, value = 0, count = 0; 1137 1137 uint32_t min, max; 1138 1138 1139 1139 smu_cmn_get_sysfs_buf(&buf, &size); 1140 1140 + start_offset = size; 1140 1141 1141 1142 switch (clk_type) { 1142 1143 case SMU_OD_SCLK: ··· 1203 1202 break; 1204 1203 } 1205 1204 1206 1206 - return size; 1205 1205 + return size - start_offset; 1207 1206 } 1208 1207 1209 1208 static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu,

+4 -3

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

reviewed

··· 1056 1056 struct smu_14_0_dpm_table *single_dpm_table; 1057 1057 struct smu_14_0_pcie_table *pcie_table; 1058 1058 uint32_t gen_speed, lane_width; 1059 1059 - int i, curr_freq, size = 0; 1059 1059 + int i, curr_freq, size = 0, start_offset = 0; 1060 1060 int32_t min_value, max_value; 1061 1061 int ret = 0; 1062 1062 1063 1063 smu_cmn_get_sysfs_buf(&buf, &size); 1064 1064 + start_offset = size; 1064 1065 1065 1066 if (amdgpu_ras_intr_triggered()) { 1066 1067 size += sysfs_emit_at(buf, size, "unavailable\n"); 1067 1067 - return size; 1068 1068 + return size - start_offset; 1068 1069 } 1069 1070 1070 1071 switch (clk_type) { ··· 1375 1374 break; 1376 1375 } 1377 1376 1378 1378 - return size; 1377 1377 + return size - start_offset; 1379 1378 } 1380 1379 1381 1380 static int smu_v14_0_2_force_clk_levels(struct smu_context *smu,