tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC bug fixes from Arnd Bergmann:
"A little later during the week than the last few pull requests, since
there was very little that came in before 3.9-rc6. At least things
have calmed down again here.

Some important bug fixes that came in over the last 10 days, mostly
mvebu and imx:

- Multiple regressions on i.mx following the conversion of the clock
code, hopefully the last we are seeing of those.
- a regression in the mvebu irq handling code
- An incorrect register offset in the rewritten s3c24xx irq code.
- Two bugs in setting up the iomega_ix2_200 machine
- Turning on an extra bus clock on imx
- A MAINTAINERS file entry for Roland Stigge"

* tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm: mvebu: Fix the irq map function in SMP mode
Fix GE0/GE1 init on ix2-200 as GE0 has no PHY
ARM: S3C24XX: Fix interrupt pending register offset of the EINT controller
ARM: S3C24XX: Correct NR_IRQS definition for s3c2440
ARM i.MX6: Fix ldb_di clock selection
ARM: imx: provide twd clock lookup from device tree
ARM: imx35 Bugfix admux clock
ARM: clk-imx35: Bugfix iomux clock
ARM: mxs: Slow down the I2C clock speed
MAINTAINERS: Add maintainer for LPC32xx
ARM: Kirkwood: Fix typo in the definition of ix2-200 rebuild LED

Linus Torvalds ce6fbaf1 7ee32a6d

+30 -27
+6
MAINTAINERS
··· 4941 4941 S: Maintained 4942 4942 F: fs/logfs/ 4943 4943 4944 + LPC32XX MACHINE SUPPORT 4945 + M: Roland Stigge <stigge@antcom.de> 4946 + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 4947 + S: Maintained 4948 + F: arch/arm/mach-lpc32xx/ 4949 + 4944 4950 LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) 4945 4951 M: Nagalakshmi Nandigama <Nagalakshmi.Nandigama@lsi.com> 4946 4952 M: Sreekanth Reddy <Sreekanth.Reddy@lsi.com>
-1
arch/arm/boot/dts/imx28-m28evk.dts
··· 152 152 i2c0: i2c@80058000 { 153 153 pinctrl-names = "default"; 154 154 pinctrl-0 = <&i2c0_pins_a>; 155 - clock-frequency = <400000>; 156 155 status = "okay"; 157 156 158 157 sgtl5000: codec@0a {
-1
arch/arm/boot/dts/imx28-sps1.dts
··· 70 70 i2c0: i2c@80058000 { 71 71 pinctrl-names = "default"; 72 72 pinctrl-0 = <&i2c0_pins_a>; 73 - clock-frequency = <400000>; 74 73 status = "okay"; 75 74 76 75 rtc: rtc@51 {
+1
arch/arm/boot/dts/imx6qdl.dtsi
··· 91 91 compatible = "arm,cortex-a9-twd-timer"; 92 92 reg = <0x00a00600 0x20>; 93 93 interrupts = <1 13 0xf01>; 94 + clocks = <&clks 15>; 94 95 }; 95 96 96 97 L2: l2-cache@00a02000 {
+7 -7
arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
··· 96 96 marvell,function = "gpio"; 97 97 }; 98 98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { 99 - marvell,pins = "mpp44"; 99 + marvell,pins = "mpp46"; 100 100 marvell,function = "gpio"; 101 101 }; 102 102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { 103 - marvell,pins = "mpp45"; 103 + marvell,pins = "mpp47"; 104 104 marvell,function = "gpio"; 105 105 }; 106 106 ··· 157 157 gpios = <&gpio0 16 0>; 158 158 linux,default-trigger = "default-on"; 159 159 }; 160 - health_led1 { 160 + rebuild_led { 161 + label = "status:white:rebuild_led"; 162 + gpios = <&gpio1 4 0>; 163 + }; 164 + health_led { 161 165 label = "status:red:health_led"; 162 166 gpios = <&gpio1 5 0>; 163 - }; 164 - health_led2 { 165 - label = "status:white:health_led"; 166 - gpios = <&gpio1 4 0>; 167 167 }; 168 168 backup_led { 169 169 label = "status:blue:backup_led";
+2
arch/arm/mach-imx/clk-imx35.c
··· 257 257 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); 258 258 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); 259 259 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); 260 + clk_register_clkdev(clk[admux_gate], "audmux", NULL); 260 261 261 262 clk_prepare_enable(clk[spba_gate]); 262 263 clk_prepare_enable(clk[gpio1_gate]); ··· 266 265 clk_prepare_enable(clk[iim_gate]); 267 266 clk_prepare_enable(clk[emi_gate]); 268 267 clk_prepare_enable(clk[max_gate]); 268 + clk_prepare_enable(clk[iomuxc_gate]); 269 269 270 270 /* 271 271 * SCC is needed to boot via mmc after a watchdog reset. The clock code
+1 -2
arch/arm/mach-imx/clk-imx6q.c
··· 115 115 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 116 116 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", }; 117 117 static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 118 - static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_pfd1_540m", }; 118 + static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; 119 119 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 120 120 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 121 121 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; ··· 443 443 444 444 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 445 445 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 446 - clk_register_clkdev(clk[twd], NULL, "smp_twd"); 447 446 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 448 447 clk_register_clkdev(clk[ahb], "ahb", NULL); 449 448 clk_register_clkdev(clk[cko1], "cko1", NULL);
+6 -1
arch/arm/mach-kirkwood/board-iomega_ix2_200.c
··· 20 20 .duplex = DUPLEX_FULL, 21 21 }; 22 22 23 + static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = { 24 + .phy_addr = MV643XX_ETH_PHY_ADDR(11), 25 + }; 26 + 23 27 void __init iomega_ix2_200_init(void) 24 28 { 25 29 /* 26 30 * Basic setup. Needs to be called early. 27 31 */ 28 - kirkwood_ge01_init(&iomega_ix2_200_ge00_data); 32 + kirkwood_ge00_init(&iomega_ix2_200_ge00_data); 33 + kirkwood_ge01_init(&iomega_ix2_200_ge01_data); 29 34 }
+5 -11
arch/arm/mach-mvebu/irq-armada-370-xp.c
··· 61 61 */ 62 62 static void armada_370_xp_irq_mask(struct irq_data *d) 63 63 { 64 - #ifdef CONFIG_SMP 65 64 irq_hw_number_t hwirq = irqd_to_hwirq(d); 66 65 67 66 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) ··· 69 70 else 70 71 writel(hwirq, per_cpu_int_base + 71 72 ARMADA_370_XP_INT_SET_MASK_OFFS); 72 - #else 73 - writel(irqd_to_hwirq(d), 74 - per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); 75 - #endif 76 73 } 77 74 78 75 static void armada_370_xp_irq_unmask(struct irq_data *d) 79 76 { 80 - #ifdef CONFIG_SMP 81 77 irq_hw_number_t hwirq = irqd_to_hwirq(d); 82 78 83 79 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) ··· 81 87 else 82 88 writel(hwirq, per_cpu_int_base + 83 89 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 84 - #else 85 - writel(irqd_to_hwirq(d), 86 - per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 87 - #endif 88 90 } 89 91 90 92 #ifdef CONFIG_SMP ··· 136 146 unsigned int virq, irq_hw_number_t hw) 137 147 { 138 148 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 139 - writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 149 + if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 150 + writel(hw, per_cpu_int_base + 151 + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 152 + else 153 + writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 140 154 irq_set_status_flags(virq, IRQ_LEVEL); 141 155 142 156 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
+1 -3
arch/arm/mach-s3c24xx/include/mach/irqs.h
··· 188 188 189 189 #if defined(CONFIG_CPU_S3C2416) 190 190 #define NR_IRQS (IRQ_S3C2416_I2S1 + 1) 191 - #elif defined(CONFIG_CPU_S3C2443) 192 - #define NR_IRQS (IRQ_S3C2443_AC97+1) 193 191 #else 194 - #define NR_IRQS (IRQ_S3C2440_AC97+1) 192 + #define NR_IRQS (IRQ_S3C2443_AC97 + 1) 195 193 #endif 196 194 197 195 /* compatibility define. */
+1 -1
arch/arm/mach-s3c24xx/irq.c
··· 500 500 base = (void *)0xfd000000; 501 501 502 502 intc->reg_mask = base + 0xa4; 503 - intc->reg_pending = base + 0x08; 503 + intc->reg_pending = base + 0xa8; 504 504 irq_num = 20; 505 505 irq_start = S3C2410_IRQ(32); 506 506 irq_offset = 4;