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irqchip/gic-v3-its: Limit number of per-device MSIs to the range the ITS supports

The ITS driver blindly assumes that EventIDs are in abundant supply, to the
point where it never checks how many the hardware actually supports.

It turns out that some pretty esoteric integrations make it so that only a
few bits are available, all the way down to a single bit.

Enforce the advertised limitation at the point of allocating the device
structure, and hope that the endpoint driver can deal with such limitation.

Fixes: 84a6a2e7fc18d ("irqchip: GICv3: ITS: device allocation and configuration")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Zenghui Yu <zenghui.yu@linux.dev>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260206154816.3582887-1-maz@kernel.org

authored by

Marc Zyngier and committed by
Thomas Gleixner ce9e40a9 10720206

+5
+4
drivers/irqchip/irq-gic-v3-its.c
··· 3475 3475 int lpi_base; 3476 3476 int nr_lpis; 3477 3477 int nr_ites; 3478 + int id_bits; 3478 3479 int sz; 3479 3480 3480 3481 if (!its_alloc_device_table(its, dev_id)) ··· 3487 3486 /* 3488 3487 * Even if the device wants a single LPI, the ITT must be 3489 3488 * sized as a power of two (and you need at least one bit...). 3489 + * Also honor the ITS's own EID limit. 3490 3490 */ 3491 + id_bits = FIELD_GET(GITS_TYPER_IDBITS, its->typer) + 1; 3492 + nvecs = min_t(unsigned int, nvecs, BIT(id_bits)); 3491 3493 nr_ites = max(2, nvecs); 3492 3494 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); 3493 3495 sz = max(sz, ITS_ITT_ALIGN);
+1
include/linux/irqchip/arm-gic-v3.h
··· 394 394 #define GITS_TYPER_VLPIS (1UL << 1) 395 395 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 396 396 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) 397 + #define GITS_TYPER_IDBITS GENMASK_ULL(12, 8) 397 398 #define GITS_TYPER_IDBITS_SHIFT 8 398 399 #define GITS_TYPER_DEVBITS_SHIFT 13 399 400 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)