Merge tag 'drm-intel-gt-next-2025-03-12' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

+4 -1

drivers/gpu/drm/i915/gem/i915_gem_mman.c

··· 164 164 * 4 - Support multiple fault handlers per object depending on object's 165 165 * backing storage (a.k.a. MMAP_OFFSET). 166 166 * 167 + * 5 - Support multiple partial mmaps(mmap part of BO + unmap a offset, multiple 168 + * times with different size and offset). 169 + * 167 170 * Restrictions: 168 171 * 169 172 * * snoopable objects cannot be accessed via the GTT. It can cause machine ··· 194 191 */ 195 192 int i915_gem_mmap_gtt_version(void) 196 193 { 197 - return 4; 194 + return 5; 198 195 } 199 196 200 197 static inline struct i915_gtt_view

+26

drivers/gpu/drm/i915/gem/i915_gem_object.c

··· 873 873 return lmem_placement; 874 874 } 875 875 876 + static int i915_gem_vmap_object(struct drm_gem_object *gem_obj, 877 + struct iosys_map *map) 878 + { 879 + struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 880 + void *vaddr; 881 + 882 + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); 883 + if (IS_ERR(vaddr)) 884 + return PTR_ERR(vaddr); 885 + 886 + iosys_map_set_vaddr(map, vaddr); 887 + 888 + return 0; 889 + } 890 + 891 + static void i915_gem_vunmap_object(struct drm_gem_object *gem_obj, 892 + struct iosys_map *map) 893 + { 894 + struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 895 + 896 + i915_gem_object_flush_map(obj); 897 + i915_gem_object_unpin_map(obj); 898 + } 899 + 876 900 void i915_gem_init__objects(struct drm_i915_private *i915) 877 901 { 878 902 INIT_WORK(&i915->mm.free_work, __i915_gem_free_work); ··· 920 896 .free = i915_gem_free_object, 921 897 .close = i915_gem_close_object, 922 898 .export = i915_gem_prime_export, 899 + .vmap = i915_gem_vmap_object, 900 + .vunmap = i915_gem_vunmap_object, 923 901 }; 924 902 925 903 /**

+2 -3

drivers/gpu/drm/i915/gt/intel_engine_cs.c

··· 769 769 if (MEDIA_VER_FULL(i915) < IP_VER(12, 55)) 770 770 media_fuse = ~media_fuse; 771 771 772 - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; 773 - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> 774 - GEN11_GT_VEBOX_DISABLE_SHIFT; 772 + vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse); 773 + vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse); 775 774 776 775 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) { 777 776 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);

+38 -51

drivers/gpu/drm/i915/gt/intel_gt.c

··· 302 302 { 303 303 struct intel_engine_cs *engine; 304 304 enum intel_engine_id id; 305 - unsigned long fault; 306 305 307 306 for_each_engine(engine, gt, id) { 307 + u32 fault; 308 + 308 309 fault = GEN6_RING_FAULT_REG_READ(engine); 310 + 309 311 if (fault & RING_FAULT_VALID) { 310 312 gt_dbg(gt, "Unexpected fault\n" 311 - "\tAddr: 0x%08lx\n" 313 + "\tAddr: 0x%08x\n" 312 314 "\tAddress space: %s\n" 313 - "\tSource ID: %ld\n" 314 - "\tType: %ld\n", 315 - fault & PAGE_MASK, 315 + "\tSource ID: %d\n" 316 + "\tType: %d\n", 317 + fault & RING_FAULT_VADDR_MASK, 316 318 fault & RING_FAULT_GTTSEL_MASK ? 317 319 "GGTT" : "PPGTT", 318 - RING_FAULT_SRCID(fault), 319 - RING_FAULT_FAULT_TYPE(fault)); 320 + REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault), 321 + REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault)); 320 322 } 321 323 } 324 + } 325 + 326 + static void gen8_report_fault(struct intel_gt *gt, u32 fault, 327 + u32 fault_data0, u32 fault_data1) 328 + { 329 + u64 fault_addr; 330 + 331 + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 332 + ((u64)fault_data0 << 12); 333 + 334 + gt_dbg(gt, "Unexpected fault\n" 335 + "\tAddr: 0x%08x_%08x\n" 336 + "\tAddress space: %s\n" 337 + "\tEngine ID: %d\n" 338 + "\tSource ID: %d\n" 339 + "\tType: %d\n", 340 + upper_32_bits(fault_addr), lower_32_bits(fault_addr), 341 + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 342 + REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault), 343 + REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault), 344 + REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault)); 322 345 } 323 346 324 347 static void xehp_check_faults(struct intel_gt *gt) ··· 356 333 * toward the primary instance. 357 334 */ 358 335 fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG); 359 - if (fault & RING_FAULT_VALID) { 360 - u32 fault_data0, fault_data1; 361 - u64 fault_addr; 362 - 363 - fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0); 364 - fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1); 365 - 366 - fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 367 - ((u64)fault_data0 << 12); 368 - 369 - gt_dbg(gt, "Unexpected fault\n" 370 - "\tAddr: 0x%08x_%08x\n" 371 - "\tAddress space: %s\n" 372 - "\tEngine ID: %d\n" 373 - "\tSource ID: %d\n" 374 - "\tType: %d\n", 375 - upper_32_bits(fault_addr), lower_32_bits(fault_addr), 376 - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 377 - GEN8_RING_FAULT_ENGINE_ID(fault), 378 - RING_FAULT_SRCID(fault), 379 - RING_FAULT_FAULT_TYPE(fault)); 380 - } 336 + if (fault & RING_FAULT_VALID) 337 + gen8_report_fault(gt, fault, 338 + intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0), 339 + intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1)); 381 340 } 382 341 383 342 static void gen8_check_faults(struct intel_gt *gt) ··· 379 374 } 380 375 381 376 fault = intel_uncore_read(uncore, fault_reg); 382 - if (fault & RING_FAULT_VALID) { 383 - u32 fault_data0, fault_data1; 384 - u64 fault_addr; 385 - 386 - fault_data0 = intel_uncore_read(uncore, fault_data0_reg); 387 - fault_data1 = intel_uncore_read(uncore, fault_data1_reg); 388 - 389 - fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | 390 - ((u64)fault_data0 << 12); 391 - 392 - gt_dbg(gt, "Unexpected fault\n" 393 - "\tAddr: 0x%08x_%08x\n" 394 - "\tAddress space: %s\n" 395 - "\tEngine ID: %d\n" 396 - "\tSource ID: %d\n" 397 - "\tType: %d\n", 398 - upper_32_bits(fault_addr), lower_32_bits(fault_addr), 399 - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", 400 - GEN8_RING_FAULT_ENGINE_ID(fault), 401 - RING_FAULT_SRCID(fault), 402 - RING_FAULT_FAULT_TYPE(fault)); 403 - } 377 + if (fault & RING_FAULT_VALID) 378 + gen8_report_fault(gt, fault, 379 + intel_uncore_read(uncore, fault_data0_reg), 380 + intel_uncore_read(uncore, fault_data1_reg)); 404 381 } 405 382 406 383 void intel_gt_check_and_clear_faults(struct intel_gt *gt)

+3 -7

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

··· 35 35 u32 f24_mhz = 24000000; 36 36 u32 f25_mhz = 25000000; 37 37 u32 f38_4_mhz = 38400000; 38 - u32 crystal_clock = 39 - (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> 40 - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; 38 + u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK; 41 39 42 40 switch (crystal_clock) { 43 41 case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: ··· 78 80 * register increments from this frequency (it might 79 81 * increment only every few clock cycle). 80 82 */ 81 - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 82 - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); 83 + freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); 83 84 } 84 85 85 86 return freq; ··· 99 102 * register increments from this frequency (it might 100 103 * increment only every few clock cycle). 101 104 */ 102 - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> 103 - CTC_SHIFT_PARAMETER_SHIFT); 105 + freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg); 104 106 } 105 107 106 108 return freq;

+2 -3

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

··· 121 121 gt->info.mslice_mask = 122 122 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, 123 123 GEN_DSS_PER_MSLICE); 124 - gt->info.mslice_mask |= 125 - (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & 126 - GEN12_MEML3_EN_MASK); 124 + gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK, 125 + intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3)); 127 126 128 127 if (!gt->info.mslice_mask) /* should be impossible! */ 129 128 gt_warn(gt, "mslice mask all zero!\n");

+62 -74

drivers/gpu/drm/i915/gt/intel_gt_regs.h

··· 30 30 31 31 /* RPM unit config (Gen8+) */ 32 32 #define RPM_CONFIG0 _MMIO(0xd00) 33 - #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 34 - #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 35 - #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 36 - #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 37 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 38 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 39 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 40 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 41 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 42 - #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 43 - #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 44 - #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 33 + #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 34 + #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0) 35 + #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1) 36 + #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2) 37 + #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3) 38 + #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3) 39 + #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0) 40 + #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1) 41 + #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 45 42 46 43 #define RPM_CONFIG1 _MMIO(0xd04) 47 44 #define GEN10_GT_NOA_ENABLE (1 << 9) ··· 323 326 _RING_FAULT_REG_VCS, \ 324 327 _RING_FAULT_REG_VECS, \ 325 328 _RING_FAULT_REG_BCS)) 329 + #define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */ 330 + #define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */ 331 + #define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */ 332 + #define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3) 333 + #define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */ 334 + #define RING_FAULT_VALID REG_BIT(0) 326 335 327 336 #define ERROR_GEN6 _MMIO(0x40a0) 328 337 ··· 388 385 389 386 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 390 387 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 388 + #define FAULT_GTT_SEL REG_BIT(4) 389 + #define FAULT_VA_HIGH_BITS REG_GENMASK(3, 0) 391 390 392 391 #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80) 393 392 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) ··· 512 507 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 513 508 514 509 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 510 + #define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2) 511 + #define GEN9_PGCTL_SLICE_ACK REG_BIT(0) 512 + 515 513 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 516 514 ((slice) % 3) * 0x4) 517 - #define GEN9_PGCTL_SLICE_ACK (1 << 0) 518 - #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 519 - #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 515 + #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0)) 520 516 521 517 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 522 518 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ ··· 525 519 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 526 520 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 527 521 ((slice) % 3) * 0x8) 528 - #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 529 - #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 530 - #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 531 - #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 532 - #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 533 - #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 534 - #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 535 - #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 522 + #define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14) 523 + #define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12) 524 + #define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10) 525 + #define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8) 526 + #define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6) 527 + #define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4) 528 + #define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2) 529 + #define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0) 536 530 537 531 #define VF_PREEMPTION _MMIO(0x83a4) 538 532 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) ··· 589 583 #define GEN10_L3BANK_MASK 0x0F 590 584 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 591 585 #define GEN12_MAX_MSLICES 4 592 - #define GEN12_MEML3_EN_MASK 0x0F 586 + #define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0) 593 587 594 588 #define HSW_PAVP_FUSE1 _MMIO(0x911c) 595 589 #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24) ··· 599 593 #define HSW_F1_EU_DIS_6EUS 2 600 594 601 595 #define GEN8_FUSE2 _MMIO(0x9120) 602 - #define GEN8_F2_SS_DIS_SHIFT 21 603 - #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 604 - #define GEN8_F2_S_ENA_SHIFT 25 605 - #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 606 - #define GEN9_F2_SS_DIS_SHIFT 20 607 - #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 608 - #define GEN10_F2_S_ENA_SHIFT 22 609 - #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 610 - #define GEN10_F2_SS_DIS_SHIFT 18 611 - #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 596 + #define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22) 597 + #define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18) 598 + #define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25) 599 + #define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20) 600 + #define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21) 612 601 613 602 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 614 603 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 615 604 #define GEN11_EU_DISABLE _MMIO(0x9134) 616 - #define GEN8_EU_DIS0_S0_MASK 0xffffff 617 - #define GEN8_EU_DIS0_S1_SHIFT 24 618 - #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 619 - #define GEN11_EU_DIS_MASK 0xFF 605 + #define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24) 606 + #define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0) 607 + #define GEN11_EU_DIS_MASK REG_GENMASK(7, 0) 620 608 #define XEHP_EU_ENABLE _MMIO(0x9134) 621 - #define XEHP_EU_ENA_MASK 0xFF 609 + #define XEHP_EU_ENA_MASK REG_GENMASK(7, 0) 622 610 623 611 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 624 - #define GEN8_EU_DIS1_S1_MASK 0xffff 625 - #define GEN8_EU_DIS1_S2_SHIFT 16 626 - #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 612 + #define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16) 613 + #define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0) 627 614 628 615 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 629 - #define GEN11_GT_S_ENA_MASK 0xFF 616 + #define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0) 630 617 631 618 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 632 - #define GEN8_EU_DIS2_S2_MASK 0xff 619 + #define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0) 633 620 634 621 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c) 635 622 #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c) ··· 630 631 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 631 632 #define GEN10_EU_DIS_SS_MASK 0xff 632 633 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 633 - #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 634 - #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 635 - #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 634 + #define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 635 + #define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 636 636 637 637 #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) 638 638 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) ··· 879 881 880 882 /* GPM unit config (Gen9+) */ 881 883 #define CTC_MODE _MMIO(0xa26c) 882 - #define CTC_SOURCE_PARAMETER_MASK 1 883 - #define CTC_SOURCE_CRYSTAL_CLOCK 0 884 - #define CTC_SOURCE_DIVIDE_LOGIC 1 885 - #define CTC_SHIFT_PARAMETER_SHIFT 1 886 - #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 884 + #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 885 + #define CTC_SOURCE_PARAMETER_MASK REG_BIT(0) 886 + #define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0) 887 + #define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1) 887 888 888 889 /* GPM MSG_IDLE */ 889 890 #define MSG_IDLE_CS _MMIO(0x8000) ··· 926 929 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 927 930 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 928 931 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 929 - #define CHV_SS_PG_ENABLE (1 << 1) 930 - #define CHV_EU08_PG_ENABLE (1 << 9) 931 - #define CHV_EU19_PG_ENABLE (1 << 17) 932 - #define CHV_EU210_PG_ENABLE (1 << 25) 932 + #define CHV_EU210_PG_ENABLE REG_BIT(25) 933 + #define CHV_EU19_PG_ENABLE REG_BIT(17) 934 + #define CHV_EU08_PG_ENABLE REG_BIT(9) 935 + #define CHV_SS_PG_ENABLE REG_BIT(1) 933 936 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 934 - #define CHV_EU311_PG_ENABLE (1 << 1) 937 + #define CHV_EU311_PG_ENABLE REG_BIT(1) 935 938 936 939 #define GEN7_SARCHKMD _MMIO(0xb000) 937 940 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) ··· 1035 1038 #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8) 1036 1039 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) 1037 1040 #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc) 1038 - #define FAULT_VA_HIGH_BITS (0xf << 0) 1039 - #define FAULT_GTT_SEL (1 << 4) 1041 + /* see GEN8_FAULT_TLB_DATA0/1 */ 1040 1042 1041 1043 #define GEN12_RING_FAULT_REG _MMIO(0xcec4) 1042 1044 #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) 1043 1045 #define XELPMP_RING_FAULT_REG _MMIO(0xcec4) 1044 - #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 1045 - #define RING_FAULT_GTTSEL_MASK (1 << 11) 1046 - #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 1047 - #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 1048 - #define RING_FAULT_VALID (1 << 0) 1046 + /* see GEN8_RING_FAULT_REG */ 1049 1047 1050 1048 #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) 1051 1049 #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8) ··· 1429 1437 #define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) 1430 1438 1431 1439 #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) 1432 - #define CHV_FGT_DISABLE_SS0 (1 << 10) 1433 - #define CHV_FGT_DISABLE_SS1 (1 << 11) 1434 - #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 1435 - #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 1436 - #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 1437 - #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 1438 - #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 1439 - #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 1440 - #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 1441 - #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 1440 + #define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28) 1441 + #define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24) 1442 + #define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20) 1443 + #define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16) 1444 + #define CHV_FGT_DISABLE_SS1 REG_BIT(11) 1445 + #define CHV_FGT_DISABLE_SS0 REG_BIT(10) 1442 1446 1443 1447 #define BCS_SWCTRL _MMIO(0x22200) 1444 1448 #define BCS_SRC_Y REG_BIT(0)

+26 -30

drivers/gpu/drm/i915/gt/intel_sseu.c

··· 236 236 GEN12_GT_COMPUTE_DSS_ENABLE, 237 237 XEHPC_GT_COMPUTE_DSS_ENABLE_EXT); 238 238 239 - eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; 239 + eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK, 240 + intel_uncore_read(uncore, XEHP_EU_ENABLE)); 240 241 241 242 if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915)) 242 243 eu_en = eu_en_fuse; ··· 270 269 * Although gen12 architecture supported multiple slices, TGL, RKL, 271 270 * DG1, and ADL only had a single slice. 272 271 */ 273 - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 274 - GEN11_GT_S_ENA_MASK; 272 + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, 273 + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); 275 274 drm_WARN_ON(&gt->i915->drm, s_en != 0x1); 276 275 277 276 g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE); 278 277 279 278 /* one bit per pair of EUs */ 280 - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 281 - GEN11_EU_DIS_MASK); 279 + eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, 280 + intel_uncore_read(uncore, GEN11_EU_DISABLE)); 282 281 283 282 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 284 283 if (eu_en_fuse & BIT(eu)) ··· 307 306 * Although gen11 architecture supported multiple slices, ICL and 308 307 * EHL/JSL only had a single slice in practice. 309 308 */ 310 - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 311 - GEN11_GT_S_ENA_MASK; 309 + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, 310 + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); 312 311 drm_WARN_ON(&gt->i915->drm, s_en != 0x1); 313 312 314 313 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); 315 314 316 - eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 317 - GEN11_EU_DIS_MASK); 315 + eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, 316 + intel_uncore_read(uncore, GEN11_EU_DISABLE)); 318 317 319 318 gen11_compute_sseu_info(sseu, ss_en, eu_en); 320 319 ··· 336 335 337 336 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 338 337 u8 disabled_mask = 339 - ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 340 - CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 341 - (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 342 - CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 338 + REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) | 339 + REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK); 343 340 344 341 sseu->subslice_mask.hsw[0] |= BIT(0); 345 342 sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF); ··· 345 346 346 347 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 347 348 u8 disabled_mask = 348 - ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 349 - CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 350 - (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 351 - CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 349 + REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) | 350 + REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK); 352 351 353 352 sseu->subslice_mask.hsw[0] |= BIT(1); 354 353 sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF); ··· 382 385 int s, ss; 383 386 384 387 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 385 - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 388 + sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); 386 389 387 390 /* BXT has a single slice and at most 3 subslices. */ 388 391 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, ··· 393 396 * to each of the enabled slices. 394 397 */ 395 398 subslice_mask = (1 << sseu->max_subslices) - 1; 396 - subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 397 - GEN9_F2_SS_DIS_SHIFT); 399 + subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2); 398 400 399 401 /* 400 402 * Iterate through enabled slices and subslices to ··· 486 490 u32 eu_disable0, eu_disable1, eu_disable2; 487 491 488 492 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 489 - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 493 + sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); 490 494 intel_sseu_set_info(sseu, 3, 3, 8); 491 495 492 496 /* ··· 494 498 * to each of the enabled slices. 495 499 */ 496 500 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 497 - subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 498 - GEN8_F2_SS_DIS_SHIFT); 501 + subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2); 499 502 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); 500 503 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); 501 504 eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); 502 - eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; 503 - eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | 504 - ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << 505 - (32 - GEN8_EU_DIS0_S1_SHIFT)); 506 - eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | 507 - ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << 508 - (32 - GEN8_EU_DIS1_S2_SHIFT)); 505 + eu_disable[0] = 506 + REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0); 507 + eu_disable[1] = 508 + REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) | 509 + REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK); 510 + eu_disable[2] = 511 + REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) | 512 + REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK); 509 513 510 514 /* 511 515 * Iterate through enabled slices and subslices to

+2 -5

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

··· 1285 1285 static u32 gpm_timestamp_shift(struct intel_gt *gt) 1286 1286 { 1287 1287 intel_wakeref_t wakeref; 1288 - u32 reg, shift; 1288 + u32 reg; 1289 1289 1290 1290 with_intel_runtime_pm(gt->uncore->rpm, wakeref) 1291 1291 reg = intel_uncore_read(gt->uncore, RPM_CONFIG0); 1292 1292 1293 - shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> 1294 - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT; 1295 - 1296 - return 3 - shift; 1293 + return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg); 1297 1294 } 1298 1295 1299 1296 static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)

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