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dt-bindings: iio: adc: sophgo,cv1800b-saradc: Add Sophgo CV1800B SARADC

The Sophgo CV1800B SARADC is a Successive Approximation ADC that can be
found in the Sophgo CV1800B SoC.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20240829-sg2002-adc-v5-1-aacb381e869b@bootlin.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Thomas Bonnefille and committed by
Jonathan Cameron cf082dbe 3c6b818b

+83
+83
Documentation/devicetree/bindings/iio/adc/sophgo,cv1800b-saradc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/iio/adc/sophgo,cv1800b-saradc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: 8 + Sophgo CV1800B SoC 3 channels Successive Approximation Analog to 9 + Digital Converters 10 + 11 + maintainers: 12 + - Thomas Bonnefille <thomas.bonnefille@bootlin.com> 13 + 14 + description: 15 + Datasheet at https://github.com/sophgo/sophgo-doc/releases 16 + 17 + properties: 18 + compatible: 19 + const: sophgo,cv1800b-saradc 20 + 21 + reg: 22 + maxItems: 1 23 + 24 + interrupts: 25 + maxItems: 1 26 + 27 + clocks: 28 + maxItems: 1 29 + 30 + '#address-cells': 31 + const: 1 32 + 33 + '#size-cells': 34 + const: 0 35 + 36 + patternProperties: 37 + "^channel@[0-2]$": 38 + $ref: adc.yaml 39 + 40 + properties: 41 + reg: 42 + items: 43 + - minimum: 0 44 + maximum: 2 45 + 46 + required: 47 + - reg 48 + 49 + additionalProperties: false 50 + 51 + required: 52 + - compatible 53 + - reg 54 + - clocks 55 + - '#address-cells' 56 + - '#size-cells' 57 + 58 + additionalProperties: false 59 + 60 + examples: 61 + - | 62 + #include <dt-bindings/clock/sophgo,cv1800.h> 63 + #include <dt-bindings/interrupt-controller/irq.h> 64 + adc@30f0000 { 65 + compatible = "sophgo,cv1800b-saradc"; 66 + reg = <0x030f0000 0x1000>; 67 + clocks = <&clk CLK_SARADC>; 68 + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; 69 + #address-cells = <1>; 70 + #size-cells = <0>; 71 + 72 + channel@0 { 73 + reg = <0>; 74 + }; 75 + 76 + channel@1 { 77 + reg = <1>; 78 + }; 79 + 80 + channel@2 { 81 + reg = <2>; 82 + }; 83 + };