tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
"A bunch of pin control fixes, some a bit overly ripe, sorry about
that. We have important systems like Intel laptops and Qualcomm mobile
chips covered.

- Pad lock register on Intel Sunrisepoint had the wrong offset

- Fix pin config setting for the Baytrail GPIO chip

- Fix a compilation warning in the Mediatek driver

- Fix a function group name in the Actions driver

- Fix a behaviour bug in the edge polarity code in the Qualcomm
driver

- Add a missing spinlock in the Intel Cherryview driver

- Add affinity callbacks to the Qualcomm MSMGPIO chip"

* tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip
pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler
pinctrl: qcom: fix wrong write in update_dual_edge
pinctrl: actions: fix function group name for i2c0_group
pinctrl: mediatek: remove shadow variable declaration
pinctrl: baytrail: Enable pin configuration setting for GPIO chip
pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H

Linus Torvalds cf0ca701 18e70f3a

+40 -11
+1 -1
drivers/pinctrl/actions/pinctrl-s700.c
··· 1435 1435 static const char * const i2c0_groups[] = { 1436 1436 "uart0_rx_mfp", 1437 1437 "uart0_tx_mfp", 1438 - "i2c0_mfp_mfp", 1438 + "i2c0_mfp", 1439 1439 }; 1440 1440 1441 1441 static const char * const i2c1_groups[] = {
+1
drivers/pinctrl/intel/pinctrl-baytrail.c
··· 1286 1286 .direction_output = byt_gpio_direction_output, 1287 1287 .get = byt_gpio_get, 1288 1288 .set = byt_gpio_set, 1289 + .set_config = gpiochip_generic_config, 1289 1290 .dbg_show = byt_gpio_dbg_show, 1290 1291 }; 1291 1292
+4
drivers/pinctrl/intel/pinctrl-cherryview.c
··· 1479 1479 struct chv_pinctrl *pctrl = gpiochip_get_data(gc); 1480 1480 struct irq_chip *chip = irq_desc_get_chip(desc); 1481 1481 unsigned long pending; 1482 + unsigned long flags; 1482 1483 u32 intr_line; 1483 1484 1484 1485 chained_irq_enter(chip, desc); 1485 1486 1487 + raw_spin_lock_irqsave(&chv_lock, flags); 1486 1488 pending = readl(pctrl->regs + CHV_INTSTAT); 1489 + raw_spin_unlock_irqrestore(&chv_lock, flags); 1490 + 1487 1491 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { 1488 1492 unsigned int irq, offset; 1489 1493
+8 -7
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
··· 15 15 16 16 #include "pinctrl-intel.h" 17 17 18 - #define SPT_PAD_OWN 0x020 19 - #define SPT_PADCFGLOCK 0x0a0 20 - #define SPT_HOSTSW_OWN 0x0d0 21 - #define SPT_GPI_IS 0x100 22 - #define SPT_GPI_IE 0x120 18 + #define SPT_PAD_OWN 0x020 19 + #define SPT_H_PADCFGLOCK 0x090 20 + #define SPT_LP_PADCFGLOCK 0x0a0 21 + #define SPT_HOSTSW_OWN 0x0d0 22 + #define SPT_GPI_IS 0x100 23 + #define SPT_GPI_IE 0x120 23 24 24 25 #define SPT_COMMUNITY(b, s, e) \ 25 26 { \ 26 27 .barno = (b), \ 27 28 .padown_offset = SPT_PAD_OWN, \ 28 - .padcfglock_offset = SPT_PADCFGLOCK, \ 29 + .padcfglock_offset = SPT_LP_PADCFGLOCK, \ 29 30 .hostown_offset = SPT_HOSTSW_OWN, \ 30 31 .is_offset = SPT_GPI_IS, \ 31 32 .ie_offset = SPT_GPI_IE, \ ··· 48 47 { \ 49 48 .barno = (b), \ 50 49 .padown_offset = SPT_PAD_OWN, \ 51 - .padcfglock_offset = SPT_PADCFGLOCK, \ 50 + .padcfglock_offset = SPT_H_PADCFGLOCK, \ 52 51 .hostown_offset = SPT_HOSTSW_OWN, \ 53 52 .is_offset = SPT_GPI_IS, \ 54 53 .ie_offset = SPT_GPI_IE, \
-2
drivers/pinctrl/mediatek/pinctrl-paris.c
··· 164 164 case MTK_PIN_CONFIG_PU_ADV: 165 165 case MTK_PIN_CONFIG_PD_ADV: 166 166 if (hw->soc->adv_pull_get) { 167 - bool pullup; 168 - 169 167 pullup = param == MTK_PIN_CONFIG_PU_ADV; 170 168 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); 171 169 } else
+26 -1
drivers/pinctrl/qcom/pinctrl-msm.c
··· 697 697 698 698 pol = msm_readl_intr_cfg(pctrl, g); 699 699 pol ^= BIT(g->intr_polarity_bit); 700 - msm_writel_intr_cfg(val, pctrl, g); 700 + msm_writel_intr_cfg(pol, pctrl, g); 701 701 702 702 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); 703 703 intstat = msm_readl_intr_status(pctrl, g); ··· 1034 1034 module_put(gc->owner); 1035 1035 } 1036 1036 1037 + static int msm_gpio_irq_set_affinity(struct irq_data *d, 1038 + const struct cpumask *dest, bool force) 1039 + { 1040 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1041 + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1042 + 1043 + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 1044 + return irq_chip_set_affinity_parent(d, dest, force); 1045 + 1046 + return 0; 1047 + } 1048 + 1049 + static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) 1050 + { 1051 + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1052 + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1053 + 1054 + if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 1055 + return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); 1056 + 1057 + return 0; 1058 + } 1059 + 1037 1060 static void msm_gpio_irq_handler(struct irq_desc *desc) 1038 1061 { 1039 1062 struct gpio_chip *gc = irq_desc_get_handler_data(desc); ··· 1155 1132 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; 1156 1133 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; 1157 1134 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; 1135 + pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; 1136 + pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; 1158 1137 1159 1138 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); 1160 1139 if (np) {