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drm/msm/a6xx: Add missing BIT(7) to REG_A6XX_UCHE_CLIENT_PF

Downstream always set BIT(7)

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/568930/

authored by

Danylo Piliaiev and committed by
Rob Clark
cf1aaa7d 6c15808d

+1 -1
+1 -1
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 1782 1782 else 1783 1783 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1784 1784 1785 - gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 1785 + gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1); 1786 1786 1787 1787 /* Set weights for bicubic filtering */ 1788 1788 if (adreno_is_a650_family(adreno_gpu)) {