tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/display: Ensure phy is accessible on lfps configuration

Ensure phy is accessible on lfps configuration by adding
intel_cx0_phy_transaction_begin/end around it.

Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Suggested-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20250722125618.1842615-4-jouni.hogander@intel.com

Jouni Högander cf433f94 d487ed7e

+6
+6
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 3239 3239 const struct intel_crtc_state *crtc_state) 3240 3240 { 3241 3241 struct intel_display *display = to_intel_display(encoder); 3242 + intel_wakeref_t wakeref; 3242 3243 int i; 3243 3244 u8 owned_lane_mask; 3244 3245 ··· 3248 3247 return; 3249 3248 3250 3249 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 3250 + 3251 + wakeref = intel_cx0_phy_transaction_begin(encoder); 3252 + 3251 3253 for (i = 0; i < 4; i++) { 3252 3254 int tx = i % 2 + 1; 3253 3255 u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; ··· 3262 3258 CONTROL0_MAC_TRANSMIT_LFPS, 3263 3259 CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED); 3264 3260 } 3261 + 3262 + intel_cx0_phy_transaction_end(encoder, wakeref); 3265 3263 } 3266 3264 3267 3265 static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)