Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Radeon has two displayport fixes, one for a regression.
i915 regression flicker fix needed so 4.0 can get fixed.
A bunch of msm fixes and a bunch of exynos fixes, these two are
probably a bit larger than I'd like, but most of them seems pretty
good"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (29 commits)
drm/radeon: fix error flag checking in native aux path
drm/radeon: retry dcpd fetch
drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()
drm/exynos: dp: Lower level of EDID read success message
drm/exynos: cleanup exynos_drm_plane
drm/exynos: 'win' is always unsigned
drm/exynos: mixer: don't dump registers under spinlock
drm/exynos: Consolidate return statements in fimd_bind()
drm/exynos: Constify exynos_drm_crtc_ops
drm/exynos: Fix build breakage on !DRM_EXYNOS_FIMD
drm/exynos: mixer: Constify platform_device_id
drm/exynos: mixer: cleanup pixelformat handling
drm/exynos: mixer: also allow NV21 for the video processor
drm/exynos: mixer: remove buffer count handling in vp_video_buffer()
drm/exynos: plane: honor buffer offset for dma_addr
drm/exynos: fb: use drm_format_num_planes to get buffer count
drm/i915: fix screen flickering
drm/msm: fix locking inconsistencies in gpu->destroy()
drm/msm/dsi: Simplify the code to get the number of read byte
drm/msm: Attach assigned encoder to eDP and DSI connectors
...
+190
-240
+2
-2
drivers/gpu/drm/exynos/exynos7_drm_decon.c
+2
-2
drivers/gpu/drm/exynos/exynos7_drm_decon.c
···
91
91
92
92
static void decon_clear_channel(struct decon_context *ctx)
93
93
{
94
-
int win, ch_enabled = 0;
94
+
unsigned int win, ch_enabled = 0;
95
95
96
96
DRM_DEBUG_KMS("%s\n", __FILE__);
97
97
···
710
710
}
711
711
}
712
712
713
-
static struct exynos_drm_crtc_ops decon_crtc_ops = {
713
+
static const struct exynos_drm_crtc_ops decon_crtc_ops = {
714
714
.dpms = decon_dpms,
715
715
.mode_fixup = decon_mode_fixup,
716
716
.commit = decon_commit,
+9
-4
drivers/gpu/drm/exynos/exynos_dp_core.c
+9
-4
drivers/gpu/drm/exynos/exynos_dp_core.c
···
32
32
#include <drm/bridge/ptn3460.h>
33
33
34
34
#include "exynos_dp_core.h"
35
-
#include "exynos_drm_fimd.h"
36
35
37
36
#define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
38
37
connector)
···
195
196
}
196
197
}
197
198
198
-
dev_err(dp->dev, "EDID Read success!\n");
199
+
dev_dbg(dp->dev, "EDID Read success!\n");
199
200
return 0;
200
201
}
201
202
···
1065
1066
1066
1067
static void exynos_dp_poweron(struct exynos_dp_device *dp)
1067
1068
{
1069
+
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1070
+
1068
1071
if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1069
1072
return;
1070
1073
···
1077
1076
}
1078
1077
}
1079
1078
1080
-
fimd_dp_clock_enable(dp_to_crtc(dp), true);
1079
+
if (crtc->ops->clock_enable)
1080
+
crtc->ops->clock_enable(dp_to_crtc(dp), true);
1081
1081
1082
1082
clk_prepare_enable(dp->clock);
1083
1083
exynos_dp_phy_init(dp);
···
1089
1087
1090
1088
static void exynos_dp_poweroff(struct exynos_dp_device *dp)
1091
1089
{
1090
+
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
1091
+
1092
1092
if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1093
1093
return;
1094
1094
···
1106
1102
exynos_dp_phy_exit(dp);
1107
1103
clk_disable_unprepare(dp->clock);
1108
1104
1109
-
fimd_dp_clock_enable(dp_to_crtc(dp), false);
1105
+
if (crtc->ops->clock_enable)
1106
+
crtc->ops->clock_enable(dp_to_crtc(dp), false);
1110
1107
1111
1108
if (dp->panel) {
1112
1109
if (drm_panel_unprepare(dp->panel))
+5
-5
drivers/gpu/drm/exynos/exynos_drm_crtc.c
+5
-5
drivers/gpu/drm/exynos/exynos_drm_crtc.c
···
238
238
};
239
239
240
240
struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
241
-
struct drm_plane *plane,
242
-
int pipe,
243
-
enum exynos_drm_output_type type,
244
-
struct exynos_drm_crtc_ops *ops,
245
-
void *ctx)
241
+
struct drm_plane *plane,
242
+
int pipe,
243
+
enum exynos_drm_output_type type,
244
+
const struct exynos_drm_crtc_ops *ops,
245
+
void *ctx)
246
246
{
247
247
struct exynos_drm_crtc *exynos_crtc;
248
248
struct exynos_drm_private *private = drm_dev->dev_private;
+5
-5
drivers/gpu/drm/exynos/exynos_drm_crtc.h
+5
-5
drivers/gpu/drm/exynos/exynos_drm_crtc.h
···
18
18
#include "exynos_drm_drv.h"
19
19
20
20
struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev,
21
-
struct drm_plane *plane,
22
-
int pipe,
23
-
enum exynos_drm_output_type type,
24
-
struct exynos_drm_crtc_ops *ops,
25
-
void *context);
21
+
struct drm_plane *plane,
22
+
int pipe,
23
+
enum exynos_drm_output_type type,
24
+
const struct exynos_drm_crtc_ops *ops,
25
+
void *context);
26
26
int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe);
27
27
void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe);
28
28
void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int pipe);
+6
-14
drivers/gpu/drm/exynos/exynos_drm_drv.h
+6
-14
drivers/gpu/drm/exynos/exynos_drm_drv.h
···
71
71
* @dma_addr: array of bus(accessed by dma) address to the memory region
72
72
* allocated for a overlay.
73
73
* @zpos: order of overlay layer(z position).
74
-
* @index_color: if using color key feature then this value would be used
75
-
* as index color.
76
-
* @default_win: a window to be enabled.
77
-
* @color_key: color key on or off.
78
-
* @local_path: in case of lcd type, local path mode on or off.
79
-
* @transparency: transparency on or off.
80
-
* @activated: activated or not.
81
74
* @enabled: enabled or not.
82
75
* @resume: to resume or not.
83
76
*
···
101
108
uint32_t pixel_format;
102
109
dma_addr_t dma_addr[MAX_FB_BUFFER];
103
110
unsigned int zpos;
104
-
unsigned int index_color;
105
111
106
-
bool default_win:1;
107
-
bool color_key:1;
108
-
bool local_path:1;
109
-
bool transparency:1;
110
-
bool activated:1;
111
112
bool enabled:1;
112
113
bool resume:1;
113
114
};
···
168
181
* @win_disable: disable hardware specific overlay.
169
182
* @te_handler: trigger to transfer video image at the tearing effect
170
183
* synchronization signal if there is a page flip request.
184
+
* @clock_enable: optional function enabling/disabling display domain clock,
185
+
* called from exynos-dp driver before powering up (with
186
+
* 'enable' argument as true) and after powering down (with
187
+
* 'enable' as false).
171
188
*/
172
189
struct exynos_drm_crtc;
173
190
struct exynos_drm_crtc_ops {
···
186
195
void (*win_commit)(struct exynos_drm_crtc *crtc, unsigned int zpos);
187
196
void (*win_disable)(struct exynos_drm_crtc *crtc, unsigned int zpos);
188
197
void (*te_handler)(struct exynos_drm_crtc *crtc);
198
+
void (*clock_enable)(struct exynos_drm_crtc *crtc, bool enable);
189
199
};
190
200
191
201
/*
···
213
221
unsigned int dpms;
214
222
wait_queue_head_t pending_flip_queue;
215
223
struct drm_pending_vblank_event *event;
216
-
struct exynos_drm_crtc_ops *ops;
224
+
const struct exynos_drm_crtc_ops *ops;
217
225
void *ctx;
218
226
};
219
227
+1
-38
drivers/gpu/drm/exynos/exynos_drm_fb.c
+1
-38
drivers/gpu/drm/exynos/exynos_drm_fb.c
···
171
171
return &exynos_fb->fb;
172
172
}
173
173
174
-
static u32 exynos_drm_format_num_buffers(struct drm_mode_fb_cmd2 *mode_cmd)
175
-
{
176
-
unsigned int cnt = 0;
177
-
178
-
if (mode_cmd->pixel_format != DRM_FORMAT_NV12)
179
-
return drm_format_num_planes(mode_cmd->pixel_format);
180
-
181
-
while (cnt != MAX_FB_BUFFER) {
182
-
if (!mode_cmd->handles[cnt])
183
-
break;
184
-
cnt++;
185
-
}
186
-
187
-
/*
188
-
* check if NV12 or NV12M.
189
-
*
190
-
* NV12
191
-
* handles[0] = base1, offsets[0] = 0
192
-
* handles[1] = base1, offsets[1] = Y_size
193
-
*
194
-
* NV12M
195
-
* handles[0] = base1, offsets[0] = 0
196
-
* handles[1] = base2, offsets[1] = 0
197
-
*/
198
-
if (cnt == 2) {
199
-
/*
200
-
* in case of NV12 format, offsets[1] is not 0 and
201
-
* handles[0] is same as handles[1].
202
-
*/
203
-
if (mode_cmd->offsets[1] &&
204
-
mode_cmd->handles[0] == mode_cmd->handles[1])
205
-
cnt = 1;
206
-
}
207
-
208
-
return cnt;
209
-
}
210
-
211
174
static struct drm_framebuffer *
212
175
exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
213
176
struct drm_mode_fb_cmd2 *mode_cmd)
···
193
230
194
231
drm_helper_mode_fill_fb_struct(&exynos_fb->fb, mode_cmd);
195
232
exynos_fb->exynos_gem_obj[0] = to_exynos_gem_obj(obj);
196
-
exynos_fb->buf_cnt = exynos_drm_format_num_buffers(mode_cmd);
233
+
exynos_fb->buf_cnt = drm_format_num_planes(mode_cmd->pixel_format);
197
234
198
235
DRM_DEBUG_KMS("buf_cnt = %d\n", exynos_fb->buf_cnt);
199
236
+24
-29
drivers/gpu/drm/exynos/exynos_drm_fimd.c
+24
-29
drivers/gpu/drm/exynos/exynos_drm_fimd.c
···
33
33
#include "exynos_drm_crtc.h"
34
34
#include "exynos_drm_plane.h"
35
35
#include "exynos_drm_iommu.h"
36
-
#include "exynos_drm_fimd.h"
37
36
38
37
/*
39
38
* FIMD stands for Fully Interactive Mobile Display and
···
215
216
DRM_DEBUG_KMS("vblank wait timed out.\n");
216
217
}
217
218
218
-
static void fimd_enable_video_output(struct fimd_context *ctx, int win,
219
+
static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
219
220
bool enable)
220
221
{
221
222
u32 val = readl(ctx->regs + WINCON(win));
···
228
229
writel(val, ctx->regs + WINCON(win));
229
230
}
230
231
231
-
static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
232
+
static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
233
+
unsigned int win,
232
234
bool enable)
233
235
{
234
236
u32 val = readl(ctx->regs + SHADOWCON);
···
244
244
245
245
static void fimd_clear_channel(struct fimd_context *ctx)
246
246
{
247
-
int win, ch_enabled = 0;
247
+
unsigned int win, ch_enabled = 0;
248
248
249
249
DRM_DEBUG_KMS("%s\n", __FILE__);
250
250
···
946
946
drm_handle_vblank(ctx->drm_dev, ctx->pipe);
947
947
}
948
948
949
-
static struct exynos_drm_crtc_ops fimd_crtc_ops = {
949
+
static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
950
+
{
951
+
struct fimd_context *ctx = crtc->ctx;
952
+
u32 val;
953
+
954
+
/*
955
+
* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
956
+
* clock. On these SoCs the bootloader may enable it but any
957
+
* power domain off/on will reset it to disable state.
958
+
*/
959
+
if (ctx->driver_data != &exynos5_fimd_driver_data)
960
+
return;
961
+
962
+
val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
963
+
writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
964
+
}
965
+
966
+
static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
950
967
.dpms = fimd_dpms,
951
968
.mode_fixup = fimd_mode_fixup,
952
969
.commit = fimd_commit,
···
973
956
.win_commit = fimd_win_commit,
974
957
.win_disable = fimd_win_disable,
975
958
.te_handler = fimd_te_handler,
959
+
.clock_enable = fimd_dp_clock_enable,
976
960
};
977
961
978
962
static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
···
1043
1025
if (ctx->display)
1044
1026
exynos_drm_create_enc_conn(drm_dev, ctx->display);
1045
1027
1046
-
ret = fimd_iommu_attach_devices(ctx, drm_dev);
1047
-
if (ret)
1048
-
return ret;
1049
-
1050
-
return 0;
1051
-
1028
+
return fimd_iommu_attach_devices(ctx, drm_dev);
1052
1029
}
1053
1030
1054
1031
static void fimd_unbind(struct device *dev, struct device *master,
···
1204
1191
1205
1192
return 0;
1206
1193
}
1207
-
1208
-
void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
1209
-
{
1210
-
struct fimd_context *ctx = crtc->ctx;
1211
-
u32 val;
1212
-
1213
-
/*
1214
-
* Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
1215
-
* clock. On these SoCs the bootloader may enable it but any
1216
-
* power domain off/on will reset it to disable state.
1217
-
*/
1218
-
if (ctx->driver_data != &exynos5_fimd_driver_data)
1219
-
return;
1220
-
1221
-
val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1222
-
writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON);
1223
-
}
1224
-
EXPORT_SYMBOL_GPL(fimd_dp_clock_enable);
1225
1194
1226
1195
struct platform_driver fimd_driver = {
1227
1196
.probe = fimd_probe,
-15
drivers/gpu/drm/exynos/exynos_drm_fimd.h
-15
drivers/gpu/drm/exynos/exynos_drm_fimd.h
···
1
-
/*
2
-
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
3
-
*
4
-
* This program is free software; you can redistribute it and/or modify it
5
-
* under the terms of the GNU General Public License as published by the
6
-
* Free Software Foundation; either version 2 of the License, or (at your
7
-
* option) any later version.
8
-
*/
9
-
10
-
#ifndef _EXYNOS_DRM_FIMD_H_
11
-
#define _EXYNOS_DRM_FIMD_H_
12
-
13
-
extern void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable);
14
-
15
-
#endif /* _EXYNOS_DRM_FIMD_H_ */
+1
-1
drivers/gpu/drm/exynos/exynos_drm_plane.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_plane.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_vidi.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_vidi.c
+38
-34
drivers/gpu/drm/exynos/exynos_mixer.c
+38
-34
drivers/gpu/drm/exynos/exynos_mixer.c
···
44
44
#define MIXER_WIN_NR 3
45
45
#define MIXER_DEFAULT_WIN 0
46
46
47
+
/* The pixelformats that are natively supported by the mixer. */
48
+
#define MXR_FORMAT_RGB565 4
49
+
#define MXR_FORMAT_ARGB1555 5
50
+
#define MXR_FORMAT_ARGB4444 6
51
+
#define MXR_FORMAT_ARGB8888 7
52
+
47
53
struct mixer_resources {
48
54
int irq;
49
55
void __iomem *mixer_regs;
···
333
327
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
334
328
}
335
329
336
-
static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
330
+
static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
331
+
bool enable)
337
332
{
338
333
struct mixer_resources *res = &ctx->mixer_res;
339
334
u32 val = enable ? ~0 : 0;
···
366
359
struct mixer_resources *res = &ctx->mixer_res;
367
360
368
361
mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
369
-
370
-
mixer_regs_dump(ctx);
371
362
}
372
363
373
364
static void mixer_stop(struct mixer_context *ctx)
···
378
373
while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
379
374
--timeout)
380
375
usleep_range(10000, 12000);
381
-
382
-
mixer_regs_dump(ctx);
383
376
}
384
377
385
-
static void vp_video_buffer(struct mixer_context *ctx, int win)
378
+
static void vp_video_buffer(struct mixer_context *ctx, unsigned int win)
386
379
{
387
380
struct mixer_resources *res = &ctx->mixer_res;
388
381
unsigned long flags;
389
382
struct exynos_drm_plane *plane;
390
-
unsigned int buf_num = 1;
391
383
dma_addr_t luma_addr[2], chroma_addr[2];
392
384
bool tiled_mode = false;
393
385
bool crcb_mode = false;
···
395
393
switch (plane->pixel_format) {
396
394
case DRM_FORMAT_NV12:
397
395
crcb_mode = false;
398
-
buf_num = 2;
399
396
break;
400
-
/* TODO: single buffer format NV12, NV21 */
397
+
case DRM_FORMAT_NV21:
398
+
crcb_mode = true;
399
+
break;
401
400
default:
402
-
/* ignore pixel format at disable time */
403
-
if (!plane->dma_addr[0])
404
-
break;
405
-
406
401
DRM_ERROR("pixel format for vp is wrong [%d].\n",
407
402
plane->pixel_format);
408
403
return;
409
404
}
410
405
411
-
if (buf_num == 2) {
412
-
luma_addr[0] = plane->dma_addr[0];
413
-
chroma_addr[0] = plane->dma_addr[1];
414
-
} else {
415
-
luma_addr[0] = plane->dma_addr[0];
416
-
chroma_addr[0] = plane->dma_addr[0]
417
-
+ (plane->pitch * plane->fb_height);
418
-
}
406
+
luma_addr[0] = plane->dma_addr[0];
407
+
chroma_addr[0] = plane->dma_addr[1];
419
408
420
409
if (plane->scan_flag & DRM_MODE_FLAG_INTERLACE) {
421
410
ctx->interlace = true;
···
477
484
mixer_vsync_set_update(ctx, true);
478
485
spin_unlock_irqrestore(&res->reg_slock, flags);
479
486
487
+
mixer_regs_dump(ctx);
480
488
vp_regs_dump(ctx);
481
489
}
482
490
···
512
518
return -ENOTSUPP;
513
519
}
514
520
515
-
static void mixer_graph_buffer(struct mixer_context *ctx, int win)
521
+
static void mixer_graph_buffer(struct mixer_context *ctx, unsigned int win)
516
522
{
517
523
struct mixer_resources *res = &ctx->mixer_res;
518
524
unsigned long flags;
···
525
531
526
532
plane = &ctx->planes[win];
527
533
528
-
#define RGB565 4
529
-
#define ARGB1555 5
530
-
#define ARGB4444 6
531
-
#define ARGB8888 7
534
+
switch (plane->pixel_format) {
535
+
case DRM_FORMAT_XRGB4444:
536
+
fmt = MXR_FORMAT_ARGB4444;
537
+
break;
532
538
533
-
switch (plane->bpp) {
534
-
case 16:
535
-
fmt = ARGB4444;
539
+
case DRM_FORMAT_XRGB1555:
540
+
fmt = MXR_FORMAT_ARGB1555;
536
541
break;
537
-
case 32:
538
-
fmt = ARGB8888;
542
+
543
+
case DRM_FORMAT_RGB565:
544
+
fmt = MXR_FORMAT_RGB565;
539
545
break;
546
+
547
+
case DRM_FORMAT_XRGB8888:
548
+
case DRM_FORMAT_ARGB8888:
549
+
fmt = MXR_FORMAT_ARGB8888;
550
+
break;
551
+
540
552
default:
541
-
fmt = ARGB8888;
553
+
DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
554
+
return;
542
555
}
543
556
544
557
/* check if mixer supports requested scaling setup */
···
618
617
619
618
mixer_vsync_set_update(ctx, true);
620
619
spin_unlock_irqrestore(&res->reg_slock, flags);
620
+
621
+
mixer_regs_dump(ctx);
621
622
}
622
623
623
624
static void vp_win_reset(struct mixer_context *ctx)
···
1073
1070
mutex_unlock(&ctx->mixer_mutex);
1074
1071
1075
1072
mixer_stop(ctx);
1073
+
mixer_regs_dump(ctx);
1076
1074
mixer_window_suspend(ctx);
1077
1075
1078
1076
ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
···
1130
1126
return -EINVAL;
1131
1127
}
1132
1128
1133
-
static struct exynos_drm_crtc_ops mixer_crtc_ops = {
1129
+
static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1134
1130
.dpms = mixer_dpms,
1135
1131
.enable_vblank = mixer_enable_vblank,
1136
1132
.disable_vblank = mixer_disable_vblank,
···
1160
1156
.has_sclk = 1,
1161
1157
};
1162
1158
1163
-
static struct platform_device_id mixer_driver_types[] = {
1159
+
static const struct platform_device_id mixer_driver_types[] = {
1164
1160
{
1165
1161
.name = "s5p-mixer",
1166
1162
.driver_data = (unsigned long)&exynos4210_mxr_drv_data,
+11
-13
drivers/gpu/drm/i915/intel_pm.c
+11
-13
drivers/gpu/drm/i915/intel_pm.c
···
2045
2045
p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2046
2046
p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2047
2047
2048
-
if (crtc->primary->state->fb) {
2049
-
p->pri.enabled = true;
2048
+
if (crtc->primary->state->fb)
2050
2049
p->pri.bytes_per_pixel =
2051
2050
crtc->primary->state->fb->bits_per_pixel / 8;
2052
-
} else {
2053
-
p->pri.enabled = false;
2054
-
p->pri.bytes_per_pixel = 0;
2055
-
}
2051
+
else
2052
+
p->pri.bytes_per_pixel = 4;
2056
2053
2057
-
if (crtc->cursor->state->fb) {
2058
-
p->cur.enabled = true;
2059
-
p->cur.bytes_per_pixel = 4;
2060
-
} else {
2061
-
p->cur.enabled = false;
2062
-
p->cur.bytes_per_pixel = 0;
2063
-
}
2054
+
p->cur.bytes_per_pixel = 4;
2055
+
/*
2056
+
* TODO: for now, assume primary and cursor planes are always enabled.
2057
+
* Setting them to false makes the screen flicker.
2058
+
*/
2059
+
p->pri.enabled = true;
2060
+
p->cur.enabled = true;
2061
+
2064
2062
p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
2065
2063
p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
2066
2064
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+1
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
384
384
if (gpu->memptrs_bo) {
385
385
if (gpu->memptrs_iova)
386
386
msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
387
-
drm_gem_object_unreference(gpu->memptrs_bo);
387
+
drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
388
388
}
389
389
release_firmware(gpu->pm4);
390
390
release_firmware(gpu->pfp);
+5
-5
drivers/gpu/drm/msm/dsi/dsi.c
+5
-5
drivers/gpu/drm/msm/dsi/dsi.c
···
177
177
goto fail;
178
178
}
179
179
180
+
for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
181
+
encoders[i]->bridge = msm_dsi->bridge;
182
+
msm_dsi->encoders[i] = encoders[i];
183
+
}
184
+
180
185
msm_dsi->connector = msm_dsi_manager_connector_init(msm_dsi->id);
181
186
if (IS_ERR(msm_dsi->connector)) {
182
187
ret = PTR_ERR(msm_dsi->connector);
183
188
dev_err(dev->dev, "failed to create dsi connector: %d\n", ret);
184
189
msm_dsi->connector = NULL;
185
190
goto fail;
186
-
}
187
-
188
-
for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) {
189
-
encoders[i]->bridge = msm_dsi->bridge;
190
-
msm_dsi->encoders[i] = encoders[i];
191
191
}
192
192
193
193
priv->bridges[priv->num_bridges++] = msm_dsi->bridge;
+8
-13
drivers/gpu/drm/msm/dsi/dsi_host.c
+8
-13
drivers/gpu/drm/msm/dsi/dsi_host.c
···
1023
1023
*data = buf[1]; /* strip out dcs type */
1024
1024
return 1;
1025
1025
} else {
1026
-
pr_err("%s: read data does not match with rx_buf len %d\n",
1026
+
pr_err("%s: read data does not match with rx_buf len %zu\n",
1027
1027
__func__, msg->rx_len);
1028
1028
return -EINVAL;
1029
1029
}
···
1040
1040
data[1] = buf[2];
1041
1041
return 2;
1042
1042
} else {
1043
-
pr_err("%s: read data does not match with rx_buf len %d\n",
1043
+
pr_err("%s: read data does not match with rx_buf len %zu\n",
1044
1044
__func__, msg->rx_len);
1045
1045
return -EINVAL;
1046
1046
}
···
1093
1093
{
1094
1094
u32 *lp, *temp, data;
1095
1095
int i, j = 0, cnt;
1096
-
bool ack_error = false;
1097
1096
u32 read_cnt;
1098
1097
u8 reg[16];
1099
1098
int repeated_bytes = 0;
···
1104
1105
if (cnt > 4)
1105
1106
cnt = 4; /* 4 x 32 bits registers only */
1106
1107
1107
-
/* Calculate real read data count */
1108
-
read_cnt = dsi_read(msm_host, 0x1d4) >> 16;
1109
-
1110
-
ack_error = (rx_byte == 4) ?
1111
-
(read_cnt == 8) : /* short pkt + 4-byte error pkt */
1112
-
(read_cnt == (pkt_size + 6 + 4)); /* long pkt+4-byte error pkt*/
1113
-
1114
-
if (ack_error)
1115
-
read_cnt -= 4; /* Remove 4 byte error pkt */
1108
+
if (rx_byte == 4)
1109
+
read_cnt = 4;
1110
+
else
1111
+
read_cnt = pkt_size + 6;
1116
1112
1117
1113
/*
1118
1114
* In case of multiple reads from the panel, after the first read, there
···
1209
1215
container_of(work, struct msm_dsi_host, err_work);
1210
1216
u32 status = msm_host->err_work_state;
1211
1217
1212
-
pr_err("%s: status=%x\n", __func__, status);
1218
+
pr_err_ratelimited("%s: status=%x\n", __func__, status);
1213
1219
if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1214
1220
dsi_sw_reset_restore(msm_host);
1215
1221
···
1791
1797
case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1792
1798
pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
1793
1799
ret = 0;
1800
+
break;
1794
1801
case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1795
1802
case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1796
1803
ret = dsi_short_read1_resp(buf, msg);
+5
-1
drivers/gpu/drm/msm/dsi/dsi_manager.c
+5
-1
drivers/gpu/drm/msm/dsi/dsi_manager.c
···
462
462
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
463
463
struct drm_connector *connector = NULL;
464
464
struct dsi_connector *dsi_connector;
465
-
int ret;
465
+
int ret, i;
466
466
467
467
dsi_connector = devm_kzalloc(msm_dsi->dev->dev,
468
468
sizeof(*dsi_connector), GFP_KERNEL);
···
494
494
ret = drm_connector_register(connector);
495
495
if (ret)
496
496
goto fail;
497
+
498
+
for (i = 0; i < MSM_DSI_ENCODER_NUM; i++)
499
+
drm_mode_connector_attach_encoder(connector,
500
+
msm_dsi->encoders[i]);
497
501
498
502
return connector;
499
503
+2
-2
drivers/gpu/drm/msm/edp/edp_aux.c
+2
-2
drivers/gpu/drm/msm/edp/edp_aux.c
···
132
132
/* msg sanity check */
133
133
if ((native && (msg->size > AUX_CMD_NATIVE_MAX)) ||
134
134
(msg->size > AUX_CMD_I2C_MAX)) {
135
-
pr_err("%s: invalid msg: size(%d), request(%x)\n",
135
+
pr_err("%s: invalid msg: size(%zu), request(%x)\n",
136
136
__func__, msg->size, msg->request);
137
137
return -EINVAL;
138
138
}
···
155
155
*/
156
156
edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0);
157
157
msm_edp_aux_ctrl(aux, 1);
158
-
pr_err("%s: aux timeout, %d\n", __func__, ret);
158
+
pr_err("%s: aux timeout, %zd\n", __func__, ret);
159
159
goto unlock_exit;
160
160
}
161
161
DBG("completion");
+2
drivers/gpu/drm/msm/edp/edp_connector.c
+2
drivers/gpu/drm/msm/edp/edp_connector.c
+2
-1
drivers/gpu/drm/msm/edp/edp_ctrl.c
+2
-1
drivers/gpu/drm/msm/edp/edp_ctrl.c
···
1149
1149
ctrl->aux = msm_edp_aux_init(dev, ctrl->base, &ctrl->drm_aux);
1150
1150
if (!ctrl->aux || !ctrl->drm_aux) {
1151
1151
pr_err("%s:failed to init aux\n", __func__);
1152
-
return ret;
1152
+
return -ENOMEM;
1153
1153
}
1154
1154
1155
1155
ctrl->phy = msm_edp_phy_init(dev, ctrl->base);
1156
1156
if (!ctrl->phy) {
1157
1157
pr_err("%s:failed to init phy\n", __func__);
1158
+
ret = -ENOMEM;
1158
1159
goto err_destory_aux;
1159
1160
}
1160
1161
+17
-17
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+17
-17
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
···
72
72
.base = { 0x12d00, 0x12e00, 0x12f00 },
73
73
},
74
74
.intf = {
75
-
.count = 4,
76
75
.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
77
-
},
78
-
.intfs = {
79
-
[0] = INTF_eDP,
80
-
[1] = INTF_DSI,
81
-
[2] = INTF_DSI,
82
-
[3] = INTF_HDMI,
76
+
.connect = {
77
+
[0] = INTF_eDP,
78
+
[1] = INTF_DSI,
79
+
[2] = INTF_DSI,
80
+
[3] = INTF_HDMI,
81
+
},
83
82
},
84
83
.max_clk = 200000000,
85
84
};
···
141
142
.base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
142
143
},
143
144
.intf = {
144
-
.count = 5,
145
145
.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
146
-
},
147
-
.intfs = {
148
-
[0] = INTF_eDP,
149
-
[1] = INTF_DSI,
150
-
[2] = INTF_DSI,
151
-
[3] = INTF_HDMI,
146
+
.connect = {
147
+
[0] = INTF_eDP,
148
+
[1] = INTF_DSI,
149
+
[2] = INTF_DSI,
150
+
[3] = INTF_HDMI,
151
+
},
152
152
},
153
153
.max_clk = 320000000,
154
154
};
···
194
196
195
197
},
196
198
.intf = {
197
-
.count = 1, /* INTF_1 */
198
-
.base = { 0x6B800 },
199
+
.base = { 0x00000, 0x6b800 },
200
+
.connect = {
201
+
[0] = INTF_DISABLED,
202
+
[1] = INTF_DSI,
203
+
},
199
204
},
200
-
/* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
201
205
.max_clk = 320000000,
202
206
};
203
207
+6
-3
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+6
-3
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
···
59
59
60
60
#define MDP5_INTF_NUM_MAX 5
61
61
62
+
struct mdp5_intf_block {
63
+
uint32_t base[MAX_BASES];
64
+
u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
65
+
};
66
+
62
67
struct mdp5_cfg_hw {
63
68
char *name;
64
69
···
77
72
struct mdp5_sub_block dspp;
78
73
struct mdp5_sub_block ad;
79
74
struct mdp5_sub_block pp;
80
-
struct mdp5_sub_block intf;
81
-
82
-
u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
75
+
struct mdp5_intf_block intf;
83
76
84
77
uint32_t max_clk;
85
78
};
+6
-6
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+6
-6
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
···
206
206
207
207
static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
208
208
{
209
-
const int intf_cnt = hw_cfg->intf.count;
210
-
const u32 *intfs = hw_cfg->intfs;
209
+
const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
210
+
const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
211
211
int id = 0, i;
212
212
213
213
for (i = 0; i < intf_cnt; i++) {
···
228
228
struct msm_drm_private *priv = dev->dev_private;
229
229
const struct mdp5_cfg_hw *hw_cfg =
230
230
mdp5_cfg_get_hw_config(mdp5_kms->cfg);
231
-
enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num];
231
+
enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
232
232
struct drm_encoder *encoder;
233
233
int ret = 0;
234
234
···
365
365
/* Construct encoders and modeset initialize connector devices
366
366
* for each external display interface.
367
367
*/
368
-
for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) {
368
+
for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
369
369
ret = modeset_init_intf(mdp5_kms, i);
370
370
if (ret)
371
371
goto fail;
···
514
514
*/
515
515
mdp5_enable(mdp5_kms);
516
516
for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
517
-
if (!config->hw->intf.base[i] ||
518
-
mdp5_cfg_intf_is_virtual(config->hw->intfs[i]))
517
+
if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
518
+
!config->hw->intf.base[i])
519
519
continue;
520
520
mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
521
521
}
+1
-1
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+1
-1
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
···
273
273
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
274
274
msm_framebuffer_iova(fb, mdp5_kms->id, 2));
275
275
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
276
-
msm_framebuffer_iova(fb, mdp5_kms->id, 4));
276
+
msm_framebuffer_iova(fb, mdp5_kms->id, 3));
277
277
278
278
plane->fb = fb;
279
279
}
+14
-10
drivers/gpu/drm/msm/msm_drv.c
+14
-10
drivers/gpu/drm/msm/msm_drv.c
···
21
21
22
22
static void msm_fb_output_poll_changed(struct drm_device *dev)
23
23
{
24
+
#ifdef CONFIG_DRM_MSM_FBDEV
24
25
struct msm_drm_private *priv = dev->dev_private;
25
26
if (priv->fbdev)
26
27
drm_fb_helper_hotplug_event(priv->fbdev);
28
+
#endif
27
29
}
28
30
29
31
static const struct drm_mode_config_funcs mode_config_funcs = {
···
96
94
}
97
95
98
96
if (reglog)
99
-
printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
97
+
printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
100
98
101
99
return ptr;
102
100
}
···
104
102
void msm_writel(u32 data, void __iomem *addr)
105
103
{
106
104
if (reglog)
107
-
printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
105
+
printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
108
106
writel(data, addr);
109
107
}
110
108
···
112
110
{
113
111
u32 val = readl(addr);
114
112
if (reglog)
115
-
printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
113
+
printk(KERN_ERR "IO:R %p %08x\n", addr, val);
116
114
return val;
117
115
}
118
116
···
145
143
if (gpu) {
146
144
mutex_lock(&dev->struct_mutex);
147
145
gpu->funcs->pm_suspend(gpu);
148
-
gpu->funcs->destroy(gpu);
149
146
mutex_unlock(&dev->struct_mutex);
147
+
gpu->funcs->destroy(gpu);
150
148
}
151
149
152
150
if (priv->vram.paddr) {
···
179
177
const struct of_device_id *match;
180
178
match = of_match_node(match_types, dev->of_node);
181
179
if (match)
182
-
return (int)match->data;
180
+
return (int)(unsigned long)match->data;
183
181
#endif
184
182
return 4;
185
183
}
···
218
216
if (ret)
219
217
return ret;
220
218
size = r.end - r.start;
221
-
DRM_INFO("using VRAM carveout: %lx@%08x\n", size, r.start);
219
+
DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
222
220
} else
223
221
#endif
224
222
···
285
283
286
284
drm_mode_config_init(dev);
287
285
288
-
ret = msm_init_vram(dev);
289
-
if (ret)
290
-
goto fail;
291
-
292
286
platform_set_drvdata(pdev, dev);
293
287
294
288
/* Bind all our sub-components: */
295
289
ret = component_bind_all(dev->dev, dev);
296
290
if (ret)
297
291
return ret;
292
+
293
+
ret = msm_init_vram(dev);
294
+
if (ret)
295
+
goto fail;
298
296
299
297
switch (get_mdp_ver(pdev)) {
300
298
case 4:
···
421
419
422
420
static void msm_lastclose(struct drm_device *dev)
423
421
{
422
+
#ifdef CONFIG_DRM_MSM_FBDEV
424
423
struct msm_drm_private *priv = dev->dev_private;
425
424
if (priv->fbdev)
426
425
drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
426
+
#endif
427
427
}
428
428
429
429
static irqreturn_t msm_irq(int irq, void *arg)
+3
-4
drivers/gpu/drm/msm/msm_fb.c
+3
-4
drivers/gpu/drm/msm/msm_fb.c
···
172
172
{
173
173
struct msm_drm_private *priv = dev->dev_private;
174
174
struct msm_kms *kms = priv->kms;
175
-
struct msm_framebuffer *msm_fb;
176
-
struct drm_framebuffer *fb = NULL;
175
+
struct msm_framebuffer *msm_fb = NULL;
176
+
struct drm_framebuffer *fb;
177
177
const struct msm_format *format;
178
178
int ret, i, n;
179
179
unsigned int hsub, vsub;
···
239
239
return fb;
240
240
241
241
fail:
242
-
if (fb)
243
-
msm_framebuffer_destroy(fb);
242
+
kfree(msm_fb);
244
243
245
244
return ERR_PTR(ret);
246
245
}
+1
-1
drivers/gpu/drm/msm/msm_gem.c
+1
-1
drivers/gpu/drm/msm/msm_gem.c
···
483
483
uint64_t off = drm_vma_node_start(&obj->vma_node);
484
484
485
485
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
486
-
seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %p %d\n",
486
+
seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %p %zu\n",
487
487
msm_obj->flags, is_active(msm_obj) ? 'A' : 'I',
488
488
msm_obj->read_fence, msm_obj->write_fence,
489
489
obj->name, obj->refcount.refcount.counter,
+2
-2
drivers/gpu/drm/msm/msm_iommu.c
+2
-2
drivers/gpu/drm/msm/msm_iommu.c
···
60
60
u32 pa = sg_phys(sg) - sg->offset;
61
61
size_t bytes = sg->length + sg->offset;
62
62
63
-
VERB("map[%d]: %08x %08x(%x)", i, iova, pa, bytes);
63
+
VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes);
64
64
65
65
ret = iommu_map(domain, da, pa, bytes, prot);
66
66
if (ret)
···
99
99
if (unmapped < bytes)
100
100
return unmapped;
101
101
102
-
VERB("unmap[%d]: %08x(%x)", i, iova, bytes);
102
+
VERB("unmap[%d]: %08x(%zx)", i, iova, bytes);
103
103
104
104
BUG_ON(!PAGE_ALIGNED(bytes));
105
105
+1
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+1
-1
drivers/gpu/drm/msm/msm_ringbuffer.c
+11
-9
drivers/gpu/drm/radeon/atombios_dp.c
+11
-9
drivers/gpu/drm/radeon/atombios_dp.c
···
421
421
{
422
422
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
423
423
u8 msg[DP_DPCD_SIZE];
424
-
int ret;
424
+
int ret, i;
425
425
426
-
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
427
-
DP_DPCD_SIZE);
428
-
if (ret > 0) {
429
-
memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
426
+
for (i = 0; i < 7; i++) {
427
+
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
428
+
DP_DPCD_SIZE);
429
+
if (ret == DP_DPCD_SIZE) {
430
+
memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
430
431
431
-
DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
432
-
dig_connector->dpcd);
432
+
DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
433
+
dig_connector->dpcd);
433
434
434
-
radeon_dp_probe_oui(radeon_connector);
435
+
radeon_dp_probe_oui(radeon_connector);
435
436
436
-
return true;
437
+
return true;
438
+
}
437
439
}
438
440
dig_connector->dpcd[0] = 0;
439
441
return false;
-2
drivers/gpu/drm/radeon/radeon_dp_auxch.c
-2
drivers/gpu/drm/radeon/radeon_dp_auxch.c