+1 -1

drivers/clk/mediatek/reset.c

reviewed

··· 57 57 return mtk_reset_deassert(rcdev, id); 58 58 } 59 59 60 60 - static struct reset_control_ops mtk_reset_ops = { 60 60 + static const struct reset_control_ops mtk_reset_ops = { 61 61 .assert = mtk_reset_assert, 62 62 .deassert = mtk_reset_deassert, 63 63 .reset = mtk_reset,

+1 -1

drivers/clk/mmp/reset.c

reviewed

··· 74 74 return 0; 75 75 } 76 76 77 77 - static struct reset_control_ops mmp_clk_reset_ops = { 77 77 + static const struct reset_control_ops mmp_clk_reset_ops = { 78 78 .assert = mmp_clk_reset_assert, 79 79 .deassert = mmp_clk_reset_deassert, 80 80 };

+35 -35

drivers/clk/qcom/gcc-ipq4019.c

reviewed

··· 129 129 }; 130 130 131 131 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 132 132 - #define P_XO 0 133 133 - #define FE_PLL_200 1 134 134 - #define FE_PLL_500 2 135 135 - #define DDRC_PLL_666 3 136 136 - 137 137 - #define DDRC_PLL_666_SDCC 1 138 138 - #define FE_PLL_125_DLY 1 139 139 - 140 140 - #define FE_PLL_WCSS2G 1 141 141 - #define FE_PLL_WCSS5G 1 142 132 143 133 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = { 144 134 F(48000000, P_XO, 1, 0, 0), 145 145 - F(200000000, FE_PLL_200, 1, 0, 0), 135 135 + F(200000000, P_FEPLL200, 1, 0, 0), 146 136 { } 147 137 }; 148 138 ··· 324 334 }; 325 335 326 336 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = { 327 327 - F(1843200, FE_PLL_200, 1, 144, 15625), 328 328 - F(3686400, FE_PLL_200, 1, 288, 15625), 329 329 - F(7372800, FE_PLL_200, 1, 576, 15625), 330 330 - F(14745600, FE_PLL_200, 1, 1152, 15625), 331 331 - F(16000000, FE_PLL_200, 1, 2, 25), 337 337 + F(1843200, P_FEPLL200, 1, 144, 15625), 338 338 + F(3686400, P_FEPLL200, 1, 288, 15625), 339 339 + F(7372800, P_FEPLL200, 1, 576, 15625), 340 340 + F(14745600, P_FEPLL200, 1, 1152, 15625), 341 341 + F(16000000, P_FEPLL200, 1, 2, 25), 332 342 F(24000000, P_XO, 1, 1, 2), 333 333 - F(32000000, FE_PLL_200, 1, 4, 25), 334 334 - F(40000000, FE_PLL_200, 1, 1, 5), 335 335 - F(46400000, FE_PLL_200, 1, 29, 125), 343 343 + F(32000000, P_FEPLL200, 1, 4, 25), 344 344 + F(40000000, P_FEPLL200, 1, 1, 5), 345 345 + F(46400000, P_FEPLL200, 1, 29, 125), 336 346 F(48000000, P_XO, 1, 0, 0), 337 347 { } 338 348 }; ··· 400 410 }; 401 411 402 412 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 403 403 - F(1250000, FE_PLL_200, 1, 16, 0), 404 404 - F(2500000, FE_PLL_200, 1, 8, 0), 405 405 - F(5000000, FE_PLL_200, 1, 4, 0), 413 413 + F(1250000, P_FEPLL200, 1, 16, 0), 414 414 + F(2500000, P_FEPLL200, 1, 8, 0), 415 415 + F(5000000, P_FEPLL200, 1, 4, 0), 406 416 { } 407 417 }; 408 418 ··· 502 512 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 503 513 F(144000, P_XO, 1, 3, 240), 504 514 F(400000, P_XO, 1, 1, 0), 505 505 - F(20000000, FE_PLL_500, 1, 1, 25), 506 506 - F(25000000, FE_PLL_500, 1, 1, 20), 507 507 - F(50000000, FE_PLL_500, 1, 1, 10), 508 508 - F(100000000, FE_PLL_500, 1, 1, 5), 509 509 - F(193000000, DDRC_PLL_666_SDCC, 1, 0, 0), 515 515 + F(20000000, P_FEPLL500, 1, 1, 25), 516 516 + F(25000000, P_FEPLL500, 1, 1, 20), 517 517 + F(50000000, P_FEPLL500, 1, 1, 10), 518 518 + F(100000000, P_FEPLL500, 1, 1, 5), 519 519 + F(193000000, P_DDRPLL, 1, 0, 0), 510 520 { } 511 521 }; 512 522 ··· 526 536 527 537 static const struct freq_tbl ftbl_gcc_apps_clk[] = { 528 538 F(48000000, P_XO, 1, 0, 0), 529 529 - F(200000000, FE_PLL_200, 1, 0, 0), 530 530 - F(500000000, FE_PLL_500, 1, 0, 0), 531 531 - F(626000000, DDRC_PLL_666, 1, 0, 0), 539 539 + F(200000000, P_FEPLL200, 1, 0, 0), 540 540 + F(500000000, P_FEPLL500, 1, 0, 0), 541 541 + F(626000000, P_DDRPLLAPSS, 1, 0, 0), 532 542 { } 533 543 }; 534 544 ··· 547 557 548 558 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = { 549 559 F(48000000, P_XO, 1, 0, 0), 550 550 - F(100000000, FE_PLL_200, 2, 0, 0), 560 560 + F(100000000, P_FEPLL200, 2, 0, 0), 551 561 { } 552 562 }; 553 563 ··· 930 940 }; 931 941 932 942 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 933 933 - F(2000000, FE_PLL_200, 10, 0, 0), 943 943 + F(2000000, P_FEPLL200, 10, 0, 0), 934 944 { } 935 945 }; 936 946 ··· 997 1007 }; 998 1008 999 1009 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = { 1000 1000 - F(125000000, FE_PLL_125_DLY, 1, 0, 0), 1010 1010 + F(125000000, P_FEPLL125DLY, 1, 0, 0), 1001 1011 { } 1002 1012 }; 1003 1013 ··· 1017 1027 1018 1028 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = { 1019 1029 F(48000000, P_XO, 1, 0, 0), 1020 1020 - F(250000000, FE_PLL_WCSS2G, 1, 0, 0), 1030 1030 + F(250000000, P_FEPLLWCSS2G, 1, 0, 0), 1021 1031 { } 1022 1032 }; 1023 1033 ··· 1087 1097 1088 1098 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = { 1089 1099 F(48000000, P_XO, 1, 0, 0), 1090 1090 - F(250000000, FE_PLL_WCSS5G, 1, 0, 0), 1100 1100 + F(250000000, P_FEPLLWCSS5G, 1, 0, 0), 1091 1101 { } 1092 1102 }; 1093 1103 ··· 1315 1325 1316 1326 static int gcc_ipq4019_probe(struct platform_device *pdev) 1317 1327 { 1328 1328 + struct device *dev = &pdev->dev; 1329 1329 + 1330 1330 + clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000); 1331 1331 + clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000); 1332 1332 + clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000); 1333 1333 + clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000); 1334 1334 + clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000); 1335 1335 + clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000); 1336 1336 + clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000); 1337 1337 + 1318 1338 return qcom_cc_probe(pdev, &gcc_ipq4019_desc); 1319 1339 } 1320 1340

+1 -1

drivers/clk/qcom/reset.c

reviewed

··· 55 55 return regmap_update_bits(rst->regmap, map->reg, mask, 0); 56 56 } 57 57 58 58 - struct reset_control_ops qcom_reset_ops = { 58 58 + const struct reset_control_ops qcom_reset_ops = { 59 59 .reset = qcom_reset, 60 60 .assert = qcom_reset_assert, 61 61 .deassert = qcom_reset_deassert,

+1 -1

drivers/clk/qcom/reset.h

reviewed

··· 32 32 #define to_qcom_reset_controller(r) \ 33 33 container_of(r, struct qcom_reset_controller, rcdev); 34 34 35 35 - extern struct reset_control_ops qcom_reset_ops; 35 35 + extern const struct reset_control_ops qcom_reset_ops; 36 36 37 37 #endif

+1 -1

drivers/clk/rockchip/softrst.c

reviewed

··· 81 81 return 0; 82 82 } 83 83 84 84 - static struct reset_control_ops rockchip_softrst_ops = { 84 84 + static const struct reset_control_ops rockchip_softrst_ops = { 85 85 .assert = rockchip_softrst_assert, 86 86 .deassert = rockchip_softrst_deassert, 87 87 };

+1 -1

drivers/clk/sirf/clk-atlas7.c

reviewed

··· 1423 1423 return 0; 1424 1424 } 1425 1425 1426 1426 - static struct reset_control_ops atlas7_rst_ops = { 1426 1426 + static const struct reset_control_ops atlas7_rst_ops = { 1427 1427 .reset = atlas7_reset_module, 1428 1428 }; 1429 1429

+1 -1

drivers/clk/sunxi/clk-a10-ve.c

reviewed

··· 85 85 return 0; 86 86 } 87 87 88 88 - static struct reset_control_ops sunxi_ve_reset_ops = { 88 88 + static const struct reset_control_ops sunxi_ve_reset_ops = { 89 89 .assert = sunxi_ve_reset_assert, 90 90 .deassert = sunxi_ve_reset_deassert, 91 91 };

+1 -1

drivers/clk/sunxi/clk-sun9i-mmc.c

reviewed

··· 83 83 return 0; 84 84 } 85 85 86 86 - static struct reset_control_ops sun9i_mmc_reset_ops = { 86 86 + static const struct reset_control_ops sun9i_mmc_reset_ops = { 87 87 .assert = sun9i_mmc_reset_assert, 88 88 .deassert = sun9i_mmc_reset_deassert, 89 89 };

+1 -1

drivers/clk/sunxi/clk-usb.c

reviewed

··· 76 76 return 0; 77 77 } 78 78 79 79 - static struct reset_control_ops sunxi_usb_reset_ops = { 79 79 + static const struct reset_control_ops sunxi_usb_reset_ops = { 80 80 .assert = sunxi_usb_reset_assert, 81 81 .deassert = sunxi_usb_reset_deassert, 82 82 };

+1 -1

drivers/clk/tegra/clk.c

reviewed

··· 271 271 } 272 272 } 273 273 274 274 - static struct reset_control_ops rst_ops = { 274 274 + static const struct reset_control_ops rst_ops = { 275 275 .assert = tegra_clk_rst_assert, 276 276 .deassert = tegra_clk_rst_deassert, 277 277 };