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arm64: Provide dcache_inval_poc_nosync helper

dcache_inval_poc_nosync does not wait for the data cache invalidation to
complete. Later, we defer the synchronization so we can wait for all SG
entries together.

Cc: Leon Romanovsky <leon@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Suren Baghdasaryan <surenb@google.com>
Cc: Tangquan Zheng <zhengtangquan@oppo.com>
Tested-by: Xueyuan Chen <xueyuan.chen21@gmail.com>
Signed-off-by: Barry Song <baohua@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20260228221258.59918-1-21cnbao@gmail.com

authored by

Barry Song and committed by
Marek Szyprowski cf875c4b 1c3a7f9e

+32 -11
+1
arch/arm64/include/asm/cacheflush.h
··· 74 74 extern void dcache_clean_inval_poc(unsigned long start, unsigned long end); 75 75 extern void dcache_inval_poc(unsigned long start, unsigned long end); 76 76 extern void dcache_clean_poc(unsigned long start, unsigned long end); 77 + extern void dcache_inval_poc_nosync(unsigned long start, unsigned long end); 77 78 extern void dcache_clean_poc_nosync(unsigned long start, unsigned long end); 78 79 extern void dcache_clean_pop(unsigned long start, unsigned long end); 79 80 extern void dcache_clean_pou(unsigned long start, unsigned long end);
+31 -11
arch/arm64/mm/cache.S
··· 132 132 ret 133 133 SYM_FUNC_END(dcache_clean_pou) 134 134 135 - /* 136 - * dcache_inval_poc(start, end) 137 - * 138 - * Ensure that any D-cache lines for the interval [start, end) 139 - * are invalidated. Any partial lines at the ends of the interval are 140 - * also cleaned to PoC to prevent data loss. 141 - * 142 - * - start - kernel start address of region 143 - * - end - kernel end address of region 144 - */ 145 - SYM_FUNC_START(__pi_dcache_inval_poc) 135 + .macro __dcache_inval_poc_nosync 146 136 dcache_line_size x2, x3 147 137 sub x3, x2, #1 148 138 tst x1, x3 // end cache line aligned? ··· 148 158 3: add x0, x0, x2 149 159 cmp x0, x1 150 160 b.lo 2b 161 + .endm 162 + 163 + /* 164 + * dcache_inval_poc(start, end) 165 + * 166 + * Ensure that any D-cache lines for the interval [start, end) 167 + * are invalidated. Any partial lines at the ends of the interval are 168 + * also cleaned to PoC to prevent data loss. 169 + * 170 + * - start - kernel start address of region 171 + * - end - kernel end address of region 172 + */ 173 + SYM_FUNC_START(__pi_dcache_inval_poc) 174 + __dcache_inval_poc_nosync 151 175 dsb sy 152 176 ret 153 177 SYM_FUNC_END(__pi_dcache_inval_poc) 154 178 SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc) 179 + 180 + /* 181 + * dcache_inval_poc_nosync(start, end) 182 + * 183 + * Issue the instructions of D-cache lines for the interval [start, end) 184 + * for invalidation. Not necessarily cleaned to PoC till an explicit dsb 185 + * sy is issued later 186 + * 187 + * - start - kernel start address of region 188 + * - end - kernel end address of region 189 + */ 190 + SYM_FUNC_START(__pi_dcache_inval_poc_nosync) 191 + __dcache_inval_poc_nosync 192 + ret 193 + SYM_FUNC_END(__pi_dcache_inval_poc_nosync) 194 + SYM_FUNC_ALIAS(dcache_inval_poc_nosync, __pi_dcache_inval_poc_nosync) 155 195 156 196 /* 157 197 * dcache_clean_poc(start, end)