Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
crypto: hisilicon/hpre - save capability registers in probe process
Pre-store the valid value of hpre alg support related capability
register in hpre_qm_init(), which will be called by hpre_probe().
It can reduce the number of capability register queries and avoid
obtaining incorrect values in abnormal scenarios, such as reset
failed and the memory space disabled.
Fixes: f214d59a0603 ("crypto: hisilicon/hpre - support hpre capability")
Signed-off-by: Zhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Zhiqi Song
and committed by
Herbert Xu
cf8b5156
cabe13d0
+64
-18
+64
-18
drivers/crypto/hisilicon/hpre/hpre_main.c
+64
-18
drivers/crypto/hisilicon/hpre/hpre_main.c
···
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{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}
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};
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+
enum hpre_pre_store_cap_idx {
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HPRE_CLUSTER_NUM_CAP_IDX = 0x0,
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HPRE_CORE_ENABLE_BITMAP_CAP_IDX,
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HPRE_DRV_ALG_BITMAP_CAP_IDX,
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HPRE_DEV_ALG_BITMAP_CAP_IDX,
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};
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+
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+
static const u32 hpre_pre_store_caps[] = {
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HPRE_CLUSTER_NUM_CAP,
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HPRE_CORE_ENABLE_BITMAP_CAP,
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HPRE_DRV_ALG_BITMAP_CAP,
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HPRE_DEV_ALG_BITMAP_CAP,
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+
};
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+
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static const struct hpre_hw_error hpre_hw_errors[] = {
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{
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.int_msk = BIT(0),
···
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{
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u32 cap_val;
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-
cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);
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+
cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;
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if (alg & cap_val)
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return true;
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···
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
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-
static inline int hpre_cluster_num(struct hisi_qm *qm)
442
-
{
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-
return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CLUSTER_NUM_CAP, qm->cap_ver);
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-
}
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-
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-
static inline int hpre_cluster_core_mask(struct hisi_qm *qm)
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-
{
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-
return hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CORE_ENABLE_BITMAP_CAP, qm->cap_ver);
449
-
}
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-
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struct hisi_qp *hpre_create_qp(u8 type)
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{
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int node = cpu_to_node(smp_processor_id());
···
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static int hpre_set_cluster(struct hisi_qm *qm)
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{
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-
u32 cluster_core_mask = hpre_cluster_core_mask(qm);
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-
u8 clusters_num = hpre_cluster_num(qm);
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struct device *dev = &qm->pdev->dev;
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unsigned long offset;
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+
u32 cluster_core_mask;
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+
u8 clusters_num;
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u32 val = 0;
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int ret, i;
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+
cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val;
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+
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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offset = i * HPRE_CLSTR_ADDR_INTRVL;
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···
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static void hpre_cnt_regs_clear(struct hisi_qm *qm)
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{
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-
u8 clusters_num = hpre_cluster_num(qm);
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unsigned long offset;
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+
u8 clusters_num;
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int i;
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/* clear clusterX/cluster_ctrl */
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+
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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for (i = 0; i < clusters_num; i++) {
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offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
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writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
···
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static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
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{
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-
u8 clusters_num = hpre_cluster_num(qm);
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struct device *dev = &qm->pdev->dev;
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char buf[HPRE_DBGFS_VAL_MAX_LEN];
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struct debugfs_regset32 *regset;
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struct dentry *tmp_d;
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+
u8 clusters_num;
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1000
int i, ret;
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1001
1002
+
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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1003
for (i = 0; i < clusters_num; i++) {
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ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
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if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
···
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debugfs_remove_recursive(qm->debug.debug_root);
1112
1104
}
1113
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1106
+
static int hpre_pre_store_cap_reg(struct hisi_qm *qm)
1107
+
{
1108
+
struct hisi_qm_cap_record *hpre_cap;
1109
+
struct device *dev = &qm->pdev->dev;
1110
+
size_t i, size;
1111
+
1112
+
size = ARRAY_SIZE(hpre_pre_store_caps);
1113
+
hpre_cap = devm_kzalloc(dev, sizeof(*hpre_cap) * size, GFP_KERNEL);
1114
+
if (!hpre_cap)
1115
+
return -ENOMEM;
1116
+
1117
+
for (i = 0; i < size; i++) {
1118
+
hpre_cap[i].type = hpre_pre_store_caps[i];
1119
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hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,
1120
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hpre_pre_store_caps[i], qm->cap_ver);
1121
+
}
1122
+
1123
+
if (hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val > HPRE_CLUSTERS_NUM_MAX) {
1124
+
dev_err(dev, "Device cluster num %u is out of range for driver supports %d!\n",
1125
+
hpre_cap[HPRE_CLUSTER_NUM_CAP_IDX].cap_val, HPRE_CLUSTERS_NUM_MAX);
1126
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return -EINVAL;
1127
+
}
1128
+
1129
+
qm->cap_tables.dev_cap_table = hpre_cap;
1130
+
1131
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return 0;
1132
+
}
1133
+
1114
1134
static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1115
1135
{
1116
1136
u64 alg_msk;
···
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return ret;
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}
1174
1138
1175
-
alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);
1139
+
/* Fetch and save the value of capability registers */
1140
+
ret = hpre_pre_store_cap_reg(qm);
1141
+
if (ret) {
1142
+
pci_err(pdev, "Failed to pre-store capability registers!\n");
1143
+
hisi_qm_uninit(qm);
1144
+
return ret;
1145
+
}
1146
+
1147
+
alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;
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ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));
1177
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if (ret) {
1178
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pci_err(pdev, "Failed to set hpre algs!\n");
···
1194
1150
{
1195
1151
int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
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1152
int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1197
-
u8 clusters_num = hpre_cluster_num(qm);
1198
1153
struct qm_debug *debug = &qm->debug;
1199
1154
void __iomem *io_base;
1155
+
u8 clusters_num;
1200
1156
int i, j, idx;
1201
1157
1158
+
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
1203
1160
com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
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1161
if (!debug->last_words)
···
1236
1191
{
1237
1192
int cluster_dfx_regs_num = ARRAY_SIZE(hpre_cluster_dfx_regs);
1238
1193
int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
1239
-
u8 clusters_num = hpre_cluster_num(qm);
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1194
struct qm_debug *debug = &qm->debug;
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1195
struct pci_dev *pdev = qm->pdev;
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1196
void __iomem *io_base;
1197
+
u8 clusters_num;
1243
1198
int i, j, idx;
1244
1199
u32 val;
1245
1200
···
1254
1209
hpre_com_dfx_regs[i].name, debug->last_words[i], val);
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1210
}
1256
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1212
+
clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val;
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1213
for (i = 0; i < clusters_num; i++) {
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1214
io_base = qm->io_base + hpre_cluster_offsets[i];
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1215
for (j = 0; j < cluster_dfx_regs_num; j++) {