tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'amd-drm-next-6.18-2025-09-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-6.18-2025-09-09:

amdgpu:
- Add CRIU support for gem objects
- SI UVD fix
- SI DPM fixes
- Misc code cleanups
- RAS updates
- GPUVM debugfs fixes
- Cyan Skillfish updates
- UserQ updates
- OEM i2c fix
- SMU 13.0.x updates
- DPCD probe quirk fix
- Make vbios build number available in sysfs
- HDCP updates
- Brightness curve fixes
- eDP updates
- Vblank fixes
- DCN 3.5 PG fix
- PBN calcution fix

amdkfd:
- Add CRIU support for gem objects
- Flexible array fix
- P2P topology fix
- APU memlimit fixes
- Misc code cleanups

UAPI:
- Add CRIU support for gem objects
Proposed userspace: https://github.com/checkpoint-restore/criu/pull/2613

radeon:
- Use dev_warn_once() in CS parsers

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250909161928.942785-1-alexander.deucher@amd.com

Dave Airlie cf99b26d 8d04ea1a

+1811 -1028
+2 -1
drivers/gpu/drm/amd/amdgpu/Makefile
··· 84 84 vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \ 85 85 nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ 86 86 sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ 87 - nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o 87 + nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ 88 + cyan_skillfish_reg_init.o 88 89 89 90 # add DF block 90 91 amdgpu-y += \
+5 -3
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 1149 1149 /* for userq and VM fences */ 1150 1150 struct amdgpu_seq64 seq64; 1151 1151 1152 - /* KFD */ 1153 - struct amdgpu_kfd_dev kfd; 1154 - 1155 1152 /* UMC */ 1156 1153 struct amdgpu_umc umc; 1157 1154 ··· 1311 1314 struct mutex userq_mutex; 1312 1315 bool userq_halt_for_enforce_isolation; 1313 1316 struct amdgpu_uid *uid_info; 1317 + 1318 + /* KFD 1319 + * Must be last --ends in a flexible-array member. 1320 + */ 1321 + struct amdgpu_kfd_dev kfd; 1314 1322 }; 1315 1323 1316 1324 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
+5 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
··· 107 107 bool init_complete; 108 108 struct work_struct reset_work; 109 109 110 - /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */ 111 - struct dev_pagemap pgmap; 112 - 113 110 /* Client for KFD BO GEM handle allocations */ 114 111 struct drm_client_dev client; 112 + 113 + /* HMM page migration MEMORY_DEVICE_PRIVATE mapping 114 + * Must be last --ends in a flexible-array member. 115 + */ 116 + struct dev_pagemap pgmap; 115 117 }; 116 118 117 119 enum kgd_engine_type {
+32 -12
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 213 213 spin_lock(&kfd_mem_limit.mem_limit_lock); 214 214 215 215 if (kfd_mem_limit.system_mem_used + system_mem_needed > 216 - kfd_mem_limit.max_system_mem_limit) 216 + kfd_mem_limit.max_system_mem_limit) { 217 217 pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); 218 + if (!no_system_mem_limit) { 219 + ret = -ENOMEM; 220 + goto release; 221 + } 222 + } 218 223 219 - if ((kfd_mem_limit.system_mem_used + system_mem_needed > 220 - kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) || 221 - (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 222 - kfd_mem_limit.max_ttm_mem_limit) || 223 - (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > 224 - vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) { 224 + if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 225 + kfd_mem_limit.max_ttm_mem_limit) { 225 226 ret = -ENOMEM; 226 227 goto release; 228 + } 229 + 230 + /*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with 231 + * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip 232 + * VRAM check since ttm_mem_limit check already cover this allocation 233 + */ 234 + 235 + if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) { 236 + uint64_t vram_available = 237 + vram_size - reserved_for_pt - reserved_for_ras - 238 + atomic64_read(&adev->vram_pin_size); 239 + if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) { 240 + ret = -ENOMEM; 241 + goto release; 242 + } 227 243 } 228 244 229 245 /* Update memory accounting by decreasing available system ··· 1643 1627 uint64_t vram_available, system_mem_available, ttm_mem_available; 1644 1628 1645 1629 spin_lock(&kfd_mem_limit.mem_limit_lock); 1646 - vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1647 - - adev->kfd.vram_used_aligned[xcp_id] 1648 - - atomic64_read(&adev->vram_pin_size) 1649 - - reserved_for_pt 1650 - - reserved_for_ras; 1630 + if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu) 1631 + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1632 + - adev->kfd.vram_used_aligned[xcp_id]; 1633 + else 1634 + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) 1635 + - adev->kfd.vram_used_aligned[xcp_id] 1636 + - atomic64_read(&adev->vram_pin_size) 1637 + - reserved_for_pt 1638 + - reserved_for_ras; 1651 1639 1652 1640 if (adev->apu_prefer_gtt) { 1653 1641 system_mem_available = no_system_mem_limit ?
+30 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
··· 1816 1816 return sysfs_emit(buf, "%s\n", ctx->vbios_pn); 1817 1817 } 1818 1818 1819 + static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev, 1820 + struct device_attribute *attr, 1821 + char *buf) 1822 + { 1823 + struct drm_device *ddev = dev_get_drvdata(dev); 1824 + struct amdgpu_device *adev = drm_to_adev(ddev); 1825 + struct atom_context *ctx = adev->mode_info.atom_context; 1826 + 1827 + return sysfs_emit(buf, "%s\n", ctx->build_num); 1828 + } 1829 + 1819 1830 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, 1820 1831 NULL); 1832 + static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); 1821 1833 1822 1834 static struct attribute *amdgpu_vbios_version_attrs[] = { 1823 - &dev_attr_vbios_version.attr, 1824 - NULL 1835 + &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL 1825 1836 }; 1826 1837 1838 + static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj, 1839 + struct attribute *attr, 1840 + int index) 1841 + { 1842 + struct device *dev = kobj_to_dev(kobj); 1843 + struct drm_device *ddev = dev_get_drvdata(dev); 1844 + struct amdgpu_device *adev = drm_to_adev(ddev); 1845 + struct atom_context *ctx = adev->mode_info.atom_context; 1846 + 1847 + if (attr == &dev_attr_vbios_build.attr && !strlen(ctx->build_num)) 1848 + return 0; 1849 + 1850 + return attr->mode; 1851 + } 1852 + 1827 1853 const struct attribute_group amdgpu_vbios_version_attr_group = { 1828 - .attrs = amdgpu_vbios_version_attrs 1854 + .attrs = amdgpu_vbios_version_attrs, 1855 + .is_visible = amdgpu_vbios_version_attrs_is_visible, 1829 1856 }; 1830 1857 1831 1858 int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev)
+12 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
··· 1196 1196 } 1197 1197 1198 1198 /** 1199 - * Returns the maximum supported HDMI (TMDS) pixel clock in KHz. 1199 + * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock 1200 + * @adev: pointer to amdgpu_device 1201 + * 1202 + * Return: maximum supported HDMI (TMDS) pixel clock in KHz. 1200 1203 */ 1201 1204 static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) 1202 1205 { ··· 1212 1209 } 1213 1210 1214 1211 /** 1215 - * Validates the given display mode on DVI and HDMI connectors, 1216 - * including analog signals on DVI-I. 1212 + * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors 1213 + * @connector: DRM connector to validate the mode on 1214 + * @mode: display mode to validate 1215 + * 1216 + * Validate the given display mode on DVI and HDMI connectors, including 1217 + * analog signals on DVI-I. 1218 + * 1219 + * Return: drm_mode_status indicating whether the mode is valid. 1217 1220 */ 1218 1221 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1219 1222 const struct drm_display_mode *mode)
+4 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
··· 68 68 hdr->error_severity = sev; 69 69 70 70 hdr->valid_bits.platform_id = 1; 71 - hdr->valid_bits.partition_id = 1; 72 71 hdr->valid_bits.timestamp = 1; 73 72 74 73 amdgpu_cper_get_timestamp(&hdr->timestamp); ··· 173 174 struct cper_sec_nonstd_err *section; 174 175 bool poison; 175 176 176 - poison = (sev == CPER_SEV_NON_FATAL_CORRECTED) ? false : true; 177 + poison = sev != CPER_SEV_NON_FATAL_CORRECTED; 177 178 section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); 178 179 section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + 179 180 NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); ··· 219 220 section->hdr.valid_bits.err_context_cnt = 1; 220 221 221 222 section->info.error_type = RUNTIME; 223 + section->info.valid_bits.ms_chk = 1; 222 224 section->info.ms_chk_bits.err_type_valid = 1; 225 + section->info.ms_chk_bits.err_type = 1; 226 + section->info.ms_chk_bits.pcc = 1; 223 227 section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; 224 228 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); 225 229
+7 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
··· 2136 2136 struct drm_file *file; 2137 2137 struct amdgpu_fpriv *fpriv; 2138 2138 struct amdgpu_bo *root_bo; 2139 + struct amdgpu_device *adev; 2139 2140 int r; 2140 2141 2141 2142 file = m->private; 2142 2143 if (!file) 2143 2144 return -EINVAL; 2144 2145 2146 + adev = drm_to_adev(file->minor->dev); 2145 2147 fpriv = file->driver_priv; 2146 2148 if (!fpriv || !fpriv->vm.root.bo) 2147 2149 return -ENODEV; ··· 2155 2153 return -EINVAL; 2156 2154 } 2157 2155 2158 - seq_printf(m, "gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(fpriv->vm.root.bo)); 2156 + seq_printf(m, "pd_address: 0x%llx\n", amdgpu_gmc_pd_addr(fpriv->vm.root.bo)); 2157 + seq_printf(m, "max_pfn: 0x%llx\n", adev->vm_manager.max_pfn); 2158 + seq_printf(m, "num_level: 0x%x\n", adev->vm_manager.num_level); 2159 + seq_printf(m, "block_size: 0x%x\n", adev->vm_manager.block_size); 2160 + seq_printf(m, "fragment_size: 0x%x\n", adev->vm_manager.fragment_size); 2159 2161 2160 2162 amdgpu_bo_unreserve(root_bo); 2161 2163 amdgpu_bo_unref(&root_bo);
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 95 95 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); 96 96 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); 97 97 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); 98 + MODULE_FIRMWARE("amdgpu/cyan_skillfish_gpu_info.bin"); 98 99 99 100 #define AMDGPU_RESUME_MS 2000 100 101 #define AMDGPU_MAX_RETRY_LIMIT 2 ··· 2629 2628 if (adev->mman.discovery_bin) 2630 2629 return 0; 2631 2630 chip_name = "navi12"; 2631 + break; 2632 + case CHIP_CYAN_SKILLFISH: 2633 + chip_name = "cyan_skillfish"; 2632 2634 break; 2633 2635 } 2634 2636
+34 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
··· 2124 2124 case IP_VERSION(11, 0, 5): 2125 2125 case IP_VERSION(11, 0, 9): 2126 2126 case IP_VERSION(11, 0, 7): 2127 - case IP_VERSION(11, 0, 8): 2128 2127 case IP_VERSION(11, 0, 11): 2129 2128 case IP_VERSION(11, 0, 12): 2130 2129 case IP_VERSION(11, 0, 13): 2131 2130 case IP_VERSION(11, 5, 0): 2132 2131 case IP_VERSION(11, 5, 2): 2133 2132 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2133 + break; 2134 + case IP_VERSION(11, 0, 8): 2135 + if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2136 + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2134 2137 break; 2135 2138 case IP_VERSION(12, 0, 0): 2136 2139 case IP_VERSION(12, 0, 1): ··· 2748 2745 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 2749 2746 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 2750 2747 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 2748 + break; 2749 + case CHIP_CYAN_SKILLFISH: 2750 + if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 2751 + r = amdgpu_discovery_reg_base_init(adev); 2752 + if (r) 2753 + return -EINVAL; 2754 + 2755 + amdgpu_discovery_harvest_ip(adev); 2756 + amdgpu_discovery_get_gfx_info(adev); 2757 + amdgpu_discovery_get_mall_info(adev); 2758 + amdgpu_discovery_get_vcn_info(adev); 2759 + } else { 2760 + cyan_skillfish_reg_base_init(adev); 2761 + adev->sdma.num_instances = 2; 2762 + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2763 + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 2764 + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 2765 + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 2766 + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 2767 + adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 2768 + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 2769 + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 2770 + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 2771 + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 2772 + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 2773 + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 2774 + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 2775 + adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 2776 + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 2777 + } 2751 2778 break; 2752 2779 default: 2753 2780 r = amdgpu_discovery_reg_base_init(adev);
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2172 2172 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2173 2173 2174 2174 /* CYAN_SKILLFISH */ 2175 + {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2176 + {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2177 + {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2178 + {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2179 + {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2175 2180 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2176 2181 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2177 2182 ··· 3056 3051 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3057 3052 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3058 3053 DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3054 + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 3059 3055 }; 3060 3056 3061 3057 static const struct drm_driver amdgpu_kms_driver = {
+158 -23
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
··· 442 442 int r; 443 443 444 444 /* reject invalid gem flags */ 445 - if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 446 - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 447 - AMDGPU_GEM_CREATE_CPU_GTT_USWC | 448 - AMDGPU_GEM_CREATE_VRAM_CLEARED | 449 - AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 450 - AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 451 - AMDGPU_GEM_CREATE_ENCRYPTED | 452 - AMDGPU_GEM_CREATE_GFX12_DCC | 453 - AMDGPU_GEM_CREATE_DISCARDABLE)) 445 + if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK) 454 446 return -EINVAL; 455 447 456 448 /* reject invalid gem domains */ ··· 955 963 struct drm_gem_object *gobj; 956 964 struct amdgpu_vm_bo_base *base; 957 965 struct amdgpu_bo *robj; 966 + struct drm_exec exec; 967 + struct amdgpu_fpriv *fpriv = filp->driver_priv; 958 968 int r; 969 + 970 + if (args->padding) 971 + return -EINVAL; 959 972 960 973 gobj = drm_gem_object_lookup(filp, args->handle); 961 974 if (!gobj) ··· 968 971 969 972 robj = gem_to_amdgpu_bo(gobj); 970 973 971 - r = amdgpu_bo_reserve(robj, false); 972 - if (unlikely(r)) 973 - goto out; 974 + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | 975 + DRM_EXEC_IGNORE_DUPLICATES, 0); 976 + drm_exec_until_all_locked(&exec) { 977 + r = drm_exec_lock_obj(&exec, gobj); 978 + drm_exec_retry_on_contention(&exec); 979 + if (r) 980 + goto out_exec; 981 + 982 + if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) { 983 + r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); 984 + drm_exec_retry_on_contention(&exec); 985 + if (r) 986 + goto out_exec; 987 + } 988 + } 974 989 975 990 switch (args->op) { 976 991 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { ··· 993 984 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 994 985 info.domains = robj->preferred_domains; 995 986 info.domain_flags = robj->flags; 996 - amdgpu_bo_unreserve(robj); 987 + drm_exec_fini(&exec); 997 988 if (copy_to_user(out, &info, sizeof(info))) 998 989 r = -EFAULT; 999 990 break; ··· 1002 993 if (drm_gem_is_imported(&robj->tbo.base) && 1003 994 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 1004 995 r = -EINVAL; 1005 - amdgpu_bo_unreserve(robj); 1006 - break; 996 + goto out_exec; 1007 997 } 1008 998 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 1009 999 r = -EPERM; 1010 - amdgpu_bo_unreserve(robj); 1011 - break; 1000 + goto out_exec; 1012 1001 } 1013 1002 for (base = robj->vm_bo; base; base = base->next) 1014 1003 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 1015 1004 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 1016 1005 r = -EINVAL; 1017 - amdgpu_bo_unreserve(robj); 1018 - goto out; 1006 + goto out_exec; 1019 1007 } 1020 1008 1021 1009 ··· 1025 1019 1026 1020 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 1027 1021 amdgpu_vm_bo_invalidate(robj, true); 1028 - 1029 - amdgpu_bo_unreserve(robj); 1022 + drm_exec_fini(&exec); 1030 1023 break; 1024 + case AMDGPU_GEM_OP_GET_MAPPING_INFO: { 1025 + struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&fpriv->vm, robj); 1026 + struct drm_amdgpu_gem_vm_entry *vm_entries; 1027 + struct amdgpu_bo_va_mapping *mapping; 1028 + int num_mappings = 0; 1029 + /* 1030 + * num_entries is set as an input to the size of the user-allocated array of 1031 + * drm_amdgpu_gem_vm_entry stored at args->value. 1032 + * num_entries is sent back as output as the number of mappings the bo has. 1033 + * If that number is larger than the size of the array, the ioctl must 1034 + * be retried. 1035 + */ 1036 + vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL); 1037 + if (!vm_entries) 1038 + return -ENOMEM; 1039 + 1040 + amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) { 1041 + if (num_mappings < args->num_entries) { 1042 + vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1043 + vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1044 + vm_entries[num_mappings].offset = mapping->offset; 1045 + vm_entries[num_mappings].flags = mapping->flags; 1046 + } 1047 + num_mappings += 1; 1048 + } 1049 + 1050 + amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) { 1051 + if (num_mappings < args->num_entries) { 1052 + vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; 1053 + vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; 1054 + vm_entries[num_mappings].offset = mapping->offset; 1055 + vm_entries[num_mappings].flags = mapping->flags; 1056 + } 1057 + num_mappings += 1; 1058 + } 1059 + 1060 + drm_exec_fini(&exec); 1061 + 1062 + if (num_mappings > 0 && num_mappings <= args->num_entries) 1063 + if (copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries))) 1064 + r = -EFAULT; 1065 + 1066 + args->num_entries = num_mappings; 1067 + 1068 + kvfree(vm_entries); 1069 + break; 1070 + } 1031 1071 default: 1032 - amdgpu_bo_unreserve(robj); 1072 + drm_exec_fini(&exec); 1033 1073 r = -EINVAL; 1034 1074 } 1035 1075 1036 - out: 1037 1076 drm_gem_object_put(gobj); 1038 1077 return r; 1078 + out_exec: 1079 + drm_exec_fini(&exec); 1080 + drm_gem_object_put(gobj); 1081 + return r; 1082 + } 1083 + 1084 + /** 1085 + * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects 1086 + * 1087 + * @dev: drm device pointer 1088 + * @data: drm_amdgpu_gem_list_handles 1089 + * @filp: drm file pointer 1090 + * 1091 + * num_entries is set as an input to the size of the entries array. 1092 + * num_entries is sent back as output as the number of bos in the process. 1093 + * If that number is larger than the size of the array, the ioctl must 1094 + * be retried. 1095 + * 1096 + * Returns: 1097 + * 0 for success, -errno for errors. 1098 + */ 1099 + int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, 1100 + struct drm_file *filp) 1101 + { 1102 + struct drm_amdgpu_gem_list_handles *args = data; 1103 + struct drm_amdgpu_gem_list_handles_entry *bo_entries; 1104 + struct drm_gem_object *gobj; 1105 + int id, ret = 0; 1106 + int bo_index = 0; 1107 + int num_bos = 0; 1108 + 1109 + spin_lock(&filp->table_lock); 1110 + idr_for_each_entry(&filp->object_idr, gobj, id) 1111 + num_bos += 1; 1112 + spin_unlock(&filp->table_lock); 1113 + 1114 + if (args->num_entries < num_bos) { 1115 + args->num_entries = num_bos; 1116 + return 0; 1117 + } 1118 + 1119 + if (num_bos == 0) { 1120 + args->num_entries = 0; 1121 + return 0; 1122 + } 1123 + 1124 + bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL); 1125 + if (!bo_entries) 1126 + return -ENOMEM; 1127 + 1128 + spin_lock(&filp->table_lock); 1129 + idr_for_each_entry(&filp->object_idr, gobj, id) { 1130 + struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 1131 + struct drm_amdgpu_gem_list_handles_entry *bo_entry; 1132 + 1133 + if (bo_index >= num_bos) { 1134 + ret = -EAGAIN; 1135 + break; 1136 + } 1137 + 1138 + bo_entry = &bo_entries[bo_index]; 1139 + 1140 + bo_entry->size = amdgpu_bo_size(bo); 1141 + bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK; 1142 + bo_entry->preferred_domains = bo->preferred_domains; 1143 + bo_entry->gem_handle = id; 1144 + bo_entry->alignment = bo->tbo.page_alignment; 1145 + 1146 + if (bo->tbo.base.import_attach) 1147 + bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT; 1148 + 1149 + bo_index += 1; 1150 + } 1151 + spin_unlock(&filp->table_lock); 1152 + 1153 + args->num_entries = bo_index; 1154 + 1155 + if (!ret) 1156 + if (copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries))) 1157 + ret = -EFAULT; 1158 + 1159 + kvfree(bo_entries); 1160 + 1161 + return ret; 1039 1162 } 1040 1163 1041 1164 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
+16
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
··· 67 67 struct drm_file *filp); 68 68 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 69 69 struct drm_file *filp); 70 + int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, 71 + struct drm_file *filp); 70 72 71 73 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 72 74 struct drm_file *filp); 75 + 76 + #define AMDGPU_GEM_CREATE_SETTABLE_MASK (AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ 77 + AMDGPU_GEM_CREATE_NO_CPU_ACCESS | \ 78 + AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ 79 + AMDGPU_GEM_CREATE_VRAM_CLEARED | \ 80 + AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | \ 81 + AMDGPU_GEM_CREATE_EXPLICIT_SYNC | \ 82 + AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \ 83 + AMDGPU_GEM_CREATE_ENCRYPTED | \ 84 + AMDGPU_GEM_CREATE_GFX12_DCC | \ 85 + AMDGPU_GEM_CREATE_DISCARDABLE | \ 86 + AMDGPU_GEM_CREATE_COHERENT | \ 87 + AMDGPU_GEM_CREATE_UNCACHED | \ 88 + AMDGPU_GEM_CREATE_EXT_COHERENT) 73 89 74 90 #endif
+65
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
··· 191 191 if (r) 192 192 goto error_doorbell; 193 193 194 + if (adev->mes.hung_queue_db_array_size) { 195 + r = amdgpu_bo_create_kernel(adev, 196 + adev->mes.hung_queue_db_array_size * sizeof(u32), 197 + PAGE_SIZE, 198 + AMDGPU_GEM_DOMAIN_GTT, 199 + &adev->mes.hung_queue_db_array_gpu_obj, 200 + &adev->mes.hung_queue_db_array_gpu_addr, 201 + &adev->mes.hung_queue_db_array_cpu_addr); 202 + if (r) { 203 + dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); 204 + goto error_doorbell; 205 + } 206 + } 207 + 194 208 return 0; 195 209 196 210 error_doorbell: ··· 229 215 void amdgpu_mes_fini(struct amdgpu_device *adev) 230 216 { 231 217 int i; 218 + 219 + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj, 220 + &adev->mes.hung_queue_db_array_gpu_addr, 221 + &adev->mes.hung_queue_db_array_cpu_addr); 232 222 233 223 amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, 234 224 &adev->mes.event_log_gpu_addr, ··· 380 362 amdgpu_mes_unlock(&adev->mes); 381 363 if (r) 382 364 dev_err(adev->dev, "failed to reset legacy queue\n"); 365 + 366 + return r; 367 + } 368 + 369 + int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev) 370 + { 371 + return adev->mes.hung_queue_db_array_size; 372 + } 373 + 374 + int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 375 + int queue_type, 376 + bool detect_only, 377 + unsigned int *hung_db_num, 378 + u32 *hung_db_array) 379 + 380 + { 381 + struct mes_detect_and_reset_queue_input input; 382 + u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr; 383 + int r, i; 384 + 385 + if (!hung_db_num || !hung_db_array) 386 + return -EINVAL; 387 + 388 + if ((queue_type != AMDGPU_RING_TYPE_GFX) && 389 + (queue_type != AMDGPU_RING_TYPE_COMPUTE) && 390 + (queue_type != AMDGPU_RING_TYPE_SDMA)) 391 + return -EINVAL; 392 + 393 + /* Clear the doorbell array before detection */ 394 + memset(adev->mes.hung_queue_db_array_cpu_addr, 0, 395 + adev->mes.hung_queue_db_array_size * sizeof(u32)); 396 + input.queue_type = queue_type; 397 + input.detect_only = detect_only; 398 + 399 + r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes, 400 + &input); 401 + if (r) { 402 + dev_err(adev->dev, "failed to detect and reset\n"); 403 + } else { 404 + *hung_db_num = 0; 405 + for (i = 0; i < adev->mes.hung_queue_db_array_size; i++) { 406 + if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { 407 + hung_db_array[i] = db_array[i]; 408 + *hung_db_num += 1; 409 + } 410 + } 411 + } 383 412 384 413 return r; 385 414 }
+21
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
··· 41 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 + #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 44 45 45 46 enum amdgpu_mes_priority_level { 46 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, ··· 148 147 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 149 148 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 150 149 150 + int hung_queue_db_array_size; 151 + struct amdgpu_bo *hung_queue_db_array_gpu_obj; 152 + uint64_t hung_queue_db_array_gpu_addr; 153 + void *hung_queue_db_array_cpu_addr; 151 154 }; 152 155 153 156 struct amdgpu_mes_gang { ··· 285 280 bool is_kq; 286 281 }; 287 282 283 + struct mes_detect_and_reset_queue_input { 284 + uint32_t queue_type; 285 + bool detect_only; 286 + }; 287 + 288 288 struct mes_inv_tlbs_pasid_input { 289 289 uint32_t xcc_id; 290 290 uint16_t pasid; ··· 385 375 int (*reset_hw_queue)(struct amdgpu_mes *mes, 386 376 struct mes_reset_queue_input *input); 387 377 378 + int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 379 + struct mes_detect_and_reset_queue_input *input); 380 + 381 + 388 382 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 389 383 struct mes_inv_tlbs_pasid_input *input); 390 384 }; ··· 413 399 struct amdgpu_ring *ring, 414 400 unsigned int vmid, 415 401 bool use_mmio); 402 + 403 + int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 404 + int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 405 + int queue_type, 406 + bool detect_only, 407 + unsigned int *hung_db_num, 408 + u32 *hung_db_array); 416 409 417 410 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 418 411 int amdgpu_mes_wreg(struct amdgpu_device *adev,
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
··· 496 496 struct drm_connector *connector; 497 497 /* for dpm */ 498 498 u32 line_time; 499 - u32 wm_low; 500 - u32 wm_high; 501 499 u32 lb_vblank_lead_lines; 502 500 struct drm_display_mode hw_mode; 503 501 /* for virtual dce */
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
··· 448 448 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 449 449 if (!psp->cmd) { 450 450 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); 451 - ret = -ENOMEM; 451 + return -ENOMEM; 452 452 } 453 453 454 454 adev->psp.xgmi_context.supports_extended_data =
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
··· 340 340 case AMDGPU_RESET_SRC_USER: 341 341 strscpy(buf, "user trigger", len); 342 342 break; 343 + case AMDGPU_RESET_SRC_USERQ: 344 + strscpy(buf, "user queue trigger", len); 345 + break; 343 346 default: 344 347 strscpy(buf, "unknown", len); 345 348 }
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h
··· 43 43 AMDGPU_RESET_SRC_MES, 44 44 AMDGPU_RESET_SRC_HWS, 45 45 AMDGPU_RESET_SRC_USER, 46 + AMDGPU_RESET_SRC_USERQ, 46 47 }; 47 48 48 49 struct amdgpu_reset_context {
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
··· 364 364 return -EINVAL; 365 365 } 366 366 367 - seq_printf(m, "queue_type %d\n", queue->queue_type); 367 + seq_printf(m, "queue_type: %d\n", queue->queue_type); 368 368 seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); 369 369 370 370 amdgpu_bo_unreserve(bo);
+6
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
··· 78 78 struct amdgpu_usermode_queue *queue); 79 79 int (*map)(struct amdgpu_userq_mgr *uq_mgr, 80 80 struct amdgpu_usermode_queue *queue); 81 + int (*preempt)(struct amdgpu_userq_mgr *uq_mgr, 82 + struct amdgpu_usermode_queue *queue); 83 + int (*restore)(struct amdgpu_userq_mgr *uq_mgr, 84 + struct amdgpu_usermode_queue *queue); 85 + int (*detect_and_reset)(struct amdgpu_device *adev, 86 + int queue_type); 81 87 }; 82 88 83 89 /* Usermode queues for gfx */
+42
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
··· 67 67 return le64_to_cpu(*fence_drv->cpu_addr); 68 68 } 69 69 70 + static void 71 + amdgpu_userq_fence_write(struct amdgpu_userq_fence_driver *fence_drv, 72 + u64 seq) 73 + { 74 + if (fence_drv->cpu_addr) 75 + *fence_drv->cpu_addr = cpu_to_le64(seq); 76 + } 77 + 70 78 int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, 71 79 struct amdgpu_usermode_queue *userq) 72 80 { ··· 414 406 static void amdgpu_userq_fence_cleanup(struct dma_fence *fence) 415 407 { 416 408 dma_fence_put(fence); 409 + } 410 + 411 + static void 412 + amdgpu_userq_fence_driver_set_error(struct amdgpu_userq_fence *fence, 413 + int error) 414 + { 415 + struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; 416 + unsigned long flags; 417 + struct dma_fence *f; 418 + 419 + spin_lock_irqsave(&fence_drv->fence_list_lock, flags); 420 + 421 + f = rcu_dereference_protected(&fence->base, 422 + lockdep_is_held(&fence_drv->fence_list_lock)); 423 + if (f && !dma_fence_is_signaled_locked(f)) 424 + dma_fence_set_error(f, error); 425 + spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); 426 + } 427 + 428 + void 429 + amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq) 430 + { 431 + struct dma_fence *f = userq->last_fence; 432 + 433 + if (f) { 434 + struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f); 435 + struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; 436 + u64 wptr = fence->base.seqno; 437 + 438 + amdgpu_userq_fence_driver_set_error(fence, -ECANCELED); 439 + amdgpu_userq_fence_write(fence_drv, wptr); 440 + amdgpu_userq_fence_driver_process(fence_drv); 441 + 442 + } 417 443 } 418 444 419 445 int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
··· 67 67 struct amdgpu_usermode_queue *userq); 68 68 void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); 69 69 void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); 70 + void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq); 70 71 void amdgpu_userq_fence_driver_destroy(struct kref *ref); 71 72 int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, 72 73 struct drm_file *filp);
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
··· 670 670 void amdgpu_vm_print_task_info(struct amdgpu_device *adev, 671 671 struct amdgpu_task_info *task_info); 672 672 673 + #define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \ 674 + list_for_each_entry(mapping, &(bo_va)->valids, list) 675 + #define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \ 676 + list_for_each_entry(mapping, &(bo_va)->invalids, list) 677 + 673 678 #endif
+22
drivers/gpu/drm/amd/amdgpu/atom.c
··· 1494 1494 } 1495 1495 } 1496 1496 1497 + static void atom_get_vbios_build(struct atom_context *ctx) 1498 + { 1499 + unsigned char *atom_rom_hdr; 1500 + unsigned char *str; 1501 + uint16_t base; 1502 + 1503 + base = CU16(ATOM_ROM_TABLE_PTR); 1504 + atom_rom_hdr = CSTR(base); 1505 + 1506 + str = CSTR(CU16(base + ATOM_ROM_CFG_PTR)); 1507 + /* Skip config string */ 1508 + while (str < atom_rom_hdr && *str++) 1509 + ; 1510 + /* Skip change list string */ 1511 + while (str < atom_rom_hdr && *str++) 1512 + ; 1513 + 1514 + if ((str + STRLEN_NORMAL) < atom_rom_hdr) 1515 + strscpy(ctx->build_num, str, STRLEN_NORMAL); 1516 + } 1517 + 1497 1518 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1498 1519 { 1499 1520 int base; ··· 1575 1554 atom_get_vbios_pn(ctx); 1576 1555 atom_get_vbios_date(ctx); 1577 1556 atom_get_vbios_version(ctx); 1557 + atom_get_vbios_build(ctx); 1578 1558 1579 1559 return ctx; 1580 1560 }
+2
drivers/gpu/drm/amd/amdgpu/atom.h
··· 37 37 #define ATOM_ROM_MAGIC "ATOM" 38 38 #define ATOM_ROM_MAGIC_PTR 4 39 39 40 + #define ATOM_ROM_CFG_PTR 0xC 40 41 #define ATOM_ROM_MSG_PTR 0x10 41 42 #define ATOM_ROM_CMD_PTR 0x1E 42 43 #define ATOM_ROM_DATA_PTR 0x20 ··· 152 151 uint32_t version; 153 152 uint8_t vbios_ver_str[STRLEN_NORMAL]; 154 153 uint8_t date[STRLEN_NORMAL]; 154 + uint8_t build_num[STRLEN_NORMAL]; 155 155 }; 156 156 157 157 extern int amdgpu_atom_debug;
+56
drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Copyright 2018 Advanced Micro Devices, Inc. 4 + * 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 + * copy of this software and associated documentation files (the "Software"), 7 + * to deal in the Software without restriction, including without limitation 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 + * Software is furnished to do so, subject to the following conditions: 11 + * 12 + * The above copyright notice and this permission notice shall be included in 13 + * all copies or substantial portions of the Software. 14 + * 15 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 + * OTHER DEALINGS IN THE SOFTWARE. 22 + * 23 + */ 24 + #include "amdgpu.h" 25 + #include "nv.h" 26 + 27 + #include "soc15_common.h" 28 + #include "soc15_hw_ip.h" 29 + #include "cyan_skillfish_ip_offset.h" 30 + 31 + int cyan_skillfish_reg_base_init(struct amdgpu_device *adev) 32 + { 33 + /* HW has more IP blocks, only initialized the blocke needed by driver */ 34 + uint32_t i; 35 + 36 + adev->gfx.xcc_mask = 1; 37 + for (i = 0 ; i < MAX_INSTANCE ; ++i) { 38 + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 39 + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 40 + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 41 + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 42 + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 43 + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 44 + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 45 + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); 46 + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); 47 + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); 48 + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); 49 + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 50 + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 51 + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); 52 + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); 53 + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); 54 + } 55 + return 0; 56 + }
+1 -2
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 1141 1141 1142 1142 /* save values for DPM */ 1143 1143 amdgpu_crtc->line_time = line_time; 1144 - amdgpu_crtc->wm_high = latency_watermark_a; 1145 - amdgpu_crtc->wm_low = latency_watermark_b; 1144 + 1146 1145 /* Save number of lines the linebuffer leads before the scanout */ 1147 1146 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1148 1147 }
+1 -2
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 1173 1173 1174 1174 /* save values for DPM */ 1175 1175 amdgpu_crtc->line_time = line_time; 1176 - amdgpu_crtc->wm_high = latency_watermark_a; 1177 - amdgpu_crtc->wm_low = latency_watermark_b; 1176 + 1178 1177 /* Save number of lines the linebuffer leads before the scanout */ 1179 1178 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1180 1179 }
-1
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 1034 1034 1035 1035 /* save values for DPM */ 1036 1036 amdgpu_crtc->line_time = line_time; 1037 - amdgpu_crtc->wm_high = latency_watermark_a; 1038 1037 1039 1038 /* Save number of lines the linebuffer leads before the scanout */ 1040 1039 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
+1 -2
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 1096 1096 1097 1097 /* save values for DPM */ 1098 1098 amdgpu_crtc->line_time = line_time; 1099 - amdgpu_crtc->wm_high = latency_watermark_a; 1100 - amdgpu_crtc->wm_low = latency_watermark_b; 1099 + 1101 1100 /* Save number of lines the linebuffer leads before the scanout */ 1102 1101 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1103 1102 }
+1 -2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 4643 4643 4644 4644 amdgpu_device_flush_hdp(adev, NULL); 4645 4645 4646 - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 4647 - false : true; 4646 + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 4648 4647 4649 4648 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 4650 4649 /* TODO investigate why this and the hdp flush above is needed,
+1 -2
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 3524 3524 3525 3525 amdgpu_device_flush_hdp(adev, NULL); 3526 3526 3527 - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 3528 - false : true; 3527 + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 3529 3528 3530 3529 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 3531 3530 /* TODO investigate why this and the hdp flush above is needed,
+1 -2
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
··· 963 963 /* Flush HDP after it is initialized */ 964 964 amdgpu_device_flush_hdp(adev, NULL); 965 965 966 - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 967 - false : true; 966 + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 968 967 969 968 if (!adev->in_s0ix) 970 969 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
+1 -2
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
··· 905 905 /* Flush HDP after it is initialized */ 906 906 amdgpu_device_flush_hdp(adev, NULL); 907 907 908 - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 909 - false : true; 908 + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 910 909 911 910 adev->mmhub.funcs->set_fault_enable_default(adev, value); 912 911 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
+1 -2
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
··· 893 893 /* Flush HDP after it is initialized */ 894 894 amdgpu_device_flush_hdp(adev, NULL); 895 895 896 - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 897 - false : true; 896 + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 898 897 899 898 adev->mmhub.funcs->set_fault_enable_default(adev, value); 900 899 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0);
+1 -2
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
··· 587 587 /* use gpu virtual address for ih ring 588 588 * until ih_checken is programmed to allow 589 589 * use bus address for ih ring by psp bl */ 590 - use_bus_addr = 591 - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 590 + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; 592 591 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); 593 592 if (r) 594 593 return r;
+1 -2
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
··· 562 562 /* use gpu virtual address for ih ring 563 563 * until ih_checken is programmed to allow 564 564 * use bus address for ih ring by psp bl */ 565 - use_bus_addr = 566 - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 565 + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; 567 566 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 568 567 if (r) 569 568 return r;
+1 -2
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
··· 552 552 /* use gpu virtual address for ih ring 553 553 * until ih_checken is programmed to allow 554 554 * use bus address for ih ring by psp bl */ 555 - use_bus_addr = 556 - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 555 + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; 557 556 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 558 557 if (r) 559 558 return r;
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
··· 686 686 enum amd_clockgating_state state) 687 687 { 688 688 struct amdgpu_device *adev = ip_block->adev; 689 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 689 + bool enable = state == AMD_CG_STATE_GATE; 690 690 int i; 691 691 692 692 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
··· 584 584 enum amd_clockgating_state state) 585 585 { 586 586 struct amdgpu_device *adev = ip_block->adev; 587 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 587 + bool enable = state == AMD_CG_STATE_GATE; 588 588 589 589 if (enable) { 590 590 if (!jpeg_v5_0_0_is_idle(ip_block))
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
··· 697 697 enum amd_clockgating_state state) 698 698 { 699 699 struct amdgpu_device *adev = ip_block->adev; 700 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 700 + bool enable = state == AMD_CG_STATE_GATE; 701 701 702 702 int i; 703 703
+49
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
··· 21 21 * OTHER DEALINGS IN THE SOFTWARE. 22 22 * 23 23 */ 24 + #include <drm/drm_drv.h> 24 25 #include "amdgpu.h" 25 26 #include "amdgpu_gfx.h" 26 27 #include "mes_userqueue.h" ··· 199 198 return 0; 200 199 } 201 200 201 + static int mes_userq_detect_and_reset(struct amdgpu_device *adev, 202 + int queue_type) 203 + { 204 + int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 205 + struct mes_detect_and_reset_queue_input input; 206 + struct amdgpu_usermode_queue *queue; 207 + struct amdgpu_userq_mgr *uqm, *tmp; 208 + unsigned int hung_db_num = 0; 209 + int queue_id, r, i; 210 + u32 db_array[4]; 211 + 212 + if (db_array_size > 4) { 213 + dev_err(adev->dev, "DB array size (%d vs 4) too small\n", 214 + db_array_size); 215 + return -EINVAL; 216 + } 217 + 218 + memset(&input, 0x0, sizeof(struct mes_detect_and_reset_queue_input)); 219 + 220 + input.queue_type = queue_type; 221 + 222 + amdgpu_mes_lock(&adev->mes); 223 + r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, 224 + &hung_db_num, db_array); 225 + amdgpu_mes_unlock(&adev->mes); 226 + if (r) { 227 + dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); 228 + } else if (hung_db_num) { 229 + list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { 230 + idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { 231 + if (queue->queue_type == queue_type) { 232 + for (i = 0; i < hung_db_num; i++) { 233 + if (queue->doorbell_index == db_array[i]) { 234 + queue->state = AMDGPU_USERQ_STATE_HUNG; 235 + atomic_inc(&adev->gpu_reset_counter); 236 + amdgpu_userq_fence_driver_force_completion(queue); 237 + drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 238 + } 239 + } 240 + } 241 + } 242 + } 243 + } 244 + 245 + return r; 246 + } 247 + 202 248 static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, 203 249 struct drm_amdgpu_userq_in *args_in, 204 250 struct amdgpu_usermode_queue *queue) ··· 400 352 .mqd_destroy = mes_userq_mqd_destroy, 401 353 .unmap = mes_userq_unmap, 402 354 .map = mes_userq_map, 355 + .detect_and_reset = mes_userq_detect_and_reset, 403 356 };
+31
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
··· 66 66 #define GFX_MES_DRAM_SIZE 0x80000 67 67 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) 68 68 69 + #define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 4 70 + 69 71 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 70 72 { 71 73 struct amdgpu_device *adev = ring->adev; ··· 786 784 offsetof(union MESAPI__RESET, api_status)); 787 785 } 788 786 787 + static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 788 + struct mes_detect_and_reset_queue_input *input) 789 + { 790 + union MESAPI__RESET mes_reset_queue_pkt; 791 + 792 + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 793 + 794 + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 795 + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 796 + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 797 + 798 + mes_reset_queue_pkt.queue_type = 799 + convert_to_mes_queue_type(input->queue_type); 800 + mes_reset_queue_pkt.doorbell_offset_addr = 801 + mes->hung_queue_db_array_gpu_addr; 802 + 803 + if (input->detect_only) 804 + mes_reset_queue_pkt.hang_detect_only = 1; 805 + else 806 + mes_reset_queue_pkt.hang_detect_then_reset = 1; 807 + 808 + return mes_v11_0_submit_pkt_and_poll_completion(mes, 809 + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 810 + offsetof(union MESAPI__RESET, api_status)); 811 + } 812 + 789 813 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 790 814 .add_hw_queue = mes_v11_0_add_hw_queue, 791 815 .remove_hw_queue = mes_v11_0_remove_hw_queue, ··· 821 793 .resume_gang = mes_v11_0_resume_gang, 822 794 .misc_op = mes_v11_0_misc_op, 823 795 .reset_hw_queue = mes_v11_0_reset_hw_queue, 796 + .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, 824 797 }; 825 798 826 799 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, ··· 1714 1685 struct amdgpu_device *adev = ip_block->adev; 1715 1686 int pipe, r; 1716 1687 1688 + adev->mes.hung_queue_db_array_size = 1689 + MES11_HUNG_DB_OFFSET_ARRAY_SIZE; 1717 1690 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1718 1691 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1719 1692 continue;
+65 -4
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
··· 47 47 48 48 #define MES_EOP_SIZE 2048 49 49 50 + #define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 4 51 + 50 52 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) 51 53 { 52 54 struct amdgpu_device *adev = ring->adev; ··· 570 568 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, 571 569 struct mes_suspend_gang_input *input) 572 570 { 573 - return 0; 571 + union MESAPI__SUSPEND mes_suspend_gang_pkt; 572 + 573 + memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); 574 + 575 + mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 576 + mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; 577 + mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 578 + 579 + mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; 580 + mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; 581 + mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; 582 + mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; 583 + 584 + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 585 + &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), 586 + offsetof(union MESAPI__SUSPEND, api_status)); 574 587 } 575 588 576 589 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, 577 590 struct mes_resume_gang_input *input) 578 591 { 579 - return 0; 592 + union MESAPI__RESUME mes_resume_gang_pkt; 593 + 594 + memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); 595 + 596 + mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; 597 + mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; 598 + mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 599 + 600 + mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; 601 + mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; 602 + 603 + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 604 + &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), 605 + offsetof(union MESAPI__RESUME, api_status)); 580 606 } 581 607 582 608 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) ··· 910 880 offsetof(union MESAPI__RESET, api_status)); 911 881 } 912 882 883 + static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, 884 + struct mes_detect_and_reset_queue_input *input) 885 + { 886 + union MESAPI__RESET mes_reset_queue_pkt; 887 + 888 + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); 889 + 890 + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 891 + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; 892 + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 893 + 894 + mes_reset_queue_pkt.queue_type = 895 + convert_to_mes_queue_type(input->queue_type); 896 + mes_reset_queue_pkt.doorbell_offset_addr = 897 + mes->hung_queue_db_array_gpu_addr; 898 + 899 + if (input->detect_only) 900 + mes_reset_queue_pkt.hang_detect_only = 1; 901 + else 902 + mes_reset_queue_pkt.hang_detect_then_reset = 1; 903 + 904 + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, 905 + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), 906 + offsetof(union MESAPI__RESET, api_status)); 907 + } 908 + 913 909 static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) 914 910 { 915 911 /* ··· 955 899 struct mes_inv_tlbs_pasid_input *input) 956 900 { 957 901 union MESAPI__INV_TLBS mes_inv_tlbs; 902 + int ret; 958 903 959 904 memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); 960 905 ··· 968 911 mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; 969 912 970 913 /*convert amdgpu_mes_hub_id to mes expected hub_id */ 971 - mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 972 - if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) 914 + ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); 915 + if (ret < 0) 973 916 return -EINVAL; 917 + mes_inv_tlbs.invalidate_tlbs.hub_id = ret; 974 918 return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, 975 919 &mes_inv_tlbs, sizeof(mes_inv_tlbs), 976 920 offsetof(union MESAPI__INV_TLBS, api_status)); ··· 988 930 .misc_op = mes_v12_0_misc_op, 989 931 .reset_hw_queue = mes_v12_0_reset_hw_queue, 990 932 .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, 933 + .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, 991 934 }; 992 935 993 936 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, ··· 1894 1835 struct amdgpu_device *adev = ip_block->adev; 1895 1836 int pipe, r; 1896 1837 1838 + adev->mes.hung_queue_db_array_size = 1839 + MES12_HUNG_DB_OFFSET_ARRAY_SIZE; 1897 1840 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1898 1841 r = amdgpu_mes_init_microcode(adev, pipe); 1899 1842 if (r)
+1
drivers/gpu/drm/amd/amdgpu/nv.h
··· 31 31 void nv_grbm_select(struct amdgpu_device *adev, 32 32 u32 me, u32 pipe, u32 queue, u32 vmid); 33 33 void nv_set_virt_ops(struct amdgpu_device *adev); 34 + int cyan_skillfish_reg_base_init(struct amdgpu_device *adev); 34 35 35 36 #endif
+25 -4
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
··· 623 623 * 624 624 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 625 625 * 626 - * Initialize the hardware, boot up the VCPU and do some testing 626 + * Initialize the hardware, boot up the VCPU and do some testing. 627 + * 628 + * On SI, the UVD is meant to be used in a specific power state, 629 + * or alternatively the driver can manually enable its clock. 630 + * In amdgpu we use the dedicated UVD power state when DPM is enabled. 631 + * Calling amdgpu_dpm_enable_uvd makes DPM select the UVD power state 632 + * for the SMU and afterwards enables the UVD clock. 633 + * This is automatically done by amdgpu_uvd_ring_begin_use when work 634 + * is submitted to the UVD ring. Here, we have to call it manually 635 + * in order to power up UVD before firmware validation. 636 + * 637 + * Note that we must not disable the UVD clock here, as that would 638 + * cause the ring test to fail. However, UVD is powered off 639 + * automatically after the ring test: amdgpu_uvd_ring_end_use calls 640 + * the UVD idle work handler which will disable the UVD clock when 641 + * all fences are signalled. 627 642 */ 628 643 static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) 629 644 { ··· 648 633 int r; 649 634 650 635 uvd_v3_1_mc_resume(adev); 636 + uvd_v3_1_enable_mgcg(adev, true); 637 + 638 + /* Make sure UVD is powered during FW validation. 639 + * It's going to be automatically powered off after the ring test. 640 + */ 641 + if (adev->pm.dpm_enabled) 642 + amdgpu_dpm_enable_uvd(adev, true); 643 + else 644 + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 651 645 652 646 r = uvd_v3_1_fw_validate(adev); 653 647 if (r) { 654 648 DRM_ERROR("amdgpu: UVD Firmware validate fail (%d).\n", r); 655 649 return r; 656 650 } 657 - 658 - uvd_v3_1_enable_mgcg(adev, true); 659 - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 660 651 661 652 uvd_v3_1_start(adev); 662 653
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
··· 1591 1591 enum amd_clockgating_state state) 1592 1592 { 1593 1593 struct amdgpu_device *adev = ip_block->adev; 1594 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1594 + bool enable = state == AMD_CG_STATE_GATE; 1595 1595 int i; 1596 1596 1597 1597 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
··· 1311 1311 enum amd_clockgating_state state) 1312 1312 { 1313 1313 struct amdgpu_device *adev = ip_block->adev; 1314 - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1314 + bool enable = state == AMD_CG_STATE_GATE; 1315 1315 int i; 1316 1316 1317 1317 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+2 -2
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
··· 2571 2571 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2572 2572 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2573 2573 2574 - if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2575 - !args->num_devices || !args->num_bos) 2574 + if ((args->num_bos > 0 && !args->bos) || !args->devices || !args->priv_data || 2575 + !args->priv_data_size || !args->num_devices) 2576 2576 return -EINVAL; 2577 2577 2578 2578 mutex_lock(&p->mutex);
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_svm.c
··· 4261 4261 r = svm_range_get_attr(p, mm, start, size, nattrs, attrs); 4262 4262 break; 4263 4263 default: 4264 - r = EINVAL; 4264 + r = -EINVAL; 4265 4265 break; 4266 4266 } 4267 4267
+2 -1
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
··· 1589 1589 break; 1590 1590 if (!dev->gpu || !dev->gpu->adev || 1591 1591 (dev->gpu->kfd->hive_id && 1592 - dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id)) 1592 + dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id && 1593 + amdgpu_xgmi_get_is_sharing_enabled(dev->gpu->adev, new_dev->gpu->adev))) 1593 1594 goto next; 1594 1595 1595 1596 /* check if node(s) is/are peer accessible in one direction or bi-direction */
+18 -25
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 2186 2186 2187 2187 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 2188 2188 drm_err(adev_to_drm(adev), 2189 - "failed to initialize sw for display support.\n"); 2189 + "failed to initialize vblank for display support.\n"); 2190 2190 goto error; 2191 2191 } 2192 2192 ··· 2957 2957 return 0; 2958 2958 } 2959 2959 2960 + static void dm_oem_i2c_hw_fini(struct amdgpu_device *adev) 2961 + { 2962 + struct amdgpu_display_manager *dm = &adev->dm; 2963 + 2964 + if (dm->oem_i2c) { 2965 + i2c_del_adapter(&dm->oem_i2c->base); 2966 + kfree(dm->oem_i2c); 2967 + dm->oem_i2c = NULL; 2968 + } 2969 + } 2970 + 2960 2971 /** 2961 2972 * dm_hw_init() - Initialize DC device 2962 2973 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. ··· 3018 3007 { 3019 3008 struct amdgpu_device *adev = ip_block->adev; 3020 3009 3021 - kfree(adev->dm.oem_i2c); 3010 + dm_oem_i2c_hw_fini(adev); 3022 3011 3023 3012 amdgpu_dm_hpd_fini(adev); 3024 3013 ··· 3180 3169 drm_atomic_helper_resume(ddev, dm->cached_state); 3181 3170 3182 3171 dm->cached_state = NULL; 3183 - } 3184 - 3185 - static void dm_complete(struct amdgpu_ip_block *ip_block) 3186 - { 3187 - struct amdgpu_device *adev = ip_block->adev; 3188 - 3189 - dm_destroy_cached_state(adev); 3190 - } 3191 - 3192 - static int dm_prepare_suspend(struct amdgpu_ip_block *ip_block) 3193 - { 3194 - struct amdgpu_device *adev = ip_block->adev; 3195 - 3196 - if (amdgpu_in_reset(adev)) 3197 - return 0; 3198 - 3199 - WARN_ON(adev->dm.cached_state); 3200 - 3201 - return dm_cache_state(adev); 3202 3172 } 3203 3173 3204 3174 static int dm_suspend(struct amdgpu_ip_block *ip_block) ··· 3607 3615 .early_fini = amdgpu_dm_early_fini, 3608 3616 .hw_init = dm_hw_init, 3609 3617 .hw_fini = dm_hw_fini, 3610 - .prepare_suspend = dm_prepare_suspend, 3611 3618 .suspend = dm_suspend, 3612 3619 .resume = dm_resume, 3613 - .complete = dm_complete, 3614 3620 .is_idle = dm_is_idle, 3615 3621 .wait_for_idle = dm_wait_for_idle, 3616 3622 .check_soft_reset = dm_check_soft_reset, ··· 5060 5070 } else 5061 5071 props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL; 5062 5072 5063 - if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) 5073 + if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) { 5064 5074 drm_info(drm, "Using custom brightness curve\n"); 5075 + props.scale = BACKLIGHT_SCALE_NON_LINEAR; 5076 + } else 5077 + props.scale = BACKLIGHT_SCALE_LINEAR; 5065 5078 props.type = BACKLIGHT_RAW; 5066 5079 5067 5080 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", ··· 8015 8022 if (IS_ERR(mst_state)) 8016 8023 return PTR_ERR(mst_state); 8017 8024 8018 - mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); 8025 + mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); 8019 8026 8020 8027 if (!state->duplicated) { 8021 8028 int max_bpc = conn_state->max_requested_bpc;
+2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
··· 223 223 display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE; 224 224 225 225 link_adjust.auth_delay = 2; 226 + link_adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; 226 227 227 228 if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { 228 229 link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; ··· 573 572 link->dp.usb4_enabled = config->usb4_enabled; 574 573 display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; 575 574 link->adjust.auth_delay = 2; 575 + link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; 576 576 link->adjust.hdcp1.disable = 0; 577 577 hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 578 578
+11 -3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 841 841 drm_dp_aux_init(&aconnector->dm_dp_aux.aux); 842 842 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, 843 843 &aconnector->base); 844 + drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); 844 845 845 846 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 846 847 return; ··· 854 853 drm_connector_attach_dp_subconnector_property(&aconnector->base); 855 854 } 856 855 857 - int dm_mst_get_pbn_divider(struct dc_link *link) 856 + uint32_t dm_mst_get_pbn_divider(struct dc_link *link) 858 857 { 858 + uint32_t pbn_div_x100; 859 + uint64_t dividend, divisor; 860 + 859 861 if (!link) 860 862 return 0; 861 863 862 - return dc_link_bandwidth_kbps(link, 863 - dc_link_get_link_cap(link)) / (8 * 1000 * 54); 864 + dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100; 865 + divisor = 8 * 1000 * 54; 866 + 867 + pbn_div_x100 = div64_u64(dividend, divisor); 868 + 869 + return dfixed_const(pbn_div_x100) / 100; 864 870 } 865 871 866 872 struct dsc_mst_fairness_params {
+1 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
··· 60 60 struct amdgpu_display_manager; 61 61 struct amdgpu_dm_connector; 62 62 63 - int dm_mst_get_pbn_divider(struct dc_link *link); 63 + uint32_t dm_mst_get_pbn_divider(struct dc_link *link); 64 64 65 65 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 66 66 struct amdgpu_dm_connector *aconnector,
+1 -1
drivers/gpu/drm/amd/display/dc/core/dc.c
··· 4169 4169 } 4170 4170 4171 4171 if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) 4172 - dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type == UPDATE_TYPE_FAST); 4172 + dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL); 4173 4173 4174 4174 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { 4175 4175 if (dc->hwss.subvp_pipe_control_lock)
+2 -1
drivers/gpu/drm/amd/display/dc/dc.h
··· 55 55 struct set_config_cmd_payload; 56 56 struct dmub_notification; 57 57 58 - #define DC_VER "3.2.348" 58 + #define DC_VER "3.2.349" 59 59 60 60 /** 61 61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC ··· 1162 1162 unsigned int auxless_alpm_lfps_silence_ns; 1163 1163 unsigned int auxless_alpm_lfps_t1t2_us; 1164 1164 short auxless_alpm_lfps_t1t2_offset_us; 1165 + bool enable_pg_cntl_debug_logs; 1165 1166 }; 1166 1167 1167 1168
+1
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
··· 1284 1284 union dp_receive_port0_cap receive_port0_cap; 1285 1285 /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ 1286 1286 uint8_t mso_cap_sst_links_supported; 1287 + uint8_t dp_edp_general_cap_2; 1287 1288 }; 1288 1289 1289 1290 union dpcd_sink_ext_caps {
+39 -35
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
··· 133 133 }; 134 134 135 135 136 - static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable) 136 + static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) 137 137 { 138 138 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 139 139 140 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable) 140 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) 141 141 return; 142 142 143 143 switch (inst) { 144 144 case 0: 145 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); 145 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 146 146 break; 147 147 case 1: 148 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); 148 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 149 149 break; 150 150 case 2: 151 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); 151 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 152 152 break; 153 153 case 3: 154 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); 154 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 155 155 break; 156 156 default: 157 157 BREAK_TO_DEBUGGER(); 158 158 return; 159 159 } 160 + 161 + /* Wait for clock to ramp */ 162 + if (!allow_rcg) 163 + udelay(10); 160 164 } 161 165 162 166 static void dccg35_set_symclk32_se_rcg( ··· 389 385 } 390 386 } 391 387 392 - static void dccg35_set_dppclk_rcg(struct dccg *dccg, 393 - int inst, bool enable) 388 + static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) 394 389 { 395 - 396 390 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 397 391 398 - 399 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable) 392 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg) 400 393 return; 401 394 402 395 switch (inst) { 403 396 case 0: 404 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); 397 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 405 398 break; 406 399 case 1: 407 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); 400 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 408 401 break; 409 402 case 2: 410 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); 403 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 411 404 break; 412 405 case 3: 413 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); 406 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); 414 407 break; 415 408 default: 416 409 BREAK_TO_DEBUGGER(); 417 410 break; 418 411 } 419 - //DC_LOG_DEBUG("%s: inst(%d) DPPCLK rcg_disable: %d\n", __func__, inst, enable ? 0 : 1); 420 412 413 + /* Wait for clock to ramp */ 414 + if (!allow_rcg) 415 + udelay(10); 421 416 } 422 417 423 418 static void dccg35_set_dpstreamclk_rcg( ··· 1180 1177 } 1181 1178 1182 1179 static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg, 1183 - uint32_t dpp_inst, uint32_t enable) 1180 + uint32_t dpp_inst, uint32_t disallow_rcg) 1184 1181 { 1185 1182 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 1186 1183 1187 - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) 1184 + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg) 1188 1185 return; 1189 1186 1190 1187 1191 1188 switch (dpp_inst) { 1192 1189 case 0: 1193 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable); 1190 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, disallow_rcg); 1194 1191 break; 1195 1192 case 1: 1196 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable); 1193 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, disallow_rcg); 1197 1194 break; 1198 1195 case 2: 1199 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable); 1196 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, disallow_rcg); 1200 1197 break; 1201 1198 case 3: 1202 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable); 1199 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, disallow_rcg); 1203 1200 break; 1204 1201 default: 1205 1202 break; 1206 1203 } 1207 - //DC_LOG_DEBUG("%s: dpp_inst(%d) rcg: %d\n", __func__, dpp_inst, enable); 1208 1204 1205 + /* Wait for clock to ramp */ 1206 + if (disallow_rcg) 1207 + udelay(10); 1209 1208 } 1210 1209 1211 1210 static void dccg35_get_pixel_rate_div( ··· 1787 1782 //Disable DTO 1788 1783 switch (inst) { 1789 1784 case 0: 1790 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1791 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); 1785 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); 1792 1786 1793 1787 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 1794 1788 DSCCLK0_DTO_PHASE, 0, ··· 1795 1791 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); 1796 1792 break; 1797 1793 case 1: 1798 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1799 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); 1794 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); 1800 1795 1801 1796 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 1802 1797 DSCCLK1_DTO_PHASE, 0, ··· 1803 1800 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); 1804 1801 break; 1805 1802 case 2: 1806 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1807 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); 1803 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); 1808 1804 1809 1805 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 1810 1806 DSCCLK2_DTO_PHASE, 0, ··· 1811 1809 REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1); 1812 1810 break; 1813 1811 case 3: 1814 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 1815 - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); 1812 + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); 1816 1813 1817 1814 REG_UPDATE_2(DSCCLK3_DTO_PARAM, 1818 1815 DSCCLK3_DTO_PHASE, 0, ··· 1822 1821 BREAK_TO_DEBUGGER(); 1823 1822 return; 1824 1823 } 1824 + 1825 + /* Wait for clock to ramp */ 1826 + udelay(10); 1825 1827 } 1826 1828 1827 1829 static void dccg35_disable_dscclk(struct dccg *dccg, ··· 1868 1864 default: 1869 1865 return; 1870 1866 } 1867 + 1868 + /* Wait for clock ramp */ 1869 + udelay(10); 1871 1870 } 1872 1871 1873 1872 static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) ··· 2356 2349 2357 2350 void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating) 2358 2351 { 2359 - 2360 - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { 2361 - dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); 2362 - } 2352 + dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); 2363 2353 } 2364 2354 2365 2355 static const struct dccg_funcs dccg35_funcs_new = {
+13 -4
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
··· 725 725 for (i = 0; i < AUX_MAX_RETRIES; i++) { 726 726 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, 727 727 LOG_FLAG_I2cAux_DceAux, 728 - "dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d", 728 + "dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: " 729 + "address=0x%04x length=%u write=%d mot=%d is_i2c=%d is_dpia=%d ddc_hw_inst=%d", 729 730 ddc && ddc->link ? ddc->link->link_index : UINT_MAX, 730 731 i + 1, 731 732 (int)AUX_MAX_RETRIES, 732 733 payload->address, 733 734 payload->length, 734 735 (unsigned int) payload->write, 735 - (unsigned int) payload->mot); 736 + (unsigned int) payload->mot, 737 + payload->i2c_over_aux, 738 + (ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false, 739 + ddc->link->ddc_hw_inst); 736 740 if (payload->write) 737 741 dce_aux_log_payload(" write", payload->data, payload->length, 16); 738 742 ··· 750 746 751 747 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, 752 748 LOG_FLAG_I2cAux_DceAux, 753 - "dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload->reply=%u", 749 + "dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: " 750 + "address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d " 751 + "payload->reply=%u is_i2c=%d is_dpia=%d ddc_hw_inst=%d", 754 752 ddc && ddc->link ? ddc->link->link_index : UINT_MAX, 755 753 i + 1, 756 754 (int)AUX_MAX_RETRIES, ··· 762 756 (unsigned int) payload->mot, 763 757 ret, 764 758 (int)operation_result, 765 - (unsigned int) *payload->reply); 759 + (unsigned int) *payload->reply, 760 + payload->i2c_over_aux, 761 + (ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false, 762 + ddc->link->ddc_hw_inst); 766 763 if (!payload->write) 767 764 dce_aux_log_payload(" read", payload->data, ret > 0 ? ret : 0, 16); 768 765
+1 -1
drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c
··· 397 397 uint32_t reset_val; 398 398 399 399 REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val); 400 - return (reset_val == 0) ? false : true; 400 + return reset_val != 0; 401 401 } 402 402 void enc35_disable_fifo(struct stream_encoder *enc) 403 403 {
+1 -1
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
··· 535 535 if (result) 536 536 result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info); 537 537 538 - return (result == 1) ? true : false; 538 + return result == 1; 539 539 } 540 540 541 541 static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2)
+20 -95
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
··· 113 113 } 114 114 #endif 115 115 116 + static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log) 117 + { 118 + if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { 119 + if (dc->res_pool->pg_cntl->funcs->print_pg_status) 120 + dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); 121 + } 122 + } 123 + 116 124 void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable) 117 125 { 118 126 REG_UPDATE_3(DMU_CLK_CNTL, ··· 144 136 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 145 137 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 146 138 int i; 139 + 140 + print_pg_status(dc, __func__, ": start"); 147 141 148 142 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 149 143 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); ··· 210 200 211 201 /* we want to turn off all dp displays before doing detection */ 212 202 dc->link_srv->blank_all_dp_displays(dc); 213 - /* 214 - if (hws->funcs.enable_power_gating_plane) 215 - hws->funcs.enable_power_gating_plane(dc->hwseq, true); 216 - */ 203 + 217 204 if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init) 218 205 res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub); 219 206 /* If taking control over from VBIOS, we may want to optimize our first ··· 243 236 } 244 237 245 238 hws->funcs.init_pipes(dc, dc->current_state); 239 + print_pg_status(dc, __func__, ": after init_pipes"); 240 + 246 241 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control && 247 242 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter) 248 243 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, ··· 321 312 if (dc->res_pool->pg_cntl->funcs->init_pg_status) 322 313 dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); 323 314 } 315 + print_pg_status(dc, __func__, ": after init_pg_status"); 324 316 } 325 317 326 318 static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) ··· 508 498 hws->ctx->dc->res_pool->dccg->funcs->set_physymclk_root_clock_gating( 509 499 hws->ctx->dc->res_pool->dccg, phy_inst, clock_on); 510 500 } 511 - } 512 - 513 - void dcn35_dsc_pg_control( 514 - struct dce_hwseq *hws, 515 - unsigned int dsc_inst, 516 - bool power_on) 517 - { 518 - uint32_t power_gate = power_on ? 0 : 1; 519 - uint32_t pwr_status = power_on ? 0 : 2; 520 - uint32_t org_ip_request_cntl = 0; 521 - 522 - if (hws->ctx->dc->debug.disable_dsc_power_gate) 523 - return; 524 - if (hws->ctx->dc->debug.ignore_pg) 525 - return; 526 - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 527 - if (org_ip_request_cntl == 0) 528 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 529 - 530 - switch (dsc_inst) { 531 - case 0: /* DSC0 */ 532 - REG_UPDATE(DOMAIN16_PG_CONFIG, 533 - DOMAIN_POWER_GATE, power_gate); 534 - 535 - REG_WAIT(DOMAIN16_PG_STATUS, 536 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 537 - 1, 1000); 538 - break; 539 - case 1: /* DSC1 */ 540 - REG_UPDATE(DOMAIN17_PG_CONFIG, 541 - DOMAIN_POWER_GATE, power_gate); 542 - 543 - REG_WAIT(DOMAIN17_PG_STATUS, 544 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 545 - 1, 1000); 546 - break; 547 - case 2: /* DSC2 */ 548 - REG_UPDATE(DOMAIN18_PG_CONFIG, 549 - DOMAIN_POWER_GATE, power_gate); 550 - 551 - REG_WAIT(DOMAIN18_PG_STATUS, 552 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 553 - 1, 1000); 554 - break; 555 - case 3: /* DSC3 */ 556 - REG_UPDATE(DOMAIN19_PG_CONFIG, 557 - DOMAIN_POWER_GATE, power_gate); 558 - 559 - REG_WAIT(DOMAIN19_PG_STATUS, 560 - DOMAIN_PGFSM_PWR_STATUS, pwr_status, 561 - 1, 1000); 562 - break; 563 - default: 564 - BREAK_TO_DEBUGGER(); 565 - break; 566 - } 567 - 568 - if (org_ip_request_cntl == 0) 569 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 570 - } 571 - 572 - void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) 573 - { 574 - bool force_on = true; /* disable power gating */ 575 - uint32_t org_ip_request_cntl = 0; 576 - 577 - if (hws->ctx->dc->debug.disable_hubp_power_gate) 578 - return; 579 - if (hws->ctx->dc->debug.ignore_pg) 580 - return; 581 - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 582 - if (org_ip_request_cntl == 0) 583 - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 584 - /* DCHUBP0/1/2/3/4/5 */ 585 - REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 586 - REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 587 - /* DPP0/1/2/3/4/5 */ 588 - REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 589 - REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 590 - 591 - force_on = true; /* disable power gating */ 592 - if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 593 - force_on = false; 594 - 595 - /* DCS0/1/2/3/4 */ 596 - REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 597 - REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 598 - REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 599 - REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 600 - 601 - 602 501 } 603 502 604 503 /* In headless boot cases, DIG may be turned ··· 1372 1453 } 1373 1454 1374 1455 dcn20_prepare_bandwidth(dc, context); 1456 + 1457 + print_pg_status(dc, __func__, ": after rcg and power up"); 1375 1458 } 1376 1459 1377 1460 void dcn35_optimize_bandwidth( ··· 1381 1460 struct dc_state *context) 1382 1461 { 1383 1462 struct pg_block_update pg_update_state; 1463 + 1464 + print_pg_status(dc, __func__, ": before rcg and power up"); 1384 1465 1385 1466 dcn20_optimize_bandwidth(dc, context); 1386 1467 ··· 1395 1472 if (dc->hwss.root_clock_control) 1396 1473 dc->hwss.root_clock_control(dc, &pg_update_state, false); 1397 1474 } 1475 + 1476 + print_pg_status(dc, __func__, ": after rcg and power up"); 1398 1477 } 1399 1478 1400 1479 void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
-3
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
··· 115 115 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 116 116 .update_visual_confirm_color = dcn10_update_visual_confirm_color, 117 117 .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, 118 - .update_dsc_pg = dcn32_update_dsc_pg, 119 118 .calc_blocks_to_gate = dcn35_calc_blocks_to_gate, 120 119 .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate, 121 120 .hw_block_power_up = dcn35_hw_block_power_up, ··· 150 151 .plane_atomic_disable = dcn35_plane_atomic_disable, 151 152 //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ 152 153 //.hubp_pg_control = dcn35_hubp_pg_control, 153 - .enable_power_gating_plane = dcn35_enable_power_gating_plane, 154 154 .dpp_root_clock_control = dcn35_dpp_root_clock_control, 155 155 .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, 156 156 .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, ··· 164 166 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, 165 167 .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, 166 168 .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, 167 - .dsc_pg_control = dcn35_dsc_pg_control, 168 169 .dsc_pg_status = dcn32_dsc_pg_status, 169 170 .enable_plane = dcn35_enable_plane, 170 171 .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,
-3
drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
··· 114 114 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 115 115 .update_visual_confirm_color = dcn10_update_visual_confirm_color, 116 116 .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, 117 - .update_dsc_pg = dcn32_update_dsc_pg, 118 117 .calc_blocks_to_gate = dcn351_calc_blocks_to_gate, 119 118 .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate, 120 119 .hw_block_power_up = dcn351_hw_block_power_up, ··· 145 146 .plane_atomic_disable = dcn35_plane_atomic_disable, 146 147 //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ 147 148 //.hubp_pg_control = dcn35_hubp_pg_control, 148 - .enable_power_gating_plane = dcn35_enable_power_gating_plane, 149 149 .dpp_root_clock_control = dcn35_dpp_root_clock_control, 150 150 .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, 151 151 .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, ··· 158 160 .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, 159 161 .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, 160 162 .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, 161 - .dsc_pg_control = dcn35_dsc_pg_control, 162 163 .dsc_pg_status = dcn32_dsc_pg_status, 163 164 .enable_plane = dcn35_enable_plane, 164 165 .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,
+22
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
··· 137 137 uint32_t dram_state_cntl; 138 138 }; 139 139 140 + struct hubbub_system_latencies { 141 + uint32_t max_latency_ns; 142 + uint32_t avg_latency_ns; 143 + uint32_t min_latency_ns; 144 + }; 145 + 146 + struct hubbub_urgent_latency_params { 147 + uint32_t refclk_mhz; 148 + uint32_t t_win_ns; 149 + uint32_t bandwidth_mbps; 150 + uint32_t bw_factor_x1000; 151 + }; 152 + 140 153 struct hubbub_funcs { 141 154 void (*update_dchub)( 142 155 struct hubbub *hubbub, ··· 244 231 bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); 245 232 void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); 246 233 uint32_t (*compbuf_config_error)(struct hubbub *hubbub); 234 + struct hubbub_perfmon_funcs{ 235 + void (*start_system_latency_measurement)(struct hubbub *hubbub); 236 + void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies); 237 + void (*start_in_order_bandwidth_measurement)(struct hubbub *hubbub); 238 + void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps); 239 + void (*start_urgent_ramp_latency_measurement)(struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params); 240 + void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns); 241 + void (*reset)(struct hubbub *hubbub); 242 + } perfmon; 247 243 }; 248 244 249 245 struct hubbub {
+1
drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h
··· 49 49 void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on); 50 50 void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on); 51 51 void (*init_pg_status)(struct pg_cntl *pg_cntl); 52 + void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log); 52 53 }; 53 54 54 55 #endif //__DC_PG_CNTL_H__
+50 -28
drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
··· 79 79 uint32_t power_gate = power_on ? 0 : 1; 80 80 uint32_t pwr_status = power_on ? 0 : 2; 81 81 uint32_t org_ip_request_cntl = 0; 82 - bool block_enabled; 82 + bool block_enabled = false; 83 + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || 84 + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || 85 + pg_cntl->ctx->dc->idle_optimizations_allowed; 83 86 84 - /*need to enable dscclk regardless DSC_PG*/ 85 - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) 86 - pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( 87 - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); 88 - 89 - if (pg_cntl->ctx->dc->debug.ignore_pg || 90 - pg_cntl->ctx->dc->debug.disable_dsc_power_gate || 91 - pg_cntl->ctx->dc->idle_optimizations_allowed) 87 + if (skip_pg && !power_on) 92 88 return; 93 89 94 90 block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst); ··· 107 111 108 112 REG_WAIT(DOMAIN16_PG_STATUS, 109 113 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 110 - 1, 1000); 114 + 1, 10000); 111 115 break; 112 116 case 1: /* DSC1 */ 113 117 REG_UPDATE(DOMAIN17_PG_CONFIG, ··· 115 119 116 120 REG_WAIT(DOMAIN17_PG_STATUS, 117 121 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 118 - 1, 1000); 122 + 1, 10000); 119 123 break; 120 124 case 2: /* DSC2 */ 121 125 REG_UPDATE(DOMAIN18_PG_CONFIG, ··· 123 127 124 128 REG_WAIT(DOMAIN18_PG_STATUS, 125 129 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 126 - 1, 1000); 130 + 1, 10000); 127 131 break; 128 132 case 3: /* DSC3 */ 129 133 REG_UPDATE(DOMAIN19_PG_CONFIG, ··· 131 135 132 136 REG_WAIT(DOMAIN19_PG_STATUS, 133 137 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 134 - 1, 1000); 138 + 1, 10000); 135 139 break; 136 140 default: 137 141 BREAK_TO_DEBUGGER(); ··· 140 144 141 145 if (dsc_inst < MAX_PIPES) 142 146 pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; 143 - 144 - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { 145 - /*this is to disable dscclk*/ 146 - pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( 147 - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); 148 - } 149 147 } 150 148 151 149 static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) ··· 179 189 uint32_t pwr_status = power_on ? 0 : 2; 180 190 uint32_t org_ip_request_cntl; 181 191 bool block_enabled; 192 + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || 193 + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || 194 + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || 195 + pg_cntl->ctx->dc->idle_optimizations_allowed; 182 196 183 - if (pg_cntl->ctx->dc->debug.ignore_pg || 184 - pg_cntl->ctx->dc->debug.disable_hubp_power_gate || 185 - pg_cntl->ctx->dc->debug.disable_dpp_power_gate || 186 - pg_cntl->ctx->dc->idle_optimizations_allowed) 197 + if (skip_pg && !power_on) 187 198 return; 188 199 189 200 block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); ··· 204 213 case 0: 205 214 /* DPP0 & HUBP0 */ 206 215 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 207 - REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 216 + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 208 217 break; 209 218 case 1: 210 219 /* DPP1 & HUBP1 */ 211 220 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 212 - REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 221 + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 213 222 break; 214 223 case 2: 215 224 /* DPP2 & HUBP2 */ 216 225 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 217 - REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 226 + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 218 227 break; 219 228 case 3: 220 229 /* DPP3 & HUBP3 */ 221 230 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); 222 - REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 231 + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); 223 232 break; 224 233 default: 225 234 BREAK_TO_DEBUGGER(); ··· 492 501 pg_cntl->pg_res_enable[PG_DWB] = block_enabled; 493 502 } 494 503 504 + static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log) 505 + { 506 + int i = 0; 507 + bool block_enabled = false; 508 + 509 + DC_LOG_DEBUG("%s: %s", debug_func, debug_log); 510 + 511 + DC_LOG_DEBUG("PG_CNTL status:\n"); 512 + 513 + block_enabled = pg_cntl35_io_clk_status(pg_cntl); 514 + DC_LOG_DEBUG("ONO0=%d (DCCG, DIO, DCIO)\n", block_enabled ? 1 : 0); 515 + 516 + block_enabled = pg_cntl35_mem_status(pg_cntl); 517 + DC_LOG_DEBUG("ONO1=%d (DCHUBBUB, DCHVM, DCHUBBUBMEM)\n", block_enabled ? 1 : 0); 518 + 519 + block_enabled = pg_cntl35_plane_otg_status(pg_cntl); 520 + DC_LOG_DEBUG("ONO2=%d (MPC, OPP, OPTC, DWB)\n", block_enabled ? 1 : 0); 521 + 522 + block_enabled = pg_cntl35_hpo_pg_status(pg_cntl); 523 + DC_LOG_DEBUG("ONO3=%d (HPO)\n", block_enabled ? 1 : 0); 524 + 525 + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { 526 + block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i); 527 + DC_LOG_DEBUG("ONO%d=%d (DCHUBP%d, DPP%d)\n", 4 + i * 2, block_enabled ? 1 : 0, i, i); 528 + 529 + block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i); 530 + DC_LOG_DEBUG("ONO%d=%d (DSC%d)\n", 5 + i * 2, block_enabled ? 1 : 0, i); 531 + } 532 + } 533 + 495 534 static const struct pg_cntl_funcs pg_cntl35_funcs = { 496 535 .init_pg_status = pg_cntl35_init_pg_status, 497 536 .dsc_pg_control = pg_cntl35_dsc_pg_control, ··· 532 511 .mpcc_pg_control = pg_cntl35_mpcc_pg_control, 533 512 .opp_pg_control = pg_cntl35_opp_pg_control, 534 513 .optc_pg_control = pg_cntl35_optc_pg_control, 535 - .dwb_pg_control = pg_cntl35_dwb_pg_control 514 + .dwb_pg_control = pg_cntl35_dwb_pg_control, 515 + .print_pg_status = pg_cntl35_print_pg_status 536 516 }; 537 517 538 518 struct pg_cntl *pg_cntl35_create(
+2 -2
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
··· 226 226 unsigned int target_duration_in_us = 227 227 calc_duration_in_us_from_refresh_in_uhz( 228 228 in_out_vrr->fixed.target_refresh_in_uhz); 229 - bool ramp_direction_is_up = (current_duration_in_us > 230 - target_duration_in_us) ? true : false; 229 + bool ramp_direction_is_up = current_duration_in_us > 230 + target_duration_in_us; 231 231 232 232 /* Calculate ratio between new and current frame duration with 3 digit */ 233 233 unsigned int frame_duration_ratio = div64_u64(1000000,
+3 -2
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c
··· 29 29 enum mod_hdcp_status status) 30 30 { 31 31 struct mod_hdcp_trace *trace = &hdcp->connection.trace; 32 + const uint8_t retry_limit = hdcp->connection.link.adjust.retry_limit; 32 33 33 34 if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) { 34 35 trace->errors[trace->error_count].status = status; ··· 40 39 41 40 if (is_hdcp1(hdcp)) { 42 41 hdcp->connection.hdcp1_retry_count++; 43 - if (hdcp->connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS) 42 + if (hdcp->connection.hdcp1_retry_count == retry_limit) 44 43 hdcp->connection.link.adjust.hdcp1.disable = 1; 45 44 } else if (is_hdcp2(hdcp)) { 46 45 hdcp->connection.hdcp2_retry_count++; 47 - if (hdcp->connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS) 46 + if (hdcp->connection.hdcp2_retry_count == retry_limit) 48 47 hdcp->connection.link.adjust.hdcp2.disable = 1; 49 48 } 50 49 }
+1
drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
··· 220 220 221 221 struct mod_hdcp_link_adjustment { 222 222 uint8_t auth_delay; 223 + uint8_t retry_limit; 223 224 struct mod_hdcp_link_adjustment_hdcp1 hdcp1; 224 225 struct mod_hdcp_link_adjustment_hdcp2 hdcp2; 225 226 };
+7
drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c
··· 66 66 (amdgpu_crtc->v_border * 2)); 67 67 68 68 vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; 69 + 70 + /* we have issues with mclk switching with 71 + * refresh rates over 120 hz on the non-DC code. 72 + */ 73 + if (drm_mode_vrefresh(&amdgpu_crtc->hw_mode) > 120) 74 + vblank_time_us = 0; 75 + 69 76 break; 70 77 } 71 78 }
+3 -2
drivers/gpu/drm/amd/pm/amdgpu_pm.c
··· 110 110 bool runpm_check = runpm ? adev->in_runpm : false; 111 111 112 112 if (amdgpu_in_reset(adev)) 113 - return -EPERM; 113 + return -EBUSY; 114 + 114 115 if (adev->in_suspend && !runpm_check) 115 - return -EPERM; 116 + return -EBUSY; 116 117 117 118 return 0; 118 119 }
+1 -2
drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c
··· 771 771 int i; 772 772 struct amdgpu_ps *ps; 773 773 u32 ui_class; 774 - bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? 775 - true : false; 774 + bool single_display = adev->pm.dpm.new_active_crtc_count < 2; 776 775 777 776 /* check if the vblank period is too short to adjust the mclk */ 778 777 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
+66 -27
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
··· 3085 3085 /* we never hit the non-gddr5 limit so disable it */ 3086 3086 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3087 3087 3088 - if (vblank_time < switch_limit) 3088 + /* Consider zero vblank time too short and disable MCLK switching. 3089 + * Note that the vblank time is set to maximum when no displays are attached, 3090 + * so we'll still enable MCLK switching in that case. 3091 + */ 3092 + if (vblank_time == 0) 3093 + return true; 3094 + else if (vblank_time < switch_limit) 3089 3095 return true; 3090 3096 else 3091 3097 return false; ··· 3449 3443 { 3450 3444 struct si_ps *ps = si_get_ps(rps); 3451 3445 struct amdgpu_clock_and_voltage_limits *max_limits; 3446 + struct amdgpu_connector *conn; 3452 3447 bool disable_mclk_switching = false; 3453 3448 bool disable_sclk_switching = false; 3454 3449 u32 mclk, sclk; 3455 3450 u16 vddc, vddci, min_vce_voltage = 0; 3456 3451 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3457 3452 u32 max_sclk = 0, max_mclk = 0; 3453 + u32 high_pixelclock_count = 0; 3458 3454 int i; 3459 3455 3460 3456 if (adev->asic_type == CHIP_HAINAN) { ··· 3482 3474 (adev->pdev->device == 0x6605)) { 3483 3475 max_sclk = 75000; 3484 3476 } 3477 + } 3478 + 3479 + /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. 3480 + * For example, 4K 60Hz and 1080p 144Hz fall into this category. 3481 + * Find number of such displays connected. 3482 + */ 3483 + for (i = 0; i < adev->mode_info.num_crtc; i++) { 3484 + if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) || 3485 + !adev->mode_info.crtcs[i]->enabled) 3486 + continue; 3487 + 3488 + conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector); 3489 + 3490 + if (conn->pixelclock_for_modeset > 297000) 3491 + high_pixelclock_count++; 3492 + } 3493 + 3494 + /* These are some ad-hoc fixes to some issues observed with SI GPUs. 3495 + * They are necessary because we don't have something like dce_calcs 3496 + * for these GPUs to calculate bandwidth requirements. 3497 + */ 3498 + if (high_pixelclock_count) { 3499 + /* On Oland, we observe some flickering when two 4K 60Hz 3500 + * displays are connected, possibly because voltage is too low. 3501 + * Raise the voltage by requiring a higher SCLK. 3502 + * (Voltage cannot be adjusted independently without also SCLK.) 3503 + */ 3504 + if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND) 3505 + disable_sclk_switching = true; 3485 3506 } 3486 3507 3487 3508 if (rps->vce_active) { ··· 5674 5637 5675 5638 static int si_disable_ulv(struct amdgpu_device *adev) 5676 5639 { 5677 - struct si_power_info *si_pi = si_get_pi(adev); 5678 - struct si_ulv_param *ulv = &si_pi->ulv; 5640 + PPSMC_Result r; 5679 5641 5680 - if (ulv->supported) 5681 - return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5682 - 0 : -EINVAL; 5683 - 5684 - return 0; 5642 + r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV); 5643 + return (r == PPSMC_Result_OK) ? 0 : -EINVAL; 5685 5644 } 5686 5645 5687 5646 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, ··· 5850 5817 { 5851 5818 struct amdgpu_crtc *amdgpu_crtc = NULL; 5852 5819 int i; 5853 - 5854 - if (adev->pm.dpm.new_active_crtc_count == 0) 5855 - return 0; 5820 + u32 crtc_index = 0; 5821 + u32 mclk_change_block_cp_min = 0; 5822 + u32 mclk_change_block_cp_max = 0; 5856 5823 5857 5824 for (i = 0; i < adev->mode_info.num_crtc; i++) { 5858 5825 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { ··· 5861 5828 } 5862 5829 } 5863 5830 5864 - if (amdgpu_crtc == NULL) 5865 - return 0; 5831 + /* When a display is plugged in, program these so that the SMC 5832 + * performs MCLK switching when it doesn't cause flickering. 5833 + * When no display is plugged in, there is no need to restrict 5834 + * MCLK switching, so program them to zero. 5835 + */ 5836 + if (adev->pm.dpm.new_active_crtc_count && amdgpu_crtc) { 5837 + crtc_index = amdgpu_crtc->crtc_id; 5866 5838 5867 - if (amdgpu_crtc->line_time <= 0) 5868 - return 0; 5839 + if (amdgpu_crtc->line_time) { 5840 + mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time; 5841 + mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time; 5842 + } 5843 + } 5869 5844 5870 - if (si_write_smc_soft_register(adev, 5871 - SI_SMC_SOFT_REGISTER_crtc_index, 5872 - amdgpu_crtc->crtc_id) != PPSMC_Result_OK) 5873 - return 0; 5845 + si_write_smc_soft_register(adev, 5846 + SI_SMC_SOFT_REGISTER_crtc_index, 5847 + crtc_index); 5874 5848 5875 - if (si_write_smc_soft_register(adev, 5876 - SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5877 - amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5878 - return 0; 5849 + si_write_smc_soft_register(adev, 5850 + SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5851 + mclk_change_block_cp_min); 5879 5852 5880 - if (si_write_smc_soft_register(adev, 5881 - SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5882 - amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5883 - return 0; 5853 + si_write_smc_soft_register(adev, 5854 + SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5855 + mclk_change_block_cp_max); 5884 5856 5885 5857 return 0; 5886 5858 } ··· 7992 7954 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); 7993 7955 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); 7994 7956 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7957 + drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 7995 7958 for (i = 0; i < ps->performance_level_count; i++) { 7996 7959 pl = &ps->performance_levels[i]; 7997 7960 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+24 -2
drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c
··· 172 172 { 173 173 u32 tmp; 174 174 int i; 175 + int usec_timeout; 176 + 177 + /* SMC seems to process some messages exceptionally slowly. */ 178 + switch (msg) { 179 + case PPSMC_MSG_NoForcedLevel: 180 + case PPSMC_MSG_SetEnabledLevels: 181 + case PPSMC_MSG_SetForcedLevels: 182 + case PPSMC_MSG_DisableULV: 183 + case PPSMC_MSG_SwitchToSwState: 184 + usec_timeout = 1000000; /* 1 sec */ 185 + break; 186 + default: 187 + usec_timeout = 200000; /* 200 ms */ 188 + break; 189 + } 175 190 176 191 if (!amdgpu_si_is_smc_running(adev)) 177 192 return PPSMC_Result_Failed; 178 193 179 194 WREG32(mmSMC_MESSAGE_0, msg); 180 195 181 - for (i = 0; i < adev->usec_timeout; i++) { 196 + for (i = 0; i < usec_timeout; i++) { 182 197 tmp = RREG32(mmSMC_RESP_0); 183 198 if (tmp != 0) 184 199 break; 185 200 udelay(1); 186 201 } 187 202 188 - return (PPSMC_Result)RREG32(mmSMC_RESP_0); 203 + tmp = RREG32(mmSMC_RESP_0); 204 + if (tmp == 0) { 205 + drm_warn(adev_to_drm(adev), 206 + "%s timeout on message: %x (SMC_SCRATCH0: %x)\n", 207 + __func__, msg, RREG32(mmSMC_SCRATCH0)); 208 + } 209 + 210 + return (PPSMC_Result)tmp; 189 211 } 190 212 191 213 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev)
+2 -2
drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c
··· 563 563 PP_ASSERT_WITH_CODE((NULL != voltage_info), 564 564 "Could not find Voltage Table in BIOS.", return false;); 565 565 566 - ret = (NULL != atomctrl_lookup_voltage_type_v3 567 - (voltage_info, voltage_type, voltage_mode)) ? true : false; 566 + ret = atomctrl_lookup_voltage_type_v3 567 + (voltage_info, voltage_type, voltage_mode) != NULL; 568 568 569 569 return ret; 570 570 }
+1 -1
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
··· 1032 1032 data->clock_vol_info.vdd_dep_on_fclk; 1033 1033 uint32_t i, now, size = 0; 1034 1034 uint32_t min_freq, max_freq = 0; 1035 - uint32_t ret = 0; 1035 + int ret = 0; 1036 1036 1037 1037 switch (type) { 1038 1038 case PP_SCLK:
+2 -3
drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c
··· 2540 2540 2541 2541 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr) 2542 2542 { 2543 - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 2544 - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 2545 - ? true : false; 2543 + return PHM_READ_INDIRECT_FIELD(hwmgr->device, 2544 + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; 2546 2545 } 2547 2546 2548 2547 static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
+2 -3
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
··· 2655 2655 2656 2656 static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr) 2657 2657 { 2658 - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 2659 - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 2660 - ? true : false; 2658 + return PHM_READ_INDIRECT_FIELD(hwmgr->device, 2659 + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; 2661 2660 } 2662 2661 2663 2662 const struct pp_smumgr_func iceland_smu_funcs = {
+2 -3
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
··· 2578 2578 2579 2579 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) 2580 2580 { 2581 - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 2582 - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 2583 - ? true : false; 2581 + return PHM_READ_INDIRECT_FIELD(hwmgr->device, 2582 + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; 2584 2583 } 2585 2584 2586 2585 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
+1 -1
drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c
··· 401 401 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) 402 402 { 403 403 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); 404 - uint32_t ret; 404 + int ret; 405 405 406 406 ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11, 407 407 smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
+2 -3
drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c
··· 3139 3139 3140 3140 static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) 3141 3141 { 3142 - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 3143 - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 3144 - ? true : false; 3142 + return PHM_READ_INDIRECT_FIELD(hwmgr->device, 3143 + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; 3145 3144 } 3146 3145 3147 3146 static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr,
+1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 333 333 SMU_TABLE_WIFIBAND, 334 334 SMU_TABLE_GPUBOARD_TEMP_METRICS, 335 335 SMU_TABLE_BASEBOARD_TEMP_METRICS, 336 + SMU_TABLE_PMFW_SYSTEM_METRICS, 336 337 SMU_TABLE_COUNT, 337 338 }; 338 339
+1 -1
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
··· 470 470 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 471 471 { 472 472 uint32_t min = 0, max = 0; 473 - uint32_t ret = 0; 473 + int ret = 0; 474 474 475 475 ret = smu_cmn_send_smc_msg_with_param(smu, 476 476 SMU_MSG_GetMinGfxclkFrequency,
+30 -13
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
··· 149 149 struct smu_table_cache *cache; 150 150 int ret; 151 151 152 + ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, 153 + smu_v13_0_12_get_system_metrics_size(), 5); 154 + 155 + if (ret) 156 + return ret; 157 + 152 158 ret = smu_table_cache_init(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS, 153 159 sizeof(*baseboard_temp_metrics), 50); 154 160 if (ret) ··· 168 162 ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, 169 163 sizeof(*gpuboard_temp_metrics), 50); 170 164 if (ret) { 165 + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 171 166 smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); 172 167 return ret; 173 168 } ··· 183 176 { 184 177 smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); 185 178 smu_table_cache_fini(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS); 179 + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); 186 180 } 187 181 188 182 static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, ··· 230 222 231 223 int smu_v13_0_12_get_max_metrics_size(void) 232 224 { 233 - return max3(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t), 234 - sizeof(SystemMetricsTable_t)); 225 + return max(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t)); 226 + } 227 + 228 + size_t smu_v13_0_12_get_system_metrics_size(void) 229 + { 230 + return sizeof(SystemMetricsTable_t); 235 231 } 236 232 237 233 static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, ··· 426 414 return 0; 427 415 } 428 416 429 - static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, 430 - void *metrics_table) 417 + static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu) 431 418 { 432 419 struct smu_table_context *smu_table = &smu->smu_table; 433 - uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; 434 420 struct smu_table *table = &smu_table->driver_table; 421 + struct smu_table *tables = smu_table->tables; 422 + struct smu_table *sys_table; 435 423 int ret; 424 + 425 + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 426 + if (smu_table_cache_is_valid(sys_table)) 427 + return 0; 436 428 437 429 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); 438 430 if (ret) { ··· 446 430 } 447 431 448 432 amdgpu_asic_invalidate_hdp(smu->adev, NULL); 449 - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); 450 - 451 - if (metrics_table) 452 - memcpy(metrics_table, smu_table->metrics_table, sizeof(SystemMetricsTable_t)); 433 + smu_table_cache_update_time(sys_table, jiffies); 434 + memcpy(sys_table->cache.buffer, table->cpu_addr, 435 + smu_v13_0_12_get_system_metrics_size()); 453 436 454 437 return 0; 455 438 } ··· 586 571 struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; 587 572 struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; 588 573 struct smu_table_context *smu_table = &smu->smu_table; 589 - SystemMetricsTable_t *metrics = 590 - (SystemMetricsTable_t *)smu_table->metrics_table; 591 - 574 + struct smu_table *tables = smu_table->tables; 575 + SystemMetricsTable_t *metrics; 592 576 struct smu_table *data_table; 577 + struct smu_table *sys_table; 593 578 int ret, sensor_type; 594 579 u32 idx, sensors; 595 580 ssize_t size; ··· 611 596 size = sizeof(*baseboard_temp_metrics); 612 597 } 613 598 614 - ret = smu_v13_0_12_get_system_metrics_table(smu, NULL); 599 + ret = smu_v13_0_12_get_system_metrics_table(smu); 615 600 if (ret) 616 601 return ret; 617 602 603 + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; 604 + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; 618 605 smu_table_cache_update_time(data_table, jiffies); 619 606 620 607 if (type == SMU_TEMP_METRIC_GPUBOARD) {
+4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
··· 559 559 PAGE_SIZE, 560 560 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); 561 561 562 + SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS, 563 + smu_v13_0_12_get_system_metrics_size(), PAGE_SIZE, 564 + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); 565 + 562 566 metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); 563 567 if (!metrics_table) 564 568 return -ENOMEM;
+1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
··· 82 82 83 83 bool smu_v13_0_12_is_dpm_running(struct smu_context *smu); 84 84 int smu_v13_0_12_get_max_metrics_size(void); 85 + size_t smu_v13_0_12_get_system_metrics_size(void); 85 86 int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu); 86 87 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, 87 88 MetricsMember_t member, uint32_t *value);
+1 -1
drivers/gpu/drm/radeon/atombios_encoders.c
··· 1832 1832 return; 1833 1833 } 1834 1834 1835 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1835 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 1836 1836 1837 1837 } 1838 1838
+8 -6
drivers/gpu/drm/radeon/ci_dpm.c
··· 2457 2457 u32 tmp, tmp2; 2458 2458 2459 2459 tmp = RREG32(MC_SEQ_MISC0); 2460 - patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 2460 + patch = (tmp & 0x0000f00) == 0x300; 2461 2461 2462 2462 if (patch && 2463 2463 ((rdev->pdev->device == 0x67B0) || ··· 3238 3238 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) * 3239 3239 SMU7_MAX_LEVELS_GRAPHICS; 3240 3240 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; 3241 - u32 i, ret; 3241 + int ret; 3242 + u32 i; 3242 3243 3243 3244 memset(levels, 0, level_array_size); 3244 3245 ··· 3286 3285 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) * 3287 3286 SMU7_MAX_LEVELS_MEMORY; 3288 3287 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; 3289 - u32 i, ret; 3288 + int ret; 3289 + u32 i; 3290 3290 3291 3291 memset(levels, 0, level_array_size); 3292 3292 ··· 3438 3436 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = 3439 3437 allowed_sclk_vddc_table->entries[i].clk; 3440 3438 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = 3441 - (i == 0) ? true : false; 3439 + i == 0; 3442 3440 pi->dpm_table.sclk_table.count++; 3443 3441 } 3444 3442 } ··· 3451 3449 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = 3452 3450 allowed_mclk_table->entries[i].clk; 3453 3451 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = 3454 - (i == 0) ? true : false; 3452 + i == 0; 3455 3453 pi->dpm_table.mclk_table.count++; 3456 3454 } 3457 3455 } ··· 4489 4487 bool patch; 4490 4488 4491 4489 tmp = RREG32(MC_SEQ_MISC0); 4492 - patch = ((tmp & 0x0000f00) == 0x300) ? true : false; 4490 + patch = (tmp & 0x0000f00) == 0x300; 4493 4491 4494 4492 if (patch && 4495 4493 ((rdev->pdev->device == 0x67B0) ||
+264 -259
drivers/gpu/drm/radeon/evergreen_cs.c
··· 951 951 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 952 952 (u64)track->vgt_strmout_size[i]; 953 953 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 954 - DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", 955 - i, offset, 956 - radeon_bo_size(track->vgt_strmout_bo[i])); 954 + dev_warn_once(p->dev, "streamout %d bo too small: 0x%llx, 0x%lx\n", 955 + i, offset, 956 + radeon_bo_size(track->vgt_strmout_bo[i])); 957 957 return -EINVAL; 958 958 } 959 959 } else { 960 - dev_warn(p->dev, "No buffer for streamout %d\n", i); 960 + dev_warn_once(p->dev, "No buffer for streamout %d\n", i); 961 961 return -EINVAL; 962 962 } 963 963 } ··· 979 979 (tmp >> (i * 4)) & 0xF) { 980 980 /* at least one component is enabled */ 981 981 if (track->cb_color_bo[i] == NULL) { 982 - dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 983 - __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 982 + dev_warn_once(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 983 + __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 984 984 return -EINVAL; 985 985 } 986 986 /* check cb */ ··· 1056 1056 case EVERGREEN_VLINE_START_END: 1057 1057 r = evergreen_cs_packet_parse_vline(p); 1058 1058 if (r) { 1059 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1060 - idx, reg); 1059 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1060 + idx, reg); 1061 1061 return r; 1062 1062 } 1063 1063 break; ··· 1143 1143 case SQ_VSTMP_RING_BASE: 1144 1144 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1145 1145 if (r) { 1146 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1147 - "0x%04X\n", reg); 1146 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1147 + "0x%04X\n", reg); 1148 1148 return -EINVAL; 1149 1149 } 1150 1150 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1155 1155 break; 1156 1156 case CAYMAN_DB_EQAA: 1157 1157 if (p->rdev->family < CHIP_CAYMAN) { 1158 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1159 - "0x%04X\n", reg); 1158 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1159 + "0x%04X\n", reg); 1160 1160 return -EINVAL; 1161 1161 } 1162 1162 break; 1163 1163 case CAYMAN_DB_DEPTH_INFO: 1164 1164 if (p->rdev->family < CHIP_CAYMAN) { 1165 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1166 - "0x%04X\n", reg); 1165 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1166 + "0x%04X\n", reg); 1167 1167 return -EINVAL; 1168 1168 } 1169 1169 break; ··· 1172 1172 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1173 1173 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1174 1174 if (r) { 1175 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1176 - "0x%04X\n", reg); 1175 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1176 + "0x%04X\n", reg); 1177 1177 return -EINVAL; 1178 1178 } 1179 1179 ib[idx] &= ~Z_ARRAY_MODE(0xf); ··· 1214 1214 case DB_Z_READ_BASE: 1215 1215 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1216 1216 if (r) { 1217 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1218 - "0x%04X\n", reg); 1217 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1218 + "0x%04X\n", reg); 1219 1219 return -EINVAL; 1220 1220 } 1221 1221 track->db_z_read_offset = radeon_get_ib_value(p, idx); ··· 1226 1226 case DB_Z_WRITE_BASE: 1227 1227 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1228 1228 if (r) { 1229 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1230 - "0x%04X\n", reg); 1229 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1230 + "0x%04X\n", reg); 1231 1231 return -EINVAL; 1232 1232 } 1233 1233 track->db_z_write_offset = radeon_get_ib_value(p, idx); ··· 1238 1238 case DB_STENCIL_READ_BASE: 1239 1239 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1240 1240 if (r) { 1241 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1242 - "0x%04X\n", reg); 1241 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1242 + "0x%04X\n", reg); 1243 1243 return -EINVAL; 1244 1244 } 1245 1245 track->db_s_read_offset = radeon_get_ib_value(p, idx); ··· 1250 1250 case DB_STENCIL_WRITE_BASE: 1251 1251 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1252 1252 if (r) { 1253 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1254 - "0x%04X\n", reg); 1253 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1254 + "0x%04X\n", reg); 1255 1255 return -EINVAL; 1256 1256 } 1257 1257 track->db_s_write_offset = radeon_get_ib_value(p, idx); ··· 1273 1273 case VGT_STRMOUT_BUFFER_BASE_3: 1274 1274 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1275 1275 if (r) { 1276 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1277 - "0x%04X\n", reg); 1276 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1277 + "0x%04X\n", reg); 1278 1278 return -EINVAL; 1279 1279 } 1280 1280 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; ··· 1295 1295 case CP_COHER_BASE: 1296 1296 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1297 1297 if (r) { 1298 - dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1299 - "0x%04X\n", reg); 1298 + dev_warn_once(p->dev, "missing reloc for CP_COHER_BASE " 1299 + "0x%04X\n", reg); 1300 1300 return -EINVAL; 1301 1301 } 1302 1302 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1311 1311 break; 1312 1312 case PA_SC_AA_CONFIG: 1313 1313 if (p->rdev->family >= CHIP_CAYMAN) { 1314 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1315 - "0x%04X\n", reg); 1314 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1315 + "0x%04X\n", reg); 1316 1316 return -EINVAL; 1317 1317 } 1318 1318 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; ··· 1320 1320 break; 1321 1321 case CAYMAN_PA_SC_AA_CONFIG: 1322 1322 if (p->rdev->family < CHIP_CAYMAN) { 1323 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1324 - "0x%04X\n", reg); 1323 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1324 + "0x%04X\n", reg); 1325 1325 return -EINVAL; 1326 1326 } 1327 1327 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; ··· 1360 1360 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1361 1361 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1362 1362 if (r) { 1363 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1364 - "0x%04X\n", reg); 1363 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1364 + "0x%04X\n", reg); 1365 1365 return -EINVAL; 1366 1366 } 1367 1367 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); ··· 1378 1378 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1379 1379 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1380 1380 if (r) { 1381 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1382 - "0x%04X\n", reg); 1381 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1382 + "0x%04X\n", reg); 1383 1383 return -EINVAL; 1384 1384 } 1385 1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); ··· 1439 1439 case CB_COLOR7_ATTRIB: 1440 1440 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1441 1441 if (r) { 1442 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1443 - "0x%04X\n", reg); 1442 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1443 + "0x%04X\n", reg); 1444 1444 return -EINVAL; 1445 1445 } 1446 1446 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { ··· 1467 1467 case CB_COLOR11_ATTRIB: 1468 1468 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1469 1469 if (r) { 1470 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1471 - "0x%04X\n", reg); 1470 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1471 + "0x%04X\n", reg); 1472 1472 return -EINVAL; 1473 1473 } 1474 1474 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { ··· 1555 1555 case CB_COLOR7_BASE: 1556 1556 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1557 1557 if (r) { 1558 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1559 - "0x%04X\n", reg); 1558 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1559 + "0x%04X\n", reg); 1560 1560 return -EINVAL; 1561 1561 } 1562 1562 tmp = (reg - CB_COLOR0_BASE) / 0x3c; ··· 1571 1571 case CB_COLOR11_BASE: 1572 1572 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1573 1573 if (r) { 1574 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1575 - "0x%04X\n", reg); 1574 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1575 + "0x%04X\n", reg); 1576 1576 return -EINVAL; 1577 1577 } 1578 1578 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; ··· 1584 1584 case DB_HTILE_DATA_BASE: 1585 1585 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1586 1586 if (r) { 1587 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1588 - "0x%04X\n", reg); 1587 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1588 + "0x%04X\n", reg); 1589 1589 return -EINVAL; 1590 1590 } 1591 1591 track->htile_offset = radeon_get_ib_value(p, idx); ··· 1702 1702 case SQ_ALU_CONST_CACHE_LS_15: 1703 1703 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1704 1704 if (r) { 1705 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1706 - "0x%04X\n", reg); 1705 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1706 + "0x%04X\n", reg); 1707 1707 return -EINVAL; 1708 1708 } 1709 1709 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1710 1710 break; 1711 1711 case SX_MEMORY_EXPORT_BASE: 1712 1712 if (p->rdev->family >= CHIP_CAYMAN) { 1713 - dev_warn(p->dev, "bad SET_CONFIG_REG " 1714 - "0x%04X\n", reg); 1713 + dev_warn_once(p->dev, "bad SET_CONFIG_REG " 1714 + "0x%04X\n", reg); 1715 1715 return -EINVAL; 1716 1716 } 1717 1717 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1718 1718 if (r) { 1719 - dev_warn(p->dev, "bad SET_CONFIG_REG " 1720 - "0x%04X\n", reg); 1719 + dev_warn_once(p->dev, "bad SET_CONFIG_REG " 1720 + "0x%04X\n", reg); 1721 1721 return -EINVAL; 1722 1722 } 1723 1723 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); 1724 1724 break; 1725 1725 case CAYMAN_SX_SCATTER_EXPORT_BASE: 1726 1726 if (p->rdev->family < CHIP_CAYMAN) { 1727 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1728 - "0x%04X\n", reg); 1727 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1728 + "0x%04X\n", reg); 1729 1729 return -EINVAL; 1730 1730 } 1731 1731 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1732 1732 if (r) { 1733 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1734 - "0x%04X\n", reg); 1733 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1734 + "0x%04X\n", reg); 1735 1735 return -EINVAL; 1736 1736 } 1737 1737 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1740 1740 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1741 1741 break; 1742 1742 default: 1743 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1743 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1744 1744 return -EINVAL; 1745 1745 } 1746 1746 return 0; ··· 1795 1795 uint64_t offset; 1796 1796 1797 1797 if (pkt->count != 1) { 1798 - DRM_ERROR("bad SET PREDICATION\n"); 1798 + dev_warn_once(p->dev, "bad SET PREDICATION\n"); 1799 1799 return -EINVAL; 1800 1800 } 1801 1801 ··· 1807 1807 return 0; 1808 1808 1809 1809 if (pred_op > 2) { 1810 - DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1810 + dev_warn_once(p->dev, "bad SET PREDICATION operation %d\n", pred_op); 1811 1811 return -EINVAL; 1812 1812 } 1813 1813 1814 1814 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1815 1815 if (r) { 1816 - DRM_ERROR("bad SET PREDICATION\n"); 1816 + dev_warn_once(p->dev, "bad SET PREDICATION\n"); 1817 1817 return -EINVAL; 1818 1818 } 1819 1819 ··· 1827 1827 break; 1828 1828 case PACKET3_CONTEXT_CONTROL: 1829 1829 if (pkt->count != 1) { 1830 - DRM_ERROR("bad CONTEXT_CONTROL\n"); 1830 + dev_warn_once(p->dev, "bad CONTEXT_CONTROL\n"); 1831 1831 return -EINVAL; 1832 1832 } 1833 1833 break; ··· 1835 1835 case PACKET3_NUM_INSTANCES: 1836 1836 case PACKET3_CLEAR_STATE: 1837 1837 if (pkt->count) { 1838 - DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1838 + dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1839 1839 return -EINVAL; 1840 1840 } 1841 1841 break; 1842 1842 case CAYMAN_PACKET3_DEALLOC_STATE: 1843 1843 if (p->rdev->family < CHIP_CAYMAN) { 1844 - DRM_ERROR("bad PACKET3_DEALLOC_STATE\n"); 1844 + dev_warn_once(p->dev, "bad PACKET3_DEALLOC_STATE\n"); 1845 1845 return -EINVAL; 1846 1846 } 1847 1847 if (pkt->count) { 1848 - DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1848 + dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1849 1849 return -EINVAL; 1850 1850 } 1851 1851 break; ··· 1854 1854 uint64_t offset; 1855 1855 1856 1856 if (pkt->count != 1) { 1857 - DRM_ERROR("bad INDEX_BASE\n"); 1857 + dev_warn_once(p->dev, "bad INDEX_BASE\n"); 1858 1858 return -EINVAL; 1859 1859 } 1860 1860 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1861 1861 if (r) { 1862 - DRM_ERROR("bad INDEX_BASE\n"); 1862 + dev_warn_once(p->dev, "bad INDEX_BASE\n"); 1863 1863 return -EINVAL; 1864 1864 } 1865 1865 ··· 1872 1872 1873 1873 r = evergreen_cs_track_check(p); 1874 1874 if (r) { 1875 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1875 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1876 1876 return r; 1877 1877 } 1878 1878 break; ··· 1880 1880 case PACKET3_INDEX_BUFFER_SIZE: 1881 1881 { 1882 1882 if (pkt->count != 0) { 1883 - DRM_ERROR("bad INDEX_BUFFER_SIZE\n"); 1883 + dev_warn_once(p->dev, "bad INDEX_BUFFER_SIZE\n"); 1884 1884 return -EINVAL; 1885 1885 } 1886 1886 break; ··· 1889 1889 { 1890 1890 uint64_t offset; 1891 1891 if (pkt->count != 3) { 1892 - DRM_ERROR("bad DRAW_INDEX\n"); 1892 + dev_warn_once(p->dev, "bad DRAW_INDEX\n"); 1893 1893 return -EINVAL; 1894 1894 } 1895 1895 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1896 1896 if (r) { 1897 - DRM_ERROR("bad DRAW_INDEX\n"); 1897 + dev_warn_once(p->dev, "bad DRAW_INDEX\n"); 1898 1898 return -EINVAL; 1899 1899 } 1900 1900 ··· 1907 1907 1908 1908 r = evergreen_cs_track_check(p); 1909 1909 if (r) { 1910 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1910 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1911 1911 return r; 1912 1912 } 1913 1913 break; ··· 1917 1917 uint64_t offset; 1918 1918 1919 1919 if (pkt->count != 4) { 1920 - DRM_ERROR("bad DRAW_INDEX_2\n"); 1920 + dev_warn_once(p->dev, "bad DRAW_INDEX_2\n"); 1921 1921 return -EINVAL; 1922 1922 } 1923 1923 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1924 1924 if (r) { 1925 - DRM_ERROR("bad DRAW_INDEX_2\n"); 1925 + dev_warn_once(p->dev, "bad DRAW_INDEX_2\n"); 1926 1926 return -EINVAL; 1927 1927 } 1928 1928 ··· 1935 1935 1936 1936 r = evergreen_cs_track_check(p); 1937 1937 if (r) { 1938 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1938 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1939 1939 return r; 1940 1940 } 1941 1941 break; 1942 1942 } 1943 1943 case PACKET3_DRAW_INDEX_AUTO: 1944 1944 if (pkt->count != 1) { 1945 - DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1945 + dev_warn_once(p->dev, "bad DRAW_INDEX_AUTO\n"); 1946 1946 return -EINVAL; 1947 1947 } 1948 1948 r = evergreen_cs_track_check(p); 1949 1949 if (r) { 1950 - dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1950 + dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1951 1951 return r; 1952 1952 } 1953 1953 break; 1954 1954 case PACKET3_DRAW_INDEX_MULTI_AUTO: 1955 1955 if (pkt->count != 2) { 1956 - DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n"); 1956 + dev_warn_once(p->dev, "bad DRAW_INDEX_MULTI_AUTO\n"); 1957 1957 return -EINVAL; 1958 1958 } 1959 1959 r = evergreen_cs_track_check(p); 1960 1960 if (r) { 1961 - dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1961 + dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1962 1962 return r; 1963 1963 } 1964 1964 break; 1965 1965 case PACKET3_DRAW_INDEX_IMMD: 1966 1966 if (pkt->count < 2) { 1967 - DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1967 + dev_warn_once(p->dev, "bad DRAW_INDEX_IMMD\n"); 1968 1968 return -EINVAL; 1969 1969 } 1970 1970 r = evergreen_cs_track_check(p); 1971 1971 if (r) { 1972 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1972 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1973 1973 return r; 1974 1974 } 1975 1975 break; 1976 1976 case PACKET3_DRAW_INDEX_OFFSET: 1977 1977 if (pkt->count != 2) { 1978 - DRM_ERROR("bad DRAW_INDEX_OFFSET\n"); 1978 + dev_warn_once(p->dev, "bad DRAW_INDEX_OFFSET\n"); 1979 1979 return -EINVAL; 1980 1980 } 1981 1981 r = evergreen_cs_track_check(p); 1982 1982 if (r) { 1983 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1983 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1984 1984 return r; 1985 1985 } 1986 1986 break; 1987 1987 case PACKET3_DRAW_INDEX_OFFSET_2: 1988 1988 if (pkt->count != 3) { 1989 - DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n"); 1989 + dev_warn_once(p->dev, "bad DRAW_INDEX_OFFSET_2\n"); 1990 1990 return -EINVAL; 1991 1991 } 1992 1992 r = evergreen_cs_track_check(p); 1993 1993 if (r) { 1994 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1994 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1995 1995 return r; 1996 1996 } 1997 1997 break; ··· 2005 2005 4 ADDRESS_HI Bits [31:8] - Reserved. Bits [7:0] - Upper bits of Address [47:32] 2006 2006 */ 2007 2007 if (pkt->count != 2) { 2008 - DRM_ERROR("bad SET_BASE\n"); 2008 + dev_warn_once(p->dev, "bad SET_BASE\n"); 2009 2009 return -EINVAL; 2010 2010 } 2011 2011 2012 2012 /* currently only supporting setting indirect draw buffer base address */ 2013 2013 if (idx_value != 1) { 2014 - DRM_ERROR("bad SET_BASE\n"); 2014 + dev_warn_once(p->dev, "bad SET_BASE\n"); 2015 2015 return -EINVAL; 2016 2016 } 2017 2017 2018 2018 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2019 2019 if (r) { 2020 - DRM_ERROR("bad SET_BASE\n"); 2020 + dev_warn_once(p->dev, "bad SET_BASE\n"); 2021 2021 return -EINVAL; 2022 2022 } 2023 2023 ··· 2039 2039 3 DRAW_INITIATOR Draw Initiator Register. Written to the VGT_DRAW_INITIATOR register for the assigned context 2040 2040 */ 2041 2041 if (pkt->count != 1) { 2042 - DRM_ERROR("bad DRAW_INDIRECT\n"); 2042 + dev_warn_once(p->dev, "bad DRAW_INDIRECT\n"); 2043 2043 return -EINVAL; 2044 2044 } 2045 2045 2046 2046 if (idx_value + size > track->indirect_draw_buffer_size) { 2047 - dev_warn(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n", 2048 - idx_value, size, track->indirect_draw_buffer_size); 2047 + dev_warn_once(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n", 2048 + idx_value, size, track->indirect_draw_buffer_size); 2049 2049 return -EINVAL; 2050 2050 } 2051 2051 2052 2052 r = evergreen_cs_track_check(p); 2053 2053 if (r) { 2054 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2054 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2055 2055 return r; 2056 2056 } 2057 2057 break; 2058 2058 } 2059 2059 case PACKET3_DISPATCH_DIRECT: 2060 2060 if (pkt->count != 3) { 2061 - DRM_ERROR("bad DISPATCH_DIRECT\n"); 2061 + dev_warn_once(p->dev, "bad DISPATCH_DIRECT\n"); 2062 2062 return -EINVAL; 2063 2063 } 2064 2064 r = evergreen_cs_track_check(p); 2065 2065 if (r) { 2066 - dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2066 + dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2067 2067 return r; 2068 2068 } 2069 2069 break; 2070 2070 case PACKET3_DISPATCH_INDIRECT: 2071 2071 if (pkt->count != 1) { 2072 - DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2072 + dev_warn_once(p->dev, "bad DISPATCH_INDIRECT\n"); 2073 2073 return -EINVAL; 2074 2074 } 2075 2075 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2076 2076 if (r) { 2077 - DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2077 + dev_warn_once(p->dev, "bad DISPATCH_INDIRECT\n"); 2078 2078 return -EINVAL; 2079 2079 } 2080 2080 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); 2081 2081 r = evergreen_cs_track_check(p); 2082 2082 if (r) { 2083 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2083 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2084 2084 return r; 2085 2085 } 2086 2086 break; 2087 2087 case PACKET3_WAIT_REG_MEM: 2088 2088 if (pkt->count != 5) { 2089 - DRM_ERROR("bad WAIT_REG_MEM\n"); 2089 + dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); 2090 2090 return -EINVAL; 2091 2091 } 2092 2092 /* bit 4 is reg (0) or mem (1) */ ··· 2095 2095 2096 2096 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2097 2097 if (r) { 2098 - DRM_ERROR("bad WAIT_REG_MEM\n"); 2098 + dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); 2099 2099 return -EINVAL; 2100 2100 } 2101 2101 ··· 2106 2106 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); 2107 2107 ib[idx+2] = upper_32_bits(offset) & 0xff; 2108 2108 } else if (idx_value & 0x100) { 2109 - DRM_ERROR("cannot use PFP on REG wait\n"); 2109 + dev_warn_once(p->dev, "cannot use PFP on REG wait\n"); 2110 2110 return -EINVAL; 2111 2111 } 2112 2112 break; ··· 2115 2115 u32 command, size, info; 2116 2116 u64 offset, tmp; 2117 2117 if (pkt->count != 4) { 2118 - DRM_ERROR("bad CP DMA\n"); 2118 + dev_warn_once(p->dev, "bad CP DMA\n"); 2119 2119 return -EINVAL; 2120 2120 } 2121 2121 command = radeon_get_ib_value(p, idx+4); ··· 2129 2129 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ 2130 2130 /* non mem to mem copies requires dw aligned count */ 2131 2131 if (size % 4) { 2132 - DRM_ERROR("CP DMA command requires dw count alignment\n"); 2132 + dev_warn_once(p->dev, "CP DMA command requires dw count alignment\n"); 2133 2133 return -EINVAL; 2134 2134 } 2135 2135 } ··· 2137 2137 /* src address space is register */ 2138 2138 /* GDS is ok */ 2139 2139 if (((info & 0x60000000) >> 29) != 1) { 2140 - DRM_ERROR("CP DMA SAS not supported\n"); 2140 + dev_warn_once(p->dev, "CP DMA SAS not supported\n"); 2141 2141 return -EINVAL; 2142 2142 } 2143 2143 } else { 2144 2144 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2145 - DRM_ERROR("CP DMA SAIC only supported for registers\n"); 2145 + dev_warn_once(p->dev, "CP DMA SAIC only supported for registers\n"); 2146 2146 return -EINVAL; 2147 2147 } 2148 2148 /* src address space is memory */ 2149 2149 if (((info & 0x60000000) >> 29) == 0) { 2150 2150 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2151 2151 if (r) { 2152 - DRM_ERROR("bad CP DMA SRC\n"); 2152 + dev_warn_once(p->dev, "bad CP DMA SRC\n"); 2153 2153 return -EINVAL; 2154 2154 } 2155 2155 ··· 2159 2159 offset = reloc->gpu_offset + tmp; 2160 2160 2161 2161 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2162 - dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", 2163 - tmp + size, radeon_bo_size(reloc->robj)); 2162 + dev_warn_once(p->dev, "CP DMA src buffer too small (%llu %lu)\n", 2163 + tmp + size, radeon_bo_size(reloc->robj)); 2164 2164 return -EINVAL; 2165 2165 } 2166 2166 2167 2167 ib[idx] = offset; 2168 2168 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2169 2169 } else if (((info & 0x60000000) >> 29) != 2) { 2170 - DRM_ERROR("bad CP DMA SRC_SEL\n"); 2170 + dev_warn_once(p->dev, "bad CP DMA SRC_SEL\n"); 2171 2171 return -EINVAL; 2172 2172 } 2173 2173 } ··· 2175 2175 /* dst address space is register */ 2176 2176 /* GDS is ok */ 2177 2177 if (((info & 0x00300000) >> 20) != 1) { 2178 - DRM_ERROR("CP DMA DAS not supported\n"); 2178 + dev_warn_once(p->dev, "CP DMA DAS not supported\n"); 2179 2179 return -EINVAL; 2180 2180 } 2181 2181 } else { 2182 2182 /* dst address space is memory */ 2183 2183 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2184 - DRM_ERROR("CP DMA DAIC only supported for registers\n"); 2184 + dev_warn_once(p->dev, "CP DMA DAIC only supported for registers\n"); 2185 2185 return -EINVAL; 2186 2186 } 2187 2187 if (((info & 0x00300000) >> 20) == 0) { 2188 2188 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2189 2189 if (r) { 2190 - DRM_ERROR("bad CP DMA DST\n"); 2190 + dev_warn_once(p->dev, "bad CP DMA DST\n"); 2191 2191 return -EINVAL; 2192 2192 } 2193 2193 ··· 2197 2197 offset = reloc->gpu_offset + tmp; 2198 2198 2199 2199 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 2200 - dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", 2201 - tmp + size, radeon_bo_size(reloc->robj)); 2200 + dev_warn_once(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", 2201 + tmp + size, radeon_bo_size(reloc->robj)); 2202 2202 return -EINVAL; 2203 2203 } 2204 2204 2205 2205 ib[idx+2] = offset; 2206 2206 ib[idx+3] = upper_32_bits(offset) & 0xff; 2207 2207 } else { 2208 - DRM_ERROR("bad CP DMA DST_SEL\n"); 2208 + dev_warn_once(p->dev, "bad CP DMA DST_SEL\n"); 2209 2209 return -EINVAL; 2210 2210 } 2211 2211 } ··· 2213 2213 } 2214 2214 case PACKET3_PFP_SYNC_ME: 2215 2215 if (pkt->count) { 2216 - DRM_ERROR("bad PFP_SYNC_ME\n"); 2216 + dev_warn_once(p->dev, "bad PFP_SYNC_ME\n"); 2217 2217 return -EINVAL; 2218 2218 } 2219 2219 break; 2220 2220 case PACKET3_SURFACE_SYNC: 2221 2221 if (pkt->count != 3) { 2222 - DRM_ERROR("bad SURFACE_SYNC\n"); 2222 + dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); 2223 2223 return -EINVAL; 2224 2224 } 2225 2225 /* 0xffffffff/0x0 is flush all cache flag */ ··· 2227 2227 radeon_get_ib_value(p, idx + 2) != 0) { 2228 2228 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2229 2229 if (r) { 2230 - DRM_ERROR("bad SURFACE_SYNC\n"); 2230 + dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); 2231 2231 return -EINVAL; 2232 2232 } 2233 2233 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 2235 2235 break; 2236 2236 case PACKET3_EVENT_WRITE: 2237 2237 if (pkt->count != 2 && pkt->count != 0) { 2238 - DRM_ERROR("bad EVENT_WRITE\n"); 2238 + dev_warn_once(p->dev, "bad EVENT_WRITE\n"); 2239 2239 return -EINVAL; 2240 2240 } 2241 2241 if (pkt->count) { ··· 2243 2243 2244 2244 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2245 2245 if (r) { 2246 - DRM_ERROR("bad EVENT_WRITE\n"); 2246 + dev_warn_once(p->dev, "bad EVENT_WRITE\n"); 2247 2247 return -EINVAL; 2248 2248 } 2249 2249 offset = reloc->gpu_offset + ··· 2259 2259 uint64_t offset; 2260 2260 2261 2261 if (pkt->count != 4) { 2262 - DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2262 + dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); 2263 2263 return -EINVAL; 2264 2264 } 2265 2265 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2266 2266 if (r) { 2267 - DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2267 + dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); 2268 2268 return -EINVAL; 2269 2269 } 2270 2270 ··· 2281 2281 uint64_t offset; 2282 2282 2283 2283 if (pkt->count != 3) { 2284 - DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2284 + dev_warn_once(p->dev, "bad EVENT_WRITE_EOS\n"); 2285 2285 return -EINVAL; 2286 2286 } 2287 2287 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2288 2288 if (r) { 2289 - DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2289 + dev_warn_once(p->dev, "bad EVENT_WRITE_EOS\n"); 2290 2290 return -EINVAL; 2291 2291 } 2292 2292 ··· 2304 2304 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2305 2305 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2306 2306 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2307 - DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2307 + dev_warn_once(p->dev, "bad PACKET3_SET_CONFIG_REG\n"); 2308 2308 return -EINVAL; 2309 2309 } 2310 2310 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { ··· 2321 2321 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || 2322 2322 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 2323 2323 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 2324 - DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 2324 + dev_warn_once(p->dev, "bad PACKET3_SET_CONTEXT_REG\n"); 2325 2325 return -EINVAL; 2326 2326 } 2327 2327 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { ··· 2334 2334 break; 2335 2335 case PACKET3_SET_RESOURCE: 2336 2336 if (pkt->count % 8) { 2337 - DRM_ERROR("bad SET_RESOURCE\n"); 2337 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 2338 2338 return -EINVAL; 2339 2339 } 2340 2340 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; ··· 2342 2342 if ((start_reg < PACKET3_SET_RESOURCE_START) || 2343 2343 (start_reg >= PACKET3_SET_RESOURCE_END) || 2344 2344 (end_reg >= PACKET3_SET_RESOURCE_END)) { 2345 - DRM_ERROR("bad SET_RESOURCE\n"); 2345 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 2346 2346 return -EINVAL; 2347 2347 } 2348 2348 for (i = 0; i < (pkt->count / 8); i++) { ··· 2355 2355 /* tex base */ 2356 2356 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2357 2357 if (r) { 2358 - DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2358 + dev_warn_once(p->dev, "bad SET_RESOURCE (tex)\n"); 2359 2359 return -EINVAL; 2360 2360 } 2361 2361 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { ··· 2392 2392 } else { 2393 2393 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2394 2394 if (r) { 2395 - DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2395 + dev_warn_once(p->dev, "bad SET_RESOURCE (tex)\n"); 2396 2396 return -EINVAL; 2397 2397 } 2398 2398 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 2411 2411 /* vtx base */ 2412 2412 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2413 2413 if (r) { 2414 - DRM_ERROR("bad SET_RESOURCE (vtx)\n"); 2414 + dev_warn_once(p->dev, "bad SET_RESOURCE (vtx)\n"); 2415 2415 return -EINVAL; 2416 2416 } 2417 2417 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); 2418 2418 size = radeon_get_ib_value(p, idx+1+(i*8)+1); 2419 2419 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2420 2420 /* force size to size of the buffer */ 2421 - dev_warn_ratelimited(p->dev, "vbo resource seems too big for the bo\n"); 2421 + dev_warn_once(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2422 + size + offset, radeon_bo_size(reloc->robj)); 2422 2423 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; 2423 2424 } 2424 2425 ··· 2432 2431 case SQ_TEX_VTX_INVALID_TEXTURE: 2433 2432 case SQ_TEX_VTX_INVALID_BUFFER: 2434 2433 default: 2435 - DRM_ERROR("bad SET_RESOURCE\n"); 2434 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 2436 2435 return -EINVAL; 2437 2436 } 2438 2437 } ··· 2446 2445 if ((start_reg < PACKET3_SET_BOOL_CONST_START) || 2447 2446 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2448 2447 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2449 - DRM_ERROR("bad SET_BOOL_CONST\n"); 2448 + dev_warn_once(p->dev, "bad SET_BOOL_CONST\n"); 2450 2449 return -EINVAL; 2451 2450 } 2452 2451 break; ··· 2456 2455 if ((start_reg < PACKET3_SET_LOOP_CONST_START) || 2457 2456 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2458 2457 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2459 - DRM_ERROR("bad SET_LOOP_CONST\n"); 2458 + dev_warn_once(p->dev, "bad SET_LOOP_CONST\n"); 2460 2459 return -EINVAL; 2461 2460 } 2462 2461 break; ··· 2466 2465 if ((start_reg < PACKET3_SET_CTL_CONST_START) || 2467 2466 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2468 2467 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2469 - DRM_ERROR("bad SET_CTL_CONST\n"); 2468 + dev_warn_once(p->dev, "bad SET_CTL_CONST\n"); 2470 2469 return -EINVAL; 2471 2470 } 2472 2471 break; 2473 2472 case PACKET3_SET_SAMPLER: 2474 2473 if (pkt->count % 3) { 2475 - DRM_ERROR("bad SET_SAMPLER\n"); 2474 + dev_warn_once(p->dev, "bad SET_SAMPLER\n"); 2476 2475 return -EINVAL; 2477 2476 } 2478 2477 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START; ··· 2480 2479 if ((start_reg < PACKET3_SET_SAMPLER_START) || 2481 2480 (start_reg >= PACKET3_SET_SAMPLER_END) || 2482 2481 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2483 - DRM_ERROR("bad SET_SAMPLER\n"); 2482 + dev_warn_once(p->dev, "bad SET_SAMPLER\n"); 2484 2483 return -EINVAL; 2485 2484 } 2486 2485 break; 2487 2486 case PACKET3_STRMOUT_BUFFER_UPDATE: 2488 2487 if (pkt->count != 4) { 2489 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2488 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2490 2489 return -EINVAL; 2491 2490 } 2492 2491 /* Updating memory at DST_ADDRESS. */ ··· 2494 2493 u64 offset; 2495 2494 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2496 2495 if (r) { 2497 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2496 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2498 2497 return -EINVAL; 2499 2498 } 2500 2499 offset = radeon_get_ib_value(p, idx+1); 2501 2500 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2502 2501 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2503 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2504 - offset + 4, radeon_bo_size(reloc->robj)); 2502 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2503 + offset + 4, radeon_bo_size(reloc->robj)); 2505 2504 return -EINVAL; 2506 2505 } 2507 2506 offset += reloc->gpu_offset; ··· 2513 2512 u64 offset; 2514 2513 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2515 2514 if (r) { 2516 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2515 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2517 2516 return -EINVAL; 2518 2517 } 2519 2518 offset = radeon_get_ib_value(p, idx+3); 2520 2519 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2521 2520 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2522 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2523 - offset + 4, radeon_bo_size(reloc->robj)); 2521 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2522 + offset + 4, radeon_bo_size(reloc->robj)); 2524 2523 return -EINVAL; 2525 2524 } 2526 2525 offset += reloc->gpu_offset; ··· 2533 2532 u64 offset; 2534 2533 2535 2534 if (pkt->count != 3) { 2536 - DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2535 + dev_warn_once(p->dev, "bad MEM_WRITE (invalid count)\n"); 2537 2536 return -EINVAL; 2538 2537 } 2539 2538 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2540 2539 if (r) { 2541 - DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2540 + dev_warn_once(p->dev, "bad MEM_WRITE (missing reloc)\n"); 2542 2541 return -EINVAL; 2543 2542 } 2544 2543 offset = radeon_get_ib_value(p, idx+0); 2545 2544 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2546 2545 if (offset & 0x7) { 2547 - DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2546 + dev_warn_once(p->dev, "bad MEM_WRITE (address not qwords aligned)\n"); 2548 2547 return -EINVAL; 2549 2548 } 2550 2549 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2551 - DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", 2552 - offset + 8, radeon_bo_size(reloc->robj)); 2550 + dev_warn_once(p->dev, "bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", 2551 + offset + 8, radeon_bo_size(reloc->robj)); 2553 2552 return -EINVAL; 2554 2553 } 2555 2554 offset += reloc->gpu_offset; ··· 2559 2558 } 2560 2559 case PACKET3_COPY_DW: 2561 2560 if (pkt->count != 4) { 2562 - DRM_ERROR("bad COPY_DW (invalid count)\n"); 2561 + dev_warn_once(p->dev, "bad COPY_DW (invalid count)\n"); 2563 2562 return -EINVAL; 2564 2563 } 2565 2564 if (idx_value & 0x1) { ··· 2567 2566 /* SRC is memory. */ 2568 2567 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2569 2568 if (r) { 2570 - DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2569 + dev_warn_once(p->dev, "bad COPY_DW (missing src reloc)\n"); 2571 2570 return -EINVAL; 2572 2571 } 2573 2572 offset = radeon_get_ib_value(p, idx+1); 2574 2573 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2575 2574 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2576 - DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2577 - offset + 4, radeon_bo_size(reloc->robj)); 2575 + dev_warn_once(p->dev, "bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2576 + offset + 4, radeon_bo_size(reloc->robj)); 2578 2577 return -EINVAL; 2579 2578 } 2580 2579 offset += reloc->gpu_offset; ··· 2584 2583 /* SRC is a reg. */ 2585 2584 reg = radeon_get_ib_value(p, idx+1) << 2; 2586 2585 if (!evergreen_is_safe_reg(p, reg)) { 2587 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2588 - reg, idx + 1); 2586 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", 2587 + reg, idx + 1); 2589 2588 return -EINVAL; 2590 2589 } 2591 2590 } ··· 2594 2593 /* DST is memory. */ 2595 2594 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2596 2595 if (r) { 2597 - DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2596 + dev_warn_once(p->dev, "bad COPY_DW (missing dst reloc)\n"); 2598 2597 return -EINVAL; 2599 2598 } 2600 2599 offset = radeon_get_ib_value(p, idx+3); 2601 2600 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2602 2601 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2603 - DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2604 - offset + 4, radeon_bo_size(reloc->robj)); 2602 + dev_warn_once(p->dev, "bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2603 + offset + 4, radeon_bo_size(reloc->robj)); 2605 2604 return -EINVAL; 2606 2605 } 2607 2606 offset += reloc->gpu_offset; ··· 2611 2610 /* DST is a reg. */ 2612 2611 reg = radeon_get_ib_value(p, idx+3) << 2; 2613 2612 if (!evergreen_is_safe_reg(p, reg)) { 2614 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2615 - reg, idx + 3); 2613 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", 2614 + reg, idx + 3); 2616 2615 return -EINVAL; 2617 2616 } 2618 2617 } ··· 2623 2622 uint32_t allowed_reg_base; 2624 2623 uint32_t source_sel; 2625 2624 if (pkt->count != 2) { 2626 - DRM_ERROR("bad SET_APPEND_CNT (invalid count)\n"); 2625 + dev_warn_once(p->dev, "bad SET_APPEND_CNT (invalid count)\n"); 2627 2626 return -EINVAL; 2628 2627 } 2629 2628 ··· 2633 2632 2634 2633 areg = idx_value >> 16; 2635 2634 if (areg < allowed_reg_base || areg > (allowed_reg_base + 11)) { 2636 - dev_warn(p->dev, "forbidden register for append cnt 0x%08x at %d\n", 2637 - areg, idx); 2635 + dev_warn_once(p->dev, "forbidden register for append cnt 0x%08x at %d\n", 2636 + areg, idx); 2638 2637 return -EINVAL; 2639 2638 } 2640 2639 ··· 2644 2643 uint32_t swap; 2645 2644 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2646 2645 if (r) { 2647 - DRM_ERROR("bad SET_APPEND_CNT (missing reloc)\n"); 2646 + dev_warn_once(p->dev, "bad SET_APPEND_CNT (missing reloc)\n"); 2648 2647 return -EINVAL; 2649 2648 } 2650 2649 offset = radeon_get_ib_value(p, idx + 1); ··· 2657 2656 ib[idx+1] = (offset & 0xfffffffc) | swap; 2658 2657 ib[idx+2] = upper_32_bits(offset) & 0xff; 2659 2658 } else { 2660 - DRM_ERROR("bad SET_APPEND_CNT (unsupported operation)\n"); 2659 + dev_warn_once(p->dev, "bad SET_APPEND_CNT (unsupported operation)\n"); 2661 2660 return -EINVAL; 2662 2661 } 2663 2662 break; ··· 2667 2666 u64 offset; 2668 2667 2669 2668 if (pkt->count != 2) { 2670 - DRM_ERROR("bad COND_EXEC (invalid count)\n"); 2669 + dev_warn_once(p->dev, "bad COND_EXEC (invalid count)\n"); 2671 2670 return -EINVAL; 2672 2671 } 2673 2672 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2674 2673 if (r) { 2675 - DRM_ERROR("bad COND_EXEC (missing reloc)\n"); 2674 + dev_warn_once(p->dev, "bad COND_EXEC (missing reloc)\n"); 2676 2675 return -EINVAL; 2677 2676 } 2678 2677 offset = radeon_get_ib_value(p, idx + 0); 2679 2678 offset += ((u64)(radeon_get_ib_value(p, idx + 1) & 0xff)) << 32UL; 2680 2679 if (offset & 0x7) { 2681 - DRM_ERROR("bad COND_EXEC (address not qwords aligned)\n"); 2680 + dev_warn_once(p->dev, "bad COND_EXEC (address not qwords aligned)\n"); 2682 2681 return -EINVAL; 2683 2682 } 2684 2683 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2685 - DRM_ERROR("bad COND_EXEC bo too small: 0x%llx, 0x%lx\n", 2686 - offset + 8, radeon_bo_size(reloc->robj)); 2684 + dev_warn_once(p->dev, "bad COND_EXEC bo too small: 0x%llx, 0x%lx\n", 2685 + offset + 8, radeon_bo_size(reloc->robj)); 2687 2686 return -EINVAL; 2688 2687 } 2689 2688 offset += reloc->gpu_offset; ··· 2693 2692 } 2694 2693 case PACKET3_COND_WRITE: 2695 2694 if (pkt->count != 7) { 2696 - DRM_ERROR("bad COND_WRITE (invalid count)\n"); 2695 + dev_warn_once(p->dev, "bad COND_WRITE (invalid count)\n"); 2697 2696 return -EINVAL; 2698 2697 } 2699 2698 if (idx_value & 0x10) { ··· 2701 2700 /* POLL is memory. */ 2702 2701 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2703 2702 if (r) { 2704 - DRM_ERROR("bad COND_WRITE (missing src reloc)\n"); 2703 + dev_warn_once(p->dev, "bad COND_WRITE (missing src reloc)\n"); 2705 2704 return -EINVAL; 2706 2705 } 2707 2706 offset = radeon_get_ib_value(p, idx + 1); 2708 2707 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32; 2709 2708 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2710 - DRM_ERROR("bad COND_WRITE src bo too small: 0x%llx, 0x%lx\n", 2711 - offset + 8, radeon_bo_size(reloc->robj)); 2709 + dev_warn_once(p->dev, "bad COND_WRITE src bo too small: 0x%llx, 0x%lx\n", 2710 + offset + 8, radeon_bo_size(reloc->robj)); 2712 2711 return -EINVAL; 2713 2712 } 2714 2713 offset += reloc->gpu_offset; ··· 2718 2717 /* POLL is a reg. */ 2719 2718 reg = radeon_get_ib_value(p, idx + 1) << 2; 2720 2719 if (!evergreen_is_safe_reg(p, reg)) { 2721 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2722 - reg, idx + 1); 2720 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", 2721 + reg, idx + 1); 2723 2722 return -EINVAL; 2724 2723 } 2725 2724 } ··· 2728 2727 /* WRITE is memory. */ 2729 2728 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2730 2729 if (r) { 2731 - DRM_ERROR("bad COND_WRITE (missing dst reloc)\n"); 2730 + dev_warn_once(p->dev, "bad COND_WRITE (missing dst reloc)\n"); 2732 2731 return -EINVAL; 2733 2732 } 2734 2733 offset = radeon_get_ib_value(p, idx + 5); 2735 2734 offset += ((u64)(radeon_get_ib_value(p, idx + 6) & 0xff)) << 32; 2736 2735 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2737 - DRM_ERROR("bad COND_WRITE dst bo too small: 0x%llx, 0x%lx\n", 2738 - offset + 8, radeon_bo_size(reloc->robj)); 2736 + dev_warn_once(p->dev, "bad COND_WRITE dst bo too small: 0x%llx, 0x%lx\n", 2737 + offset + 8, radeon_bo_size(reloc->robj)); 2739 2738 return -EINVAL; 2740 2739 } 2741 2740 offset += reloc->gpu_offset; ··· 2745 2744 /* WRITE is a reg. */ 2746 2745 reg = radeon_get_ib_value(p, idx + 5) << 2; 2747 2746 if (!evergreen_is_safe_reg(p, reg)) { 2748 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", 2749 - reg, idx + 5); 2747 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", 2748 + reg, idx + 5); 2750 2749 return -EINVAL; 2751 2750 } 2752 2751 } ··· 2754 2753 case PACKET3_NOP: 2755 2754 break; 2756 2755 default: 2757 - DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2756 + dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); 2758 2757 return -EINVAL; 2759 2758 } 2760 2759 return 0; ··· 2854 2853 r = evergreen_packet3_check(p, &pkt); 2855 2854 break; 2856 2855 default: 2857 - DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2856 + dev_warn_once(p->dev, "Unknown packet type %d !\n", pkt.type); 2858 2857 kfree(p->track); 2859 2858 p->track = NULL; 2860 2859 return -EINVAL; ··· 2897 2896 2898 2897 do { 2899 2898 if (p->idx >= ib_chunk->length_dw) { 2900 - DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2901 - p->idx, ib_chunk->length_dw); 2899 + dev_warn_once(p->dev, "Can not parse packet at %d after CS end %d !\n", 2900 + p->idx, ib_chunk->length_dw); 2902 2901 return -EINVAL; 2903 2902 } 2904 2903 idx = p->idx; ··· 2911 2910 case DMA_PACKET_WRITE: 2912 2911 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2913 2912 if (r) { 2914 - DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2913 + dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); 2915 2914 return -EINVAL; 2916 2915 } 2917 2916 switch (sub_cmd) { ··· 2933 2932 p->idx += count + 3; 2934 2933 break; 2935 2934 default: 2936 - DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); 2935 + dev_warn_once(p->dev, "bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); 2937 2936 return -EINVAL; 2938 2937 } 2939 2938 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2940 - dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", 2941 - dst_offset, radeon_bo_size(dst_reloc->robj)); 2939 + dev_warn_once(p->dev, "DMA write buffer too small (%llu %lu)\n", 2940 + dst_offset, radeon_bo_size(dst_reloc->robj)); 2942 2941 return -EINVAL; 2943 2942 } 2944 2943 break; 2945 2944 case DMA_PACKET_COPY: 2946 2945 r = r600_dma_cs_next_reloc(p, &src_reloc); 2947 2946 if (r) { 2948 - DRM_ERROR("bad DMA_PACKET_COPY\n"); 2947 + dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); 2949 2948 return -EINVAL; 2950 2949 } 2951 2950 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2952 2951 if (r) { 2953 - DRM_ERROR("bad DMA_PACKET_COPY\n"); 2952 + dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); 2954 2953 return -EINVAL; 2955 2954 } 2956 2955 switch (sub_cmd) { ··· 2962 2961 dst_offset = radeon_get_ib_value(p, idx+1); 2963 2962 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 2964 2963 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2965 - dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n", 2966 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2964 + dev_warn_once(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n", 2965 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2967 2966 return -EINVAL; 2968 2967 } 2969 2968 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2970 - dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n", 2971 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2969 + dev_warn_once(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n", 2970 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2972 2971 return -EINVAL; 2973 2972 } 2974 2973 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); ··· 3002 3001 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3003 3002 } 3004 3003 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3005 - dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", 3006 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3004 + dev_warn_once(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", 3005 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3007 3006 return -EINVAL; 3008 3007 } 3009 3008 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3010 - dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n", 3011 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3009 + dev_warn_once(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n", 3010 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3012 3011 return -EINVAL; 3013 3012 } 3014 3013 p->idx += 9; ··· 3021 3020 dst_offset = radeon_get_ib_value(p, idx+1); 3022 3021 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; 3023 3022 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { 3024 - dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", 3025 - src_offset + count, radeon_bo_size(src_reloc->robj)); 3023 + dev_warn_once(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", 3024 + src_offset + count, radeon_bo_size(src_reloc->robj)); 3026 3025 return -EINVAL; 3027 3026 } 3028 3027 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { 3029 - dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", 3030 - dst_offset + count, radeon_bo_size(dst_reloc->robj)); 3028 + dev_warn_once(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", 3029 + dst_offset + count, radeon_bo_size(dst_reloc->robj)); 3031 3030 return -EINVAL; 3032 3031 } 3033 3032 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); ··· 3040 3039 case 0x41: 3041 3040 /* L2L, partial */ 3042 3041 if (p->family < CHIP_CAYMAN) { 3043 - DRM_ERROR("L2L Partial is cayman only !\n"); 3042 + dev_warn_once(p->dev, "L2L Partial is cayman only !\n"); 3044 3043 return -EINVAL; 3045 3044 } 3046 3045 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); ··· 3055 3054 /* L2L, dw, broadcast */ 3056 3055 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3057 3056 if (r) { 3058 - DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n"); 3057 + dev_warn_once(p->dev, "bad L2L, dw, broadcast DMA_PACKET_COPY\n"); 3059 3058 return -EINVAL; 3060 3059 } 3061 3060 dst_offset = radeon_get_ib_value(p, idx+1); ··· 3065 3064 src_offset = radeon_get_ib_value(p, idx+3); 3066 3065 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; 3067 3066 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3068 - dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", 3069 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3067 + dev_warn_once(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", 3068 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3070 3069 return -EINVAL; 3071 3070 } 3072 3071 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3073 - dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", 3074 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3072 + dev_warn_once(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", 3073 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3075 3074 return -EINVAL; 3076 3075 } 3077 3076 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3078 - dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", 3079 - dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3077 + dev_warn_once(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", 3078 + dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3080 3079 return -EINVAL; 3081 3080 } 3082 3081 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); ··· 3090 3089 /* Copy L2T Frame to Field */ 3091 3090 case 0x48: 3092 3091 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3093 - DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 3092 + dev_warn_once(p->dev, "bad L2T, frame to fields DMA_PACKET_COPY\n"); 3094 3093 return -EINVAL; 3095 3094 } 3096 3095 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3097 3096 if (r) { 3098 - DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 3097 + dev_warn_once(p->dev, "bad L2T, frame to fields DMA_PACKET_COPY\n"); 3099 3098 return -EINVAL; 3100 3099 } 3101 3100 dst_offset = radeon_get_ib_value(p, idx+1); ··· 3105 3104 src_offset = radeon_get_ib_value(p, idx+8); 3106 3105 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3107 3106 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3108 - dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", 3109 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3107 + dev_warn_once(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", 3108 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3110 3109 return -EINVAL; 3111 3110 } 3112 3111 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3113 - dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 3114 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3112 + dev_warn_once(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 3113 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3115 3114 return -EINVAL; 3116 3115 } 3117 3116 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3118 - dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 3119 - dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3117 + dev_warn_once(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 3118 + dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3120 3119 return -EINVAL; 3121 3120 } 3122 3121 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); ··· 3129 3128 case 0x49: 3130 3129 /* L2T, T2L partial */ 3131 3130 if (p->family < CHIP_CAYMAN) { 3132 - DRM_ERROR("L2T, T2L Partial is cayman only !\n"); 3131 + dev_warn_once(p->dev, "L2T, T2L Partial is cayman only !\n"); 3133 3132 return -EINVAL; 3134 3133 } 3135 3134 /* detile bit */ ··· 3152 3151 case 0x4b: 3153 3152 /* L2T, broadcast */ 3154 3153 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3155 - DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3154 + dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); 3156 3155 return -EINVAL; 3157 3156 } 3158 3157 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3159 3158 if (r) { 3160 - DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3159 + dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); 3161 3160 return -EINVAL; 3162 3161 } 3163 3162 dst_offset = radeon_get_ib_value(p, idx+1); ··· 3167 3166 src_offset = radeon_get_ib_value(p, idx+8); 3168 3167 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3169 3168 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3170 - dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", 3171 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3169 + dev_warn_once(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", 3170 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3172 3171 return -EINVAL; 3173 3172 } 3174 3173 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3175 - dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", 3176 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3174 + dev_warn_once(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", 3175 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3177 3176 return -EINVAL; 3178 3177 } 3179 3178 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3180 - dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", 3181 - dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3179 + dev_warn_once(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", 3180 + dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3182 3181 return -EINVAL; 3183 3182 } 3184 3183 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); ··· 3213 3212 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); 3214 3213 } 3215 3214 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3216 - dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", 3217 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3215 + dev_warn_once(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", 3216 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3218 3217 return -EINVAL; 3219 3218 } 3220 3219 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3221 - dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n", 3222 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3220 + dev_warn_once(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n", 3221 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3223 3222 return -EINVAL; 3224 3223 } 3225 3224 p->idx += 9; ··· 3228 3227 case 0x4d: 3229 3228 /* T2T partial */ 3230 3229 if (p->family < CHIP_CAYMAN) { 3231 - DRM_ERROR("L2T, T2L Partial is cayman only !\n"); 3230 + dev_warn_once(p->dev, "L2T, T2L Partial is cayman only !\n"); 3232 3231 return -EINVAL; 3233 3232 } 3234 3233 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); ··· 3239 3238 case 0x4f: 3240 3239 /* L2T, broadcast */ 3241 3240 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { 3242 - DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3241 + dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); 3243 3242 return -EINVAL; 3244 3243 } 3245 3244 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 3246 3245 if (r) { 3247 - DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n"); 3246 + dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); 3248 3247 return -EINVAL; 3249 3248 } 3250 3249 dst_offset = radeon_get_ib_value(p, idx+1); ··· 3254 3253 src_offset = radeon_get_ib_value(p, idx+8); 3255 3254 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; 3256 3255 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3257 - dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", 3258 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3256 + dev_warn_once(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", 3257 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 3259 3258 return -EINVAL; 3260 3259 } 3261 3260 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3262 - dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", 3263 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3261 + dev_warn_once(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", 3262 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 3264 3263 return -EINVAL; 3265 3264 } 3266 3265 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 3267 - dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", 3268 - dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3266 + dev_warn_once(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", 3267 + dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 3269 3268 return -EINVAL; 3270 3269 } 3271 3270 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); ··· 3275 3274 p->idx += 10; 3276 3275 break; 3277 3276 default: 3278 - DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); 3277 + dev_warn_once(p->dev, "bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); 3279 3278 return -EINVAL; 3280 3279 } 3281 3280 break; 3282 3281 case DMA_PACKET_CONSTANT_FILL: 3283 3282 r = r600_dma_cs_next_reloc(p, &dst_reloc); 3284 3283 if (r) { 3285 - DRM_ERROR("bad DMA_PACKET_CONSTANT_FILL\n"); 3284 + dev_warn_once(p->dev, "bad DMA_PACKET_CONSTANT_FILL\n"); 3286 3285 return -EINVAL; 3287 3286 } 3288 3287 dst_offset = radeon_get_ib_value(p, idx+1); 3289 3288 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 3290 3289 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 3291 - dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", 3292 - dst_offset, radeon_bo_size(dst_reloc->robj)); 3290 + dev_warn_once(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", 3291 + dst_offset, radeon_bo_size(dst_reloc->robj)); 3293 3292 return -EINVAL; 3294 3293 } 3295 3294 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); ··· 3300 3299 p->idx += 1; 3301 3300 break; 3302 3301 default: 3303 - DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 3302 + dev_warn_once(p->dev, "Unknown packet type %d at %d !\n", cmd, idx); 3304 3303 return -EINVAL; 3305 3304 } 3306 3305 } while (p->idx < p->chunk_ib->length_dw); ··· 3431 3430 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: 3432 3431 return true; 3433 3432 default: 3434 - DRM_ERROR("Invalid register 0x%x in CS\n", reg); 3433 + DRM_DEBUG("Invalid register 0x%x in CS\n", reg); 3435 3434 return false; 3436 3435 } 3437 3436 } ··· 3449 3448 break; 3450 3449 case PACKET3_SET_BASE: 3451 3450 if (idx_value != 1) { 3452 - DRM_ERROR("bad SET_BASE"); 3451 + dev_warn_once(rdev->dev, "bad SET_BASE"); 3453 3452 return -EINVAL; 3454 3453 } 3455 3454 break; ··· 3520 3519 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 3521 3520 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 3522 3521 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 3523 - DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 3522 + dev_warn_once(rdev->dev, "bad PACKET3_SET_CONFIG_REG\n"); 3524 3523 return -EINVAL; 3525 3524 } 3526 3525 for (i = 0; i < pkt->count; i++) { ··· 3540 3539 (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ 3541 3540 /* non mem to mem copies requires dw aligned count */ 3542 3541 if ((command & 0x1fffff) % 4) { 3543 - DRM_ERROR("CP DMA command requires dw count alignment\n"); 3542 + dev_warn_once(rdev->dev, "CP DMA command requires dw count alignment\n"); 3544 3543 return -EINVAL; 3545 3544 } 3546 3545 } ··· 3551 3550 if (command & PACKET3_CP_DMA_CMD_SAIC) { 3552 3551 reg = start_reg; 3553 3552 if (!evergreen_vm_reg_valid(reg)) { 3554 - DRM_ERROR("CP DMA Bad SRC register\n"); 3553 + dev_warn_once(rdev->dev, "CP DMA Bad SRC register\n"); 3555 3554 return -EINVAL; 3556 3555 } 3557 3556 } else { 3558 3557 for (i = 0; i < (command & 0x1fffff); i++) { 3559 3558 reg = start_reg + (4 * i); 3560 3559 if (!evergreen_vm_reg_valid(reg)) { 3561 - DRM_ERROR("CP DMA Bad SRC register\n"); 3560 + dev_warn_once(rdev->dev, "CP DMA Bad SRC register\n"); 3562 3561 return -EINVAL; 3563 3562 } 3564 3563 } ··· 3572 3571 if (command & PACKET3_CP_DMA_CMD_DAIC) { 3573 3572 reg = start_reg; 3574 3573 if (!evergreen_vm_reg_valid(reg)) { 3575 - DRM_ERROR("CP DMA Bad DST register\n"); 3574 + dev_warn_once(rdev->dev, "CP DMA Bad DST register\n"); 3576 3575 return -EINVAL; 3577 3576 } 3578 3577 } else { 3579 3578 for (i = 0; i < (command & 0x1fffff); i++) { 3580 3579 reg = start_reg + (4 * i); 3581 3580 if (!evergreen_vm_reg_valid(reg)) { 3582 - DRM_ERROR("CP DMA Bad DST register\n"); 3581 + dev_warn_once(rdev->dev, "CP DMA Bad DST register\n"); 3583 3582 return -EINVAL; 3584 3583 } 3585 3584 } ··· 3592 3591 uint32_t allowed_reg_base; 3593 3592 3594 3593 if (pkt->count != 2) { 3595 - DRM_ERROR("bad SET_APPEND_CNT (invalid count)\n"); 3594 + dev_warn_once(rdev->dev, "bad SET_APPEND_CNT (invalid count)\n"); 3596 3595 return -EINVAL; 3597 3596 } 3598 3597 ··· 3602 3601 3603 3602 areg = idx_value >> 16; 3604 3603 if (areg < allowed_reg_base || areg > (allowed_reg_base + 11)) { 3605 - DRM_ERROR("forbidden register for append cnt 0x%08x at %d\n", 3606 - areg, idx); 3604 + dev_warn_once(rdev->dev, "forbidden register for append cnt 0x%08x at %d\n", 3605 + areg, idx); 3607 3606 return -EINVAL; 3608 3607 } 3609 3608 break; ··· 3682 3681 idx += count + 3; 3683 3682 break; 3684 3683 default: 3685 - DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); 3684 + dev_warn_once(rdev->dev, 3685 + "bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", 3686 + idx, ib->ptr[idx]); 3686 3687 return -EINVAL; 3687 3688 } 3688 3689 break; ··· 3735 3732 idx += 10; 3736 3733 break; 3737 3734 default: 3738 - DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); 3735 + dev_warn_once(rdev->dev, 3736 + "bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", 3737 + idx, ib->ptr[idx]); 3739 3738 return -EINVAL; 3740 3739 } 3741 3740 break; ··· 3748 3743 idx += 1; 3749 3744 break; 3750 3745 default: 3751 - DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 3746 + dev_warn_once(rdev->dev, "Unknown packet type %d at %d !\n", cmd, idx); 3752 3747 return -EINVAL; 3753 3748 } 3754 3749 } while (idx < ib->length_dw);
+1 -1
drivers/gpu/drm/radeon/ni_dpm.c
··· 3397 3397 if (PPSMC_Result_OK != smc_result) 3398 3398 ret = -EINVAL; 3399 3399 3400 - ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false; 3400 + ni_pi->cac_enabled = PPSMC_Result_OK == smc_result; 3401 3401 } 3402 3402 } else if (ni_pi->cac_enabled) { 3403 3403 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
+108 -107
drivers/gpu/drm/radeon/r100.c
··· 1298 1298 1299 1299 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1300 1300 if (r) { 1301 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1302 - idx, reg); 1301 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1302 + idx, reg); 1303 1303 radeon_cs_dump_packet(p, pkt); 1304 1304 return r; 1305 1305 } ··· 1313 1313 tile_flags |= RADEON_DST_TILE_MACRO; 1314 1314 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1315 1315 if (reg == RADEON_SRC_PITCH_OFFSET) { 1316 - DRM_ERROR("Cannot src blit from microtiled surface\n"); 1316 + dev_warn_once(p->dev, "Cannot src blit from microtiled surface\n"); 1317 1317 radeon_cs_dump_packet(p, pkt); 1318 1318 return -EINVAL; 1319 1319 } ··· 1342 1342 track = (struct r100_cs_track *)p->track; 1343 1343 c = radeon_get_ib_value(p, idx++) & 0x1F; 1344 1344 if (c > 16) { 1345 - DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1346 - pkt->opcode); 1345 + dev_warn_once(p->dev, "Only 16 vertex buffers are allowed %d\n", 1346 + pkt->opcode); 1347 1347 radeon_cs_dump_packet(p, pkt); 1348 1348 return -EINVAL; 1349 1349 } ··· 1351 1351 for (i = 0; i < (c - 1); i += 2, idx += 3) { 1352 1352 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1353 1353 if (r) { 1354 - DRM_ERROR("No reloc for packet3 %d\n", 1355 - pkt->opcode); 1354 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1355 + pkt->opcode); 1356 1356 radeon_cs_dump_packet(p, pkt); 1357 1357 return r; 1358 1358 } ··· 1364 1364 track->arrays[i + 0].esize &= 0x7F; 1365 1365 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1366 1366 if (r) { 1367 - DRM_ERROR("No reloc for packet3 %d\n", 1368 - pkt->opcode); 1367 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1368 + pkt->opcode); 1369 1369 radeon_cs_dump_packet(p, pkt); 1370 1370 return r; 1371 1371 } ··· 1377 1377 if (c & 1) { 1378 1378 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1379 1379 if (r) { 1380 - DRM_ERROR("No reloc for packet3 %d\n", 1381 - pkt->opcode); 1380 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", 1381 + pkt->opcode); 1382 1382 radeon_cs_dump_packet(p, pkt); 1383 1383 return r; 1384 1384 } ··· 1470 1470 /* check its a wait until and only 1 count */ 1471 1471 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1472 1472 waitreloc.count != 0) { 1473 - DRM_ERROR("vline wait had illegal wait until segment\n"); 1473 + dev_warn_once(p->dev, "vline wait had illegal wait until segment\n"); 1474 1474 return -EINVAL; 1475 1475 } 1476 1476 1477 1477 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1478 - DRM_ERROR("vline wait had illegal wait until\n"); 1478 + dev_warn_once(p->dev, "vline wait had illegal wait until\n"); 1479 1479 return -EINVAL; 1480 1480 } 1481 1481 ··· 1493 1493 reg = R100_CP_PACKET0_GET_REG(header); 1494 1494 crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id); 1495 1495 if (!crtc) { 1496 - DRM_ERROR("cannot find crtc %d\n", crtc_id); 1496 + dev_warn_once(p->dev, "cannot find crtc %d\n", crtc_id); 1497 1497 return -ENOENT; 1498 1498 } 1499 1499 radeon_crtc = to_radeon_crtc(crtc); ··· 1514 1514 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1515 1515 break; 1516 1516 default: 1517 - DRM_ERROR("unknown crtc reloc\n"); 1517 + dev_warn_once(p->dev, "unknown crtc reloc\n"); 1518 1518 return -EINVAL; 1519 1519 } 1520 1520 ib[h_idx] = header; ··· 1599 1599 case RADEON_CRTC_GUI_TRIG_VLINE: 1600 1600 r = r100_cs_packet_parse_vline(p); 1601 1601 if (r) { 1602 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1602 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1603 1603 idx, reg); 1604 1604 radeon_cs_dump_packet(p, pkt); 1605 1605 return r; ··· 1616 1616 case RADEON_RB3D_DEPTHOFFSET: 1617 1617 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1618 1618 if (r) { 1619 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1620 - idx, reg); 1619 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1620 + idx, reg); 1621 1621 radeon_cs_dump_packet(p, pkt); 1622 1622 return r; 1623 1623 } ··· 1629 1629 case RADEON_RB3D_COLOROFFSET: 1630 1630 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1631 1631 if (r) { 1632 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1633 - idx, reg); 1632 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1633 + idx, reg); 1634 1634 radeon_cs_dump_packet(p, pkt); 1635 1635 return r; 1636 1636 } ··· 1645 1645 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1646 1646 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1647 1647 if (r) { 1648 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1649 - idx, reg); 1648 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1649 + idx, reg); 1650 1650 radeon_cs_dump_packet(p, pkt); 1651 1651 return r; 1652 1652 } ··· 1672 1672 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1673 1673 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1674 1674 if (r) { 1675 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1676 - idx, reg); 1675 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1676 + idx, reg); 1677 1677 radeon_cs_dump_packet(p, pkt); 1678 1678 return r; 1679 1679 } ··· 1690 1690 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1691 1691 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1692 1692 if (r) { 1693 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1694 - idx, reg); 1693 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1694 + idx, reg); 1695 1695 radeon_cs_dump_packet(p, pkt); 1696 1696 return r; 1697 1697 } ··· 1708 1708 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1709 1709 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1710 1710 if (r) { 1711 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1712 - idx, reg); 1711 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1712 + idx, reg); 1713 1713 radeon_cs_dump_packet(p, pkt); 1714 1714 return r; 1715 1715 } ··· 1726 1726 case RADEON_RB3D_COLORPITCH: 1727 1727 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1728 1728 if (r) { 1729 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1730 - idx, reg); 1729 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1730 + idx, reg); 1731 1731 radeon_cs_dump_packet(p, pkt); 1732 1732 return r; 1733 1733 } ··· 1768 1768 track->cb[0].cpp = 4; 1769 1769 break; 1770 1770 default: 1771 - DRM_ERROR("Invalid color buffer format (%d) !\n", 1772 - ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1771 + dev_warn_once(p->dev, "Invalid color buffer format (%d) !\n", 1772 + ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1773 1773 return -EINVAL; 1774 1774 } 1775 1775 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); ··· 1797 1797 case RADEON_RB3D_ZPASS_ADDR: 1798 1798 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1799 1799 if (r) { 1800 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1801 - idx, reg); 1800 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1801 + idx, reg); 1802 1802 radeon_cs_dump_packet(p, pkt); 1803 1803 return r; 1804 1804 } ··· 1927 1927 idx = pkt->idx + 1; 1928 1928 value = radeon_get_ib_value(p, idx + 2); 1929 1929 if ((value + 1) > radeon_bo_size(robj)) { 1930 - DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1931 - "(need %u have %lu) !\n", 1932 - value + 1, 1933 - radeon_bo_size(robj)); 1930 + dev_warn_once(p->dev, "[drm] Buffer too small for PACKET3 INDX_BUFFER " 1931 + "(need %u have %lu) !\n", 1932 + value + 1, 1933 + radeon_bo_size(robj)); 1934 1934 return -EINVAL; 1935 1935 } 1936 1936 return 0; ··· 1957 1957 case PACKET3_INDX_BUFFER: 1958 1958 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1959 1959 if (r) { 1960 - DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1960 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", pkt->opcode); 1961 1961 radeon_cs_dump_packet(p, pkt); 1962 1962 return r; 1963 1963 } ··· 1971 1971 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1972 1972 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1973 1973 if (r) { 1974 - DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1974 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", pkt->opcode); 1975 1975 radeon_cs_dump_packet(p, pkt); 1976 1976 return r; 1977 1977 } ··· 1992 1992 break; 1993 1993 case PACKET3_3D_DRAW_IMMD: 1994 1994 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1995 - DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1995 + dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 1996 1996 return -EINVAL; 1997 1997 } 1998 1998 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); ··· 2005 2005 /* triggers drawing using in-packet vertex data */ 2006 2006 case PACKET3_3D_DRAW_IMMD_2: 2007 2007 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 2008 - DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 2008 + dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 2009 2009 return -EINVAL; 2010 2010 } 2011 2011 track->vap_vf_cntl = radeon_get_ib_value(p, idx); ··· 2051 2051 case PACKET3_NOP: 2052 2052 break; 2053 2053 default: 2054 - DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2054 + dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); 2055 2055 return -EINVAL; 2056 2056 } 2057 2057 return 0; ··· 2093 2093 r = r100_packet3_check(p, &pkt); 2094 2094 break; 2095 2095 default: 2096 - DRM_ERROR("Unknown packet type %d !\n", 2097 - pkt.type); 2096 + dev_warn_once(p->dev, "Unknown packet type %d !\n", 2097 + pkt.type); 2098 2098 return -EINVAL; 2099 2099 } 2100 2100 if (r) ··· 2105 2105 2106 2106 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2107 2107 { 2108 - DRM_ERROR("pitch %d\n", t->pitch); 2109 - DRM_ERROR("use_pitch %d\n", t->use_pitch); 2110 - DRM_ERROR("width %d\n", t->width); 2111 - DRM_ERROR("width_11 %d\n", t->width_11); 2112 - DRM_ERROR("height %d\n", t->height); 2113 - DRM_ERROR("height_11 %d\n", t->height_11); 2114 - DRM_ERROR("num levels %d\n", t->num_levels); 2115 - DRM_ERROR("depth %d\n", t->txdepth); 2116 - DRM_ERROR("bpp %d\n", t->cpp); 2117 - DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2118 - DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2119 - DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2120 - DRM_ERROR("compress format %d\n", t->compress_format); 2108 + DRM_DEBUG("pitch %d\n", t->pitch); 2109 + DRM_DEBUG("use_pitch %d\n", t->use_pitch); 2110 + DRM_DEBUG("width %d\n", t->width); 2111 + DRM_DEBUG("width_11 %d\n", t->width_11); 2112 + DRM_DEBUG("height %d\n", t->height); 2113 + DRM_DEBUG("height_11 %d\n", t->height_11); 2114 + DRM_DEBUG("num levels %d\n", t->num_levels); 2115 + DRM_DEBUG("depth %d\n", t->txdepth); 2116 + DRM_DEBUG("bpp %d\n", t->cpp); 2117 + DRM_DEBUG("coordinate type %d\n", t->tex_coord_type); 2118 + DRM_DEBUG("width round to power of 2 %d\n", t->roundup_w); 2119 + DRM_DEBUG("height round to power of 2 %d\n", t->roundup_h); 2120 + DRM_DEBUG("compress format %d\n", t->compress_format); 2121 2121 } 2122 2122 2123 2123 static int r100_track_compress_size(int compress_format, int w, int h) ··· 2172 2172 size += track->textures[idx].cube_info[face].offset; 2173 2173 2174 2174 if (size > radeon_bo_size(cube_robj)) { 2175 - DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2176 - size, radeon_bo_size(cube_robj)); 2175 + dev_warn_once(rdev->dev, 2176 + "Cube texture offset greater than object size %lu %lu\n", 2177 + size, radeon_bo_size(cube_robj)); 2177 2178 r100_cs_track_texture_print(&track->textures[idx]); 2178 2179 return -1; 2179 2180 } ··· 2197 2196 continue; 2198 2197 robj = track->textures[u].robj; 2199 2198 if (robj == NULL) { 2200 - DRM_ERROR("No texture bound to unit %u\n", u); 2199 + dev_warn_once(rdev->dev, "No texture bound to unit %u\n", u); 2201 2200 return -EINVAL; 2202 2201 } 2203 2202 size = 0; ··· 2250 2249 size *= 6; 2251 2250 break; 2252 2251 default: 2253 - DRM_ERROR("Invalid texture coordinate type %u for unit " 2254 - "%u\n", track->textures[u].tex_coord_type, u); 2252 + dev_warn_once(rdev->dev, "Invalid texture coordinate type %u for unit " 2253 + "%u\n", track->textures[u].tex_coord_type, u); 2255 2254 return -EINVAL; 2256 2255 } 2257 2256 if (size > radeon_bo_size(robj)) { 2258 - DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2259 - "%lu\n", u, size, radeon_bo_size(robj)); 2257 + dev_warn_once(rdev->dev, "Texture of unit %u needs %lu bytes but is " 2258 + "%lu\n", u, size, radeon_bo_size(robj)); 2260 2259 r100_cs_track_texture_print(&track->textures[u]); 2261 2260 return -EINVAL; 2262 2261 } ··· 2278 2277 2279 2278 for (i = 0; i < num_cb; i++) { 2280 2279 if (track->cb[i].robj == NULL) { 2281 - DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2280 + dev_warn_once(rdev->dev, "[drm] No buffer for color buffer %d !\n", i); 2282 2281 return -EINVAL; 2283 2282 } 2284 2283 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2285 2284 size += track->cb[i].offset; 2286 2285 if (size > radeon_bo_size(track->cb[i].robj)) { 2287 - DRM_ERROR("[drm] Buffer too small for color buffer %d " 2288 - "(need %lu have %lu) !\n", i, size, 2289 - radeon_bo_size(track->cb[i].robj)); 2290 - DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2291 - i, track->cb[i].pitch, track->cb[i].cpp, 2292 - track->cb[i].offset, track->maxy); 2286 + dev_warn_once(rdev->dev, "[drm] Buffer too small for color buffer %d " 2287 + "(need %lu have %lu) !\n", i, size, 2288 + radeon_bo_size(track->cb[i].robj)); 2289 + dev_warn_once(rdev->dev, "[drm] color buffer %d (%u %u %u %u)\n", 2290 + i, track->cb[i].pitch, track->cb[i].cpp, 2291 + track->cb[i].offset, track->maxy); 2293 2292 return -EINVAL; 2294 2293 } 2295 2294 } ··· 2297 2296 2298 2297 if (track->zb_dirty && track->z_enabled) { 2299 2298 if (track->zb.robj == NULL) { 2300 - DRM_ERROR("[drm] No buffer for z buffer !\n"); 2299 + dev_warn_once(rdev->dev, "[drm] No buffer for z buffer !\n"); 2301 2300 return -EINVAL; 2302 2301 } 2303 2302 size = track->zb.pitch * track->zb.cpp * track->maxy; 2304 2303 size += track->zb.offset; 2305 2304 if (size > radeon_bo_size(track->zb.robj)) { 2306 - DRM_ERROR("[drm] Buffer too small for z buffer " 2307 - "(need %lu have %lu) !\n", size, 2308 - radeon_bo_size(track->zb.robj)); 2309 - DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2310 - track->zb.pitch, track->zb.cpp, 2311 - track->zb.offset, track->maxy); 2305 + dev_warn_once(rdev->dev, "[drm] Buffer too small for z buffer " 2306 + "(need %lu have %lu) !\n", size, 2307 + radeon_bo_size(track->zb.robj)); 2308 + dev_warn_once(rdev->dev, "[drm] zbuffer (%u %u %u %u)\n", 2309 + track->zb.pitch, track->zb.cpp, 2310 + track->zb.offset, track->maxy); 2312 2311 return -EINVAL; 2313 2312 } 2314 2313 } ··· 2316 2315 2317 2316 if (track->aa_dirty && track->aaresolve) { 2318 2317 if (track->aa.robj == NULL) { 2319 - DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2318 + dev_warn_once(rdev->dev, "[drm] No buffer for AA resolve buffer %d !\n", i); 2320 2319 return -EINVAL; 2321 2320 } 2322 2321 /* I believe the format comes from colorbuffer0. */ 2323 2322 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2324 2323 size += track->aa.offset; 2325 2324 if (size > radeon_bo_size(track->aa.robj)) { 2326 - DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2327 - "(need %lu have %lu) !\n", i, size, 2328 - radeon_bo_size(track->aa.robj)); 2329 - DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2330 - i, track->aa.pitch, track->cb[0].cpp, 2331 - track->aa.offset, track->maxy); 2325 + dev_warn_once(rdev->dev, "[drm] Buffer too small for AA resolve buffer %d " 2326 + "(need %lu have %lu) !\n", i, size, 2327 + radeon_bo_size(track->aa.robj)); 2328 + dev_warn_once(rdev->dev, "[drm] AA resolve buffer %d (%u %u %u %u)\n", 2329 + i, track->aa.pitch, track->cb[0].cpp, 2330 + track->aa.offset, track->maxy); 2332 2331 return -EINVAL; 2333 2332 } 2334 2333 } ··· 2345 2344 for (i = 0; i < track->num_arrays; i++) { 2346 2345 size = track->arrays[i].esize * track->max_indx * 4UL; 2347 2346 if (track->arrays[i].robj == NULL) { 2348 - DRM_ERROR("(PW %u) Vertex array %u no buffer " 2349 - "bound\n", prim_walk, i); 2347 + dev_warn_once(rdev->dev, "(PW %u) Vertex array %u no buffer " 2348 + "bound\n", prim_walk, i); 2350 2349 return -EINVAL; 2351 2350 } 2352 2351 if (size > radeon_bo_size(track->arrays[i].robj)) { 2353 - dev_err(rdev->dev, "(PW %u) Vertex array %u " 2354 - "need %lu dwords have %lu dwords\n", 2355 - prim_walk, i, size >> 2, 2356 - radeon_bo_size(track->arrays[i].robj) 2357 - >> 2); 2358 - DRM_ERROR("Max indices %u\n", track->max_indx); 2352 + dev_warn_once(rdev->dev, "(PW %u) Vertex array %u " 2353 + "need %lu dwords have %lu dwords\n", 2354 + prim_walk, i, size >> 2, 2355 + radeon_bo_size(track->arrays[i].robj) 2356 + >> 2); 2357 + dev_warn_once(rdev->dev, "Max indices %u\n", track->max_indx); 2359 2358 return -EINVAL; 2360 2359 } 2361 2360 } ··· 2364 2363 for (i = 0; i < track->num_arrays; i++) { 2365 2364 size = track->arrays[i].esize * (nverts - 1) * 4UL; 2366 2365 if (track->arrays[i].robj == NULL) { 2367 - DRM_ERROR("(PW %u) Vertex array %u no buffer " 2368 - "bound\n", prim_walk, i); 2366 + dev_warn_once(rdev->dev, "(PW %u) Vertex array %u no buffer " 2367 + "bound\n", prim_walk, i); 2369 2368 return -EINVAL; 2370 2369 } 2371 2370 if (size > radeon_bo_size(track->arrays[i].robj)) { 2372 - dev_err(rdev->dev, "(PW %u) Vertex array %u " 2373 - "need %lu dwords have %lu dwords\n", 2374 - prim_walk, i, size >> 2, 2375 - radeon_bo_size(track->arrays[i].robj) 2376 - >> 2); 2371 + dev_warn_once(rdev->dev, "(PW %u) Vertex array %u " 2372 + "need %lu dwords have %lu dwords\n", 2373 + prim_walk, i, size >> 2, 2374 + radeon_bo_size(track->arrays[i].robj) 2375 + >> 2); 2377 2376 return -EINVAL; 2378 2377 } 2379 2378 } ··· 2381 2380 case 3: 2382 2381 size = track->vtx_size * nverts; 2383 2382 if (size != track->immd_dwords) { 2384 - DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2385 - track->immd_dwords, size); 2386 - DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2387 - nverts, track->vtx_size); 2383 + dev_warn_once(rdev->dev, "IMMD draw %u dwors but needs %lu dwords\n", 2384 + track->immd_dwords, size); 2385 + dev_warn_once(rdev->dev, "VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2386 + nverts, track->vtx_size); 2388 2387 return -EINVAL; 2389 2388 } 2390 2389 break; 2391 2390 default: 2392 - DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2393 - prim_walk); 2391 + dev_warn_once(rdev->dev, "[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2392 + prim_walk); 2394 2393 return -EINVAL; 2395 2394 } 2396 2395
+17 -17
drivers/gpu/drm/radeon/r200.c
··· 163 163 case RADEON_CRTC_GUI_TRIG_VLINE: 164 164 r = r100_cs_packet_parse_vline(p); 165 165 if (r) { 166 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 167 - idx, reg); 166 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 167 + idx, reg); 168 168 radeon_cs_dump_packet(p, pkt); 169 169 return r; 170 170 } ··· 180 180 case RADEON_RB3D_DEPTHOFFSET: 181 181 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 182 182 if (r) { 183 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 184 - idx, reg); 183 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 184 + idx, reg); 185 185 radeon_cs_dump_packet(p, pkt); 186 186 return r; 187 187 } ··· 193 193 case RADEON_RB3D_COLOROFFSET: 194 194 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 195 195 if (r) { 196 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 197 - idx, reg); 196 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 197 + idx, reg); 198 198 radeon_cs_dump_packet(p, pkt); 199 199 return r; 200 200 } ··· 212 212 i = (reg - R200_PP_TXOFFSET_0) / 24; 213 213 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 214 214 if (r) { 215 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 216 - idx, reg); 215 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 216 + idx, reg); 217 217 radeon_cs_dump_packet(p, pkt); 218 218 return r; 219 219 } ··· 265 265 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; 266 266 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 267 267 if (r) { 268 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 269 - idx, reg); 268 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 269 + idx, reg); 270 270 radeon_cs_dump_packet(p, pkt); 271 271 return r; 272 272 } ··· 283 283 case RADEON_RB3D_COLORPITCH: 284 284 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 285 285 if (r) { 286 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 287 - idx, reg); 286 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 287 + idx, reg); 288 288 radeon_cs_dump_packet(p, pkt); 289 289 return r; 290 290 } ··· 326 326 track->cb[0].cpp = 4; 327 327 break; 328 328 default: 329 - DRM_ERROR("Invalid color buffer format (%d) !\n", 330 - ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 329 + dev_warn_once(p->dev, "Invalid color buffer format (%d) !\n", 330 + ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 331 331 return -EINVAL; 332 332 } 333 333 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { 334 - DRM_ERROR("No support for depth xy offset in kms\n"); 334 + dev_warn_once(p->dev, "No support for depth xy offset in kms\n"); 335 335 return -EINVAL; 336 336 } 337 337 ··· 360 360 case RADEON_RB3D_ZPASS_ADDR: 361 361 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 362 362 if (r) { 363 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 364 - idx, reg); 363 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 364 + idx, reg); 365 365 radeon_cs_dump_packet(p, pkt); 366 366 return r; 367 367 }
+33 -33
drivers/gpu/drm/radeon/r300.c
··· 645 645 case RADEON_CRTC_GUI_TRIG_VLINE: 646 646 r = r100_cs_packet_parse_vline(p); 647 647 if (r) { 648 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 649 - idx, reg); 648 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 649 + idx, reg); 650 650 radeon_cs_dump_packet(p, pkt); 651 651 return r; 652 652 } ··· 664 664 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 665 665 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 666 666 if (r) { 667 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 668 - idx, reg); 667 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 668 + idx, reg); 669 669 radeon_cs_dump_packet(p, pkt); 670 670 return r; 671 671 } ··· 677 677 case R300_ZB_DEPTHOFFSET: 678 678 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 679 679 if (r) { 680 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 681 - idx, reg); 680 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 681 + idx, reg); 682 682 radeon_cs_dump_packet(p, pkt); 683 683 return r; 684 684 } ··· 706 706 i = (reg - R300_TX_OFFSET_0) >> 2; 707 707 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 708 708 if (r) { 709 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 710 - idx, reg); 709 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 710 + idx, reg); 711 711 radeon_cs_dump_packet(p, pkt); 712 712 return r; 713 713 } ··· 762 762 /* RB3D_CCTL */ 763 763 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 764 764 p->rdev->cmask_filp != p->filp) { 765 - DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 765 + dev_warn_once(p->dev, "Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 766 766 return -EINVAL; 767 767 } 768 768 track->num_cb = ((idx_value >> 5) & 0x3) + 1; ··· 779 779 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 780 780 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 781 781 if (r) { 782 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 783 - idx, reg); 782 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 783 + idx, reg); 784 784 radeon_cs_dump_packet(p, pkt); 785 785 return r; 786 786 } ··· 812 812 break; 813 813 case 5: 814 814 if (p->rdev->family < CHIP_RV515) { 815 - DRM_ERROR("Invalid color buffer format (%d)!\n", 816 - ((idx_value >> 21) & 0xF)); 815 + dev_warn_once(p->dev, "Invalid color buffer format (%d)!\n", 816 + ((idx_value >> 21) & 0xF)); 817 817 return -EINVAL; 818 818 } 819 819 fallthrough; ··· 827 827 track->cb[i].cpp = 16; 828 828 break; 829 829 default: 830 - DRM_ERROR("Invalid color buffer format (%d) !\n", 831 - ((idx_value >> 21) & 0xF)); 830 + dev_warn_once(p->dev, "Invalid color buffer format (%d) !\n", 831 + ((idx_value >> 21) & 0xF)); 832 832 return -EINVAL; 833 833 } 834 834 track->cb_dirty = true; ··· 853 853 track->zb.cpp = 4; 854 854 break; 855 855 default: 856 - DRM_ERROR("Invalid z buffer format (%d) !\n", 857 - (idx_value & 0xF)); 856 + dev_warn_once(p->dev, "Invalid z buffer format (%d) !\n", 857 + (idx_value & 0xF)); 858 858 return -EINVAL; 859 859 } 860 860 track->zb_dirty = true; ··· 864 864 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 865 865 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 866 866 if (r) { 867 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 868 - idx, reg); 867 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 868 + idx, reg); 869 869 radeon_cs_dump_packet(p, pkt); 870 870 return r; 871 871 } ··· 962 962 break; 963 963 case R300_TX_FORMAT_ATI2N: 964 964 if (p->rdev->family < CHIP_R420) { 965 - DRM_ERROR("Invalid texture format %u\n", 966 - (idx_value & 0x1F)); 965 + dev_warn_once(p->dev, "Invalid texture format %u\n", 966 + (idx_value & 0x1F)); 967 967 return -EINVAL; 968 968 } 969 969 /* The same rules apply as for DXT3/5. */ ··· 974 974 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 975 975 break; 976 976 default: 977 - DRM_ERROR("Invalid texture format %u\n", 978 - (idx_value & 0x1F)); 977 + dev_warn_once(p->dev, "Invalid texture format %u\n", 978 + (idx_value & 0x1F)); 979 979 return -EINVAL; 980 980 } 981 981 track->tex_dirty = true; ··· 1041 1041 R100_TRACK_COMP_DXT1; 1042 1042 } 1043 1043 } else if (idx_value & (1 << 14)) { 1044 - DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1044 + dev_warn_once(p->dev, "Forbidden bit TXFORMAT_MSB\n"); 1045 1045 return -EINVAL; 1046 1046 } 1047 1047 track->tex_dirty = true; ··· 1079 1079 case R300_ZB_ZPASS_ADDR: 1080 1080 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1081 1081 if (r) { 1082 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1083 - idx, reg); 1082 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1083 + idx, reg); 1084 1084 radeon_cs_dump_packet(p, pkt); 1085 1085 return r; 1086 1086 } ··· 1121 1121 case R300_RB3D_AARESOLVE_OFFSET: 1122 1122 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1123 1123 if (r) { 1124 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1125 - idx, reg); 1124 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 1125 + idx, reg); 1126 1126 radeon_cs_dump_packet(p, pkt); 1127 1127 return r; 1128 1128 } ··· 1191 1191 case PACKET3_INDX_BUFFER: 1192 1192 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1193 1193 if (r) { 1194 - DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1194 + dev_warn_once(p->dev, "No reloc for packet3 %d\n", pkt->opcode); 1195 1195 radeon_cs_dump_packet(p, pkt); 1196 1196 return r; 1197 1197 } ··· 1207 1207 * PRIM_WALK must be equal to 3 vertex data in embedded 1208 1208 * in cmd stream */ 1209 1209 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1210 - DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1210 + dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 1211 1211 return -EINVAL; 1212 1212 } 1213 1213 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); ··· 1222 1222 * PRIM_WALK must be equal to 3 vertex data in embedded 1223 1223 * in cmd stream */ 1224 1224 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1225 - DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1225 + dev_warn_once(p->dev, "PRIM_WALK must be 3 for IMMD draw\n"); 1226 1226 return -EINVAL; 1227 1227 } 1228 1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx); ··· 1272 1272 case PACKET3_NOP: 1273 1273 break; 1274 1274 default: 1275 - DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1275 + dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); 1276 1276 return -EINVAL; 1277 1277 } 1278 1278 return 0; ··· 1308 1308 r = r300_packet3_check(p, &pkt); 1309 1309 break; 1310 1310 default: 1311 - DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1311 + dev_warn_once(p->dev, "Unknown packet type %d !\n", pkt.type); 1312 1312 return -EINVAL; 1313 1313 } 1314 1314 if (r) {
+227 -218
drivers/gpu/drm/radeon/r600_cs.c
··· 361 361 362 362 format = G_0280A0_FORMAT(track->cb_color_info[i]); 363 363 if (!r600_fmt_is_valid_color(format)) { 364 - dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 365 - __func__, __LINE__, format, 366 - i, track->cb_color_info[i]); 364 + dev_warn_once(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 365 + __func__, __LINE__, format, 366 + i, track->cb_color_info[i]); 367 367 return -EINVAL; 368 368 } 369 369 /* pitch in pixels */ ··· 384 384 array_check.blocksize = r600_fmt_get_blocksize(format); 385 385 if (r600_get_array_mode_alignment(&array_check, 386 386 &pitch_align, &height_align, &depth_align, &base_align)) { 387 - dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 388 - G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 389 - track->cb_color_info[i]); 387 + dev_warn_once(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 388 + G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 389 + track->cb_color_info[i]); 390 390 return -EINVAL; 391 391 } 392 392 switch (array_mode) { ··· 402 402 case V_0280A0_ARRAY_2D_TILED_THIN1: 403 403 break; 404 404 default: 405 - dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 406 - G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 407 - track->cb_color_info[i]); 405 + dev_warn_once(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, 406 + G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i, 407 + track->cb_color_info[i]); 408 408 return -EINVAL; 409 409 } 410 410 411 411 if (!IS_ALIGNED(pitch, pitch_align)) { 412 - dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 413 - __func__, __LINE__, pitch, pitch_align, array_mode); 412 + dev_warn_once(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", 413 + __func__, __LINE__, pitch, pitch_align, array_mode); 414 414 return -EINVAL; 415 415 } 416 416 if (!IS_ALIGNED(height, height_align)) { 417 - dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 418 - __func__, __LINE__, height, height_align, array_mode); 417 + dev_warn_once(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", 418 + __func__, __LINE__, height, height_align, array_mode); 419 419 return -EINVAL; 420 420 } 421 421 if (!IS_ALIGNED(base_offset, base_align)) { 422 - dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, 423 - base_offset, base_align, array_mode); 422 + dev_warn_once(p->dev, 423 + "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, 424 + base_offset, base_align, array_mode); 424 425 return -EINVAL; 425 426 } 426 427 ··· 448 447 * broken userspace. 449 448 */ 450 449 } else { 451 - dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n", 452 - __func__, i, array_mode, 453 - track->cb_color_bo_offset[i], tmp, 454 - radeon_bo_size(track->cb_color_bo[i]), 455 - pitch, height, r600_fmt_get_nblocksx(format, pitch), 456 - r600_fmt_get_nblocksy(format, height), 457 - r600_fmt_get_blocksize(format)); 450 + dev_warn_once(p->dev, 451 + "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n", 452 + __func__, i, array_mode, 453 + track->cb_color_bo_offset[i], tmp, 454 + radeon_bo_size(track->cb_color_bo[i]), 455 + pitch, height, r600_fmt_get_nblocksx(format, pitch), 456 + r600_fmt_get_nblocksy(format, height), 457 + r600_fmt_get_blocksize(format)); 458 458 return -EINVAL; 459 459 } 460 460 } ··· 480 478 481 479 if (bytes + track->cb_color_frag_offset[i] > 482 480 radeon_bo_size(track->cb_color_frag_bo[i])) { 483 - dev_warn(p->dev, "%s FMASK_TILE_MAX too large " 484 - "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 485 - __func__, tile_max, bytes, 486 - track->cb_color_frag_offset[i], 487 - radeon_bo_size(track->cb_color_frag_bo[i])); 481 + dev_warn_once(p->dev, "%s FMASK_TILE_MAX too large " 482 + "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 483 + __func__, tile_max, bytes, 484 + track->cb_color_frag_offset[i], 485 + radeon_bo_size(track->cb_color_frag_bo[i])); 488 486 return -EINVAL; 489 487 } 490 488 } ··· 498 496 499 497 if (bytes + track->cb_color_tile_offset[i] > 500 498 radeon_bo_size(track->cb_color_tile_bo[i])) { 501 - dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " 502 - "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 503 - __func__, block_max, bytes, 504 - track->cb_color_tile_offset[i], 505 - radeon_bo_size(track->cb_color_tile_bo[i])); 499 + dev_warn_once(p->dev, "%s CMASK_BLOCK_MAX too large " 500 + "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n", 501 + __func__, block_max, bytes, 502 + track->cb_color_tile_offset[i], 503 + radeon_bo_size(track->cb_color_tile_bo[i])); 506 504 return -EINVAL; 507 505 } 508 506 break; 509 507 } 510 508 default: 511 - dev_warn(p->dev, "%s invalid tile mode\n", __func__); 509 + dev_warn_once(p->dev, "%s invalid tile mode\n", __func__); 512 510 return -EINVAL; 513 511 } 514 512 return 0; ··· 528 526 529 527 530 528 if (track->db_bo == NULL) { 531 - dev_warn(p->dev, "z/stencil with no depth buffer\n"); 529 + dev_warn_once(p->dev, "z/stencil with no depth buffer\n"); 532 530 return -EINVAL; 533 531 } 534 532 switch (G_028010_FORMAT(track->db_depth_info)) { ··· 546 544 bpe = 8; 547 545 break; 548 546 default: 549 - dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); 547 + dev_warn_once(p->dev, 548 + "z/stencil with invalid format %d\n", 549 + G_028010_FORMAT(track->db_depth_info)); 550 550 return -EINVAL; 551 551 } 552 552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 553 553 if (!track->db_depth_size_idx) { 554 - dev_warn(p->dev, "z/stencil buffer size not set\n"); 554 + dev_warn_once(p->dev, "z/stencil buffer size not set\n"); 555 555 return -EINVAL; 556 556 } 557 557 tmp = radeon_bo_size(track->db_bo) - track->db_offset; 558 558 tmp = (tmp / bpe) >> 6; 559 559 if (!tmp) { 560 - dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", 561 - track->db_depth_size, bpe, track->db_offset, 562 - radeon_bo_size(track->db_bo)); 560 + dev_warn_once(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", 561 + track->db_depth_size, bpe, track->db_offset, 562 + radeon_bo_size(track->db_bo)); 563 563 return -EINVAL; 564 564 } 565 565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); ··· 583 579 array_check.blocksize = bpe; 584 580 if (r600_get_array_mode_alignment(&array_check, 585 581 &pitch_align, &height_align, &depth_align, &base_align)) { 586 - dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 587 - G_028010_ARRAY_MODE(track->db_depth_info), 588 - track->db_depth_info); 582 + dev_warn_once(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 583 + G_028010_ARRAY_MODE(track->db_depth_info), 584 + track->db_depth_info); 589 585 return -EINVAL; 590 586 } 591 587 switch (array_mode) { ··· 596 592 case V_028010_ARRAY_2D_TILED_THIN1: 597 593 break; 598 594 default: 599 - dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 600 - G_028010_ARRAY_MODE(track->db_depth_info), 601 - track->db_depth_info); 595 + dev_warn_once(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, 596 + G_028010_ARRAY_MODE(track->db_depth_info), 597 + track->db_depth_info); 602 598 return -EINVAL; 603 599 } 604 600 605 601 if (!IS_ALIGNED(pitch, pitch_align)) { 606 - dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 602 + dev_warn_once(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", 607 603 __func__, __LINE__, pitch, pitch_align, array_mode); 608 604 return -EINVAL; 609 605 } 610 606 if (!IS_ALIGNED(height, height_align)) { 611 - dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 607 + dev_warn_once(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", 612 608 __func__, __LINE__, height, height_align, array_mode); 613 609 return -EINVAL; 614 610 } 615 611 if (!IS_ALIGNED(base_offset, base_align)) { 616 - dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, 612 + dev_warn_once(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, 617 613 base_offset, base_align, array_mode); 618 614 return -EINVAL; 619 615 } ··· 622 618 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 623 619 tmp = ntiles * bpe * 64 * nviews * track->nsamples; 624 620 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 625 - dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 626 - array_mode, 627 - track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 628 - radeon_bo_size(track->db_bo)); 621 + dev_warn_once(p->dev, 622 + "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 623 + array_mode, 624 + track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, 625 + radeon_bo_size(track->db_bo)); 629 626 return -EINVAL; 630 627 } 631 628 } ··· 637 632 unsigned nbx, nby; 638 633 639 634 if (track->htile_bo == NULL) { 640 - dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 641 - __func__, __LINE__, track->db_depth_info); 635 + dev_warn_once(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 636 + __func__, __LINE__, track->db_depth_info); 642 637 return -EINVAL; 643 638 } 644 639 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { 645 - dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", 646 - __func__, __LINE__, track->db_depth_size); 640 + dev_warn_once(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", 641 + __func__, __LINE__, track->db_depth_size); 647 642 return -EINVAL; 648 643 } 649 644 ··· 681 676 nby = round_up(nby, 16 * 8); 682 677 break; 683 678 default: 684 - dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 685 - __func__, __LINE__, track->npipes); 679 + dev_warn_once(p->dev, "%s:%d invalid num pipes %d\n", 680 + __func__, __LINE__, track->npipes); 686 681 return -EINVAL; 687 682 } 688 683 } ··· 694 689 size += track->htile_offset; 695 690 696 691 if (size > radeon_bo_size(track->htile_bo)) { 697 - dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 698 - __func__, __LINE__, radeon_bo_size(track->htile_bo), 699 - size, nbx, nby); 692 + dev_warn_once(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 693 + __func__, __LINE__, radeon_bo_size(track->htile_bo), 694 + size, nbx, nby); 700 695 return -EINVAL; 701 696 } 702 697 } ··· 723 718 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 724 719 (u64)track->vgt_strmout_size[i]; 725 720 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 726 - DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", 727 - i, offset, 728 - radeon_bo_size(track->vgt_strmout_bo[i])); 721 + dev_warn_once(p->dev, "streamout %d bo too small: 0x%llx, 0x%lx\n", 722 + i, offset, 723 + radeon_bo_size(track->vgt_strmout_bo[i])); 729 724 return -EINVAL; 730 725 } 731 726 } else { 732 - dev_warn(p->dev, "No buffer for streamout %d\n", i); 727 + dev_warn_once(p->dev, "No buffer for streamout %d\n", i); 733 728 return -EINVAL; 734 729 } 735 730 } ··· 758 753 (tmp >> (i * 4)) & 0xF) { 759 754 /* at least one component is enabled */ 760 755 if (track->cb_color_bo[i] == NULL) { 761 - dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 762 - __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 756 + dev_warn_once(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 757 + __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 763 758 return -EINVAL; 764 759 } 765 760 /* perform rewrite of CB_COLOR[0-7]_SIZE */ ··· 846 841 /* check its a WAIT_REG_MEM */ 847 842 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || 848 843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 849 - DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 844 + dev_warn_once(p->dev, "vline wait missing WAIT_REG_MEM segment\n"); 850 845 return -EINVAL; 851 846 } 852 847 853 848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 854 849 /* bit 4 is reg (0) or mem (1) */ 855 850 if (wait_reg_mem_info & 0x10) { 856 - DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n"); 851 + dev_warn_once(p->dev, "vline WAIT_REG_MEM waiting on MEM instead of REG\n"); 857 852 return -EINVAL; 858 853 } 859 854 /* bit 8 is me (0) or pfp (1) */ 860 855 if (wait_reg_mem_info & 0x100) { 861 - DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n"); 856 + dev_warn_once(p->dev, "vline WAIT_REG_MEM waiting on PFP instead of ME\n"); 862 857 return -EINVAL; 863 858 } 864 859 /* waiting for value to be equal */ 865 860 if ((wait_reg_mem_info & 0x7) != 0x3) { 866 - DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 861 + dev_warn_once(p->dev, "vline WAIT_REG_MEM function not equal\n"); 867 862 return -EINVAL; 868 863 } 869 864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { 870 - DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 865 + dev_warn_once(p->dev, "vline WAIT_REG_MEM bad reg\n"); 871 866 return -EINVAL; 872 867 } 873 868 874 869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { 875 - DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 870 + dev_warn_once(p->dev, "vline WAIT_REG_MEM bad bit mask\n"); 876 871 return -EINVAL; 877 872 } 878 873 ··· 891 886 892 887 crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id); 893 888 if (!crtc) { 894 - DRM_ERROR("cannot find crtc %d\n", crtc_id); 889 + dev_warn_once(p->dev, "cannot find crtc %d\n", crtc_id); 895 890 return -ENOENT; 896 891 } 897 892 radeon_crtc = to_radeon_crtc(crtc); ··· 912 907 ib[h_idx] = header; 913 908 ib[h_idx + 4] = vline_status[crtc_id] >> 2; 914 909 } else { 915 - DRM_ERROR("unknown crtc reloc\n"); 910 + dev_warn_once(p->dev, "unknown crtc reloc\n"); 916 911 return -EINVAL; 917 912 } 918 913 return 0; ··· 928 923 case AVIVO_D1MODE_VLINE_START_END: 929 924 r = r600_cs_packet_parse_vline(p); 930 925 if (r) { 931 - DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 932 - idx, reg); 926 + dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", 927 + idx, reg); 933 928 return r; 934 929 } 935 930 break; ··· 977 972 978 973 i = (reg >> 7); 979 974 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 980 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 975 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 981 976 return -EINVAL; 982 977 } 983 978 m = 1 << ((reg >> 2) & 31); ··· 1018 1013 case SQ_VSTMP_RING_BASE: 1019 1014 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1020 1015 if (r) { 1021 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1022 - "0x%04X\n", reg); 1016 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1017 + "0x%04X\n", reg); 1023 1018 return -EINVAL; 1024 1019 } 1025 1020 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1036 1031 radeon_cs_packet_next_is_pkt3_nop(p)) { 1037 1032 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1038 1033 if (r) { 1039 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1040 - "0x%04X\n", reg); 1034 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1035 + "0x%04X\n", reg); 1041 1036 return -EINVAL; 1042 1037 } 1043 1038 track->db_depth_info = radeon_get_ib_value(p, idx); ··· 1078 1073 case VGT_STRMOUT_BUFFER_BASE_3: 1079 1074 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1080 1075 if (r) { 1081 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1082 - "0x%04X\n", reg); 1076 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1077 + "0x%04X\n", reg); 1083 1078 return -EINVAL; 1084 1079 } 1085 1080 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; ··· 1101 1096 case CP_COHER_BASE: 1102 1097 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1103 1098 if (r) { 1104 - dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1105 - "0x%04X\n", reg); 1099 + dev_warn_once(p->dev, "missing reloc for CP_COHER_BASE " 1100 + "0x%04X\n", reg); 1106 1101 return -EINVAL; 1107 1102 } 1108 1103 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1275 1270 case CB_COLOR7_BASE: 1276 1271 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1277 1272 if (r) { 1278 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1279 - "0x%04X\n", reg); 1273 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1274 + "0x%04X\n", reg); 1280 1275 return -EINVAL; 1281 1276 } 1282 1277 tmp = (reg - CB_COLOR0_BASE) / 4; ··· 1290 1285 case DB_DEPTH_BASE: 1291 1286 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1292 1287 if (r) { 1293 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1294 - "0x%04X\n", reg); 1288 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1289 + "0x%04X\n", reg); 1295 1290 return -EINVAL; 1296 1291 } 1297 1292 track->db_offset = radeon_get_ib_value(p, idx) << 8; ··· 1303 1298 case DB_HTILE_DATA_BASE: 1304 1299 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1305 1300 if (r) { 1306 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1307 - "0x%04X\n", reg); 1301 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1302 + "0x%04X\n", reg); 1308 1303 return -EINVAL; 1309 1304 } 1310 1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; ··· 1373 1368 case SQ_ALU_CONST_CACHE_VS_15: 1374 1369 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1375 1370 if (r) { 1376 - dev_warn(p->dev, "bad SET_CONTEXT_REG " 1377 - "0x%04X\n", reg); 1371 + dev_warn_once(p->dev, "bad SET_CONTEXT_REG " 1372 + "0x%04X\n", reg); 1378 1373 return -EINVAL; 1379 1374 } 1380 1375 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1382 1377 case SX_MEMORY_EXPORT_BASE: 1383 1378 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1384 1379 if (r) { 1385 - dev_warn(p->dev, "bad SET_CONFIG_REG " 1386 - "0x%04X\n", reg); 1380 + dev_warn_once(p->dev, "bad SET_CONFIG_REG " 1381 + "0x%04X\n", reg); 1387 1382 return -EINVAL; 1388 1383 } 1389 1384 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1392 1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1393 1388 break; 1394 1389 default: 1395 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1390 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1396 1391 return -EINVAL; 1397 1392 } 1398 1393 return 0; ··· 1548 1543 llevel = 0; 1549 1544 break; 1550 1545 default: 1551 - dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1546 + dev_warn_once(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); 1552 1547 return -EINVAL; 1553 1548 } 1554 1549 if (!r600_fmt_is_valid_texture(format, p->family)) { 1555 - dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1556 - __func__, __LINE__, format); 1550 + dev_warn_once(p->dev, "%s:%d texture invalid format %d\n", 1551 + __func__, __LINE__, format); 1557 1552 return -EINVAL; 1558 1553 } 1559 1554 1560 1555 if (r600_get_array_mode_alignment(&array_check, 1561 1556 &pitch_align, &height_align, &depth_align, &base_align)) { 1562 - dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", 1563 - __func__, __LINE__, G_038000_TILE_MODE(word0)); 1557 + dev_warn_once(p->dev, "%s:%d tex array mode (%d) invalid\n", 1558 + __func__, __LINE__, G_038000_TILE_MODE(word0)); 1564 1559 return -EINVAL; 1565 1560 } 1566 1561 1567 1562 /* XXX check height as well... */ 1568 1563 1569 1564 if (!IS_ALIGNED(pitch, pitch_align)) { 1570 - dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1571 - __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1565 + dev_warn_once(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", 1566 + __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); 1572 1567 return -EINVAL; 1573 1568 } 1574 1569 if (!IS_ALIGNED(base_offset, base_align)) { 1575 - dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", 1576 - __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); 1570 + dev_warn_once(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", 1571 + __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); 1577 1572 return -EINVAL; 1578 1573 } 1579 1574 if (!IS_ALIGNED(mip_offset, base_align)) { 1580 - dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", 1581 - __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); 1575 + dev_warn_once(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", 1576 + __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); 1582 1577 return -EINVAL; 1583 1578 } 1584 1579 1585 1580 if (blevel > llevel) { 1586 - dev_warn(p->dev, "texture blevel %d > llevel %d\n", 1587 - blevel, llevel); 1581 + dev_warn_once(p->dev, "texture blevel %d > llevel %d\n", 1582 + blevel, llevel); 1588 1583 } 1589 1584 if (is_array) { 1590 1585 barray = G_038014_BASE_ARRAY(word5); ··· 1597 1592 &l0_size, &mipmap_size); 1598 1593 /* using get ib will give us the offset into the texture bo */ 1599 1594 if ((l0_size + word2) > radeon_bo_size(texture)) { 1600 - dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", 1601 - w0, h0, pitch_align, height_align, 1602 - array_check.array_mode, format, word2, 1603 - l0_size, radeon_bo_size(texture)); 1604 - dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); 1595 + dev_warn_once(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", 1596 + w0, h0, pitch_align, height_align, 1597 + array_check.array_mode, format, word2, 1598 + l0_size, radeon_bo_size(texture)); 1599 + dev_warn_once(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); 1605 1600 return -EINVAL; 1606 1601 } 1607 1602 /* using get ib will give us the offset into the mipmap bo */ 1608 1603 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) { 1609 - /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1604 + /*dev_warn_once(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1610 1605 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/ 1611 1606 } 1612 1607 return 0; ··· 1618 1613 1619 1614 i = (reg >> 7); 1620 1615 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) { 1621 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1616 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1622 1617 return false; 1623 1618 } 1624 1619 m = 1 << ((reg >> 2) & 31); 1625 1620 if (!(r600_reg_safe_bm[i] & m)) 1626 1621 return true; 1627 - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1622 + dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1628 1623 return false; 1629 1624 } 1630 1625 ··· 1653 1648 uint64_t offset; 1654 1649 1655 1650 if (pkt->count != 1) { 1656 - DRM_ERROR("bad SET PREDICATION\n"); 1651 + dev_warn_once(p->dev, "bad SET PREDICATION\n"); 1657 1652 return -EINVAL; 1658 1653 } 1659 1654 ··· 1665 1660 return 0; 1666 1661 1667 1662 if (pred_op > 2) { 1668 - DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1663 + dev_warn_once(p->dev, "bad SET PREDICATION operation %d\n", pred_op); 1669 1664 return -EINVAL; 1670 1665 } 1671 1666 1672 1667 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1673 1668 if (r) { 1674 - DRM_ERROR("bad SET PREDICATION\n"); 1669 + dev_warn_once(p->dev, "bad SET PREDICATION\n"); 1675 1670 return -EINVAL; 1676 1671 } 1677 1672 ··· 1686 1681 1687 1682 case PACKET3_START_3D_CMDBUF: 1688 1683 if (p->family >= CHIP_RV770 || pkt->count) { 1689 - DRM_ERROR("bad START_3D\n"); 1684 + dev_warn_once(p->dev, "bad START_3D\n"); 1690 1685 return -EINVAL; 1691 1686 } 1692 1687 break; 1693 1688 case PACKET3_CONTEXT_CONTROL: 1694 1689 if (pkt->count != 1) { 1695 - DRM_ERROR("bad CONTEXT_CONTROL\n"); 1690 + dev_warn_once(p->dev, "bad CONTEXT_CONTROL\n"); 1696 1691 return -EINVAL; 1697 1692 } 1698 1693 break; 1699 1694 case PACKET3_INDEX_TYPE: 1700 1695 case PACKET3_NUM_INSTANCES: 1701 1696 if (pkt->count) { 1702 - DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n"); 1697 + dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES\n"); 1703 1698 return -EINVAL; 1704 1699 } 1705 1700 break; ··· 1707 1702 { 1708 1703 uint64_t offset; 1709 1704 if (pkt->count != 3) { 1710 - DRM_ERROR("bad DRAW_INDEX\n"); 1705 + dev_warn_once(p->dev, "bad DRAW_INDEX\n"); 1711 1706 return -EINVAL; 1712 1707 } 1713 1708 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1714 1709 if (r) { 1715 - DRM_ERROR("bad DRAW_INDEX\n"); 1710 + dev_warn_once(p->dev, "bad DRAW_INDEX\n"); 1716 1711 return -EINVAL; 1717 1712 } 1718 1713 ··· 1725 1720 1726 1721 r = r600_cs_track_check(p); 1727 1722 if (r) { 1728 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1723 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1729 1724 return r; 1730 1725 } 1731 1726 break; 1732 1727 } 1733 1728 case PACKET3_DRAW_INDEX_AUTO: 1734 1729 if (pkt->count != 1) { 1735 - DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 1730 + dev_warn_once(p->dev, "bad DRAW_INDEX_AUTO\n"); 1736 1731 return -EINVAL; 1737 1732 } 1738 1733 r = r600_cs_track_check(p); 1739 1734 if (r) { 1740 - dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1735 + dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 1741 1736 return r; 1742 1737 } 1743 1738 break; 1744 1739 case PACKET3_DRAW_INDEX_IMMD_BE: 1745 1740 case PACKET3_DRAW_INDEX_IMMD: 1746 1741 if (pkt->count < 2) { 1747 - DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 1742 + dev_warn_once(p->dev, "bad DRAW_INDEX_IMMD\n"); 1748 1743 return -EINVAL; 1749 1744 } 1750 1745 r = r600_cs_track_check(p); 1751 1746 if (r) { 1752 - dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1747 + dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 1753 1748 return r; 1754 1749 } 1755 1750 break; 1756 1751 case PACKET3_WAIT_REG_MEM: 1757 1752 if (pkt->count != 5) { 1758 - DRM_ERROR("bad WAIT_REG_MEM\n"); 1753 + dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); 1759 1754 return -EINVAL; 1760 1755 } 1761 1756 /* bit 4 is reg (0) or mem (1) */ ··· 1764 1759 1765 1760 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1766 1761 if (r) { 1767 - DRM_ERROR("bad WAIT_REG_MEM\n"); 1762 + dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); 1768 1763 return -EINVAL; 1769 1764 } 1770 1765 ··· 1775 1770 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); 1776 1771 ib[idx+2] = upper_32_bits(offset) & 0xff; 1777 1772 } else if (idx_value & 0x100) { 1778 - DRM_ERROR("cannot use PFP on REG wait\n"); 1773 + dev_warn_once(p->dev, "cannot use PFP on REG wait\n"); 1779 1774 return -EINVAL; 1780 1775 } 1781 1776 break; ··· 1784 1779 u32 command, size; 1785 1780 u64 offset, tmp; 1786 1781 if (pkt->count != 4) { 1787 - DRM_ERROR("bad CP DMA\n"); 1782 + dev_warn_once(p->dev, "bad CP DMA\n"); 1788 1783 return -EINVAL; 1789 1784 } 1790 1785 command = radeon_get_ib_value(p, idx+4); 1791 1786 size = command & 0x1fffff; 1792 1787 if (command & PACKET3_CP_DMA_CMD_SAS) { 1793 1788 /* src address space is register */ 1794 - DRM_ERROR("CP DMA SAS not supported\n"); 1789 + dev_warn_once(p->dev, "CP DMA SAS not supported\n"); 1795 1790 return -EINVAL; 1796 1791 } else { 1797 1792 if (command & PACKET3_CP_DMA_CMD_SAIC) { 1798 - DRM_ERROR("CP DMA SAIC only supported for registers\n"); 1793 + dev_warn_once(p->dev, "CP DMA SAIC only supported for registers\n"); 1799 1794 return -EINVAL; 1800 1795 } 1801 1796 /* src address space is memory */ 1802 1797 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1803 1798 if (r) { 1804 - DRM_ERROR("bad CP DMA SRC\n"); 1799 + dev_warn_once(p->dev, "bad CP DMA SRC\n"); 1805 1800 return -EINVAL; 1806 1801 } 1807 1802 ··· 1811 1806 offset = reloc->gpu_offset + tmp; 1812 1807 1813 1808 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1814 - dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", 1815 - tmp + size, radeon_bo_size(reloc->robj)); 1809 + dev_warn_once(p->dev, "CP DMA src buffer too small (%llu %lu)\n", 1810 + tmp + size, radeon_bo_size(reloc->robj)); 1816 1811 return -EINVAL; 1817 1812 } 1818 1813 ··· 1821 1816 } 1822 1817 if (command & PACKET3_CP_DMA_CMD_DAS) { 1823 1818 /* dst address space is register */ 1824 - DRM_ERROR("CP DMA DAS not supported\n"); 1819 + dev_warn_once(p->dev, "CP DMA DAS not supported\n"); 1825 1820 return -EINVAL; 1826 1821 } else { 1827 1822 /* dst address space is memory */ 1828 1823 if (command & PACKET3_CP_DMA_CMD_DAIC) { 1829 - DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1824 + dev_warn_once(p->dev, "CP DMA DAIC only supported for registers\n"); 1830 1825 return -EINVAL; 1831 1826 } 1832 1827 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1833 1828 if (r) { 1834 - DRM_ERROR("bad CP DMA DST\n"); 1829 + dev_warn_once(p->dev, "bad CP DMA DST\n"); 1835 1830 return -EINVAL; 1836 1831 } 1837 1832 ··· 1841 1836 offset = reloc->gpu_offset + tmp; 1842 1837 1843 1838 if ((tmp + size) > radeon_bo_size(reloc->robj)) { 1844 - dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", 1845 - tmp + size, radeon_bo_size(reloc->robj)); 1839 + dev_warn_once(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", 1840 + tmp + size, radeon_bo_size(reloc->robj)); 1846 1841 return -EINVAL; 1847 1842 } 1848 1843 ··· 1853 1848 } 1854 1849 case PACKET3_SURFACE_SYNC: 1855 1850 if (pkt->count != 3) { 1856 - DRM_ERROR("bad SURFACE_SYNC\n"); 1851 + dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); 1857 1852 return -EINVAL; 1858 1853 } 1859 1854 /* 0xffffffff/0x0 is flush all cache flag */ ··· 1861 1856 radeon_get_ib_value(p, idx + 2) != 0) { 1862 1857 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1863 1858 if (r) { 1864 - DRM_ERROR("bad SURFACE_SYNC\n"); 1859 + dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); 1865 1860 return -EINVAL; 1866 1861 } 1867 1862 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1869 1864 break; 1870 1865 case PACKET3_EVENT_WRITE: 1871 1866 if (pkt->count != 2 && pkt->count != 0) { 1872 - DRM_ERROR("bad EVENT_WRITE\n"); 1867 + dev_warn_once(p->dev, "bad EVENT_WRITE\n"); 1873 1868 return -EINVAL; 1874 1869 } 1875 1870 if (pkt->count) { ··· 1877 1872 1878 1873 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1879 1874 if (r) { 1880 - DRM_ERROR("bad EVENT_WRITE\n"); 1875 + dev_warn_once(p->dev, "bad EVENT_WRITE\n"); 1881 1876 return -EINVAL; 1882 1877 } 1883 1878 offset = reloc->gpu_offset + ··· 1893 1888 uint64_t offset; 1894 1889 1895 1890 if (pkt->count != 4) { 1896 - DRM_ERROR("bad EVENT_WRITE_EOP\n"); 1891 + dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); 1897 1892 return -EINVAL; 1898 1893 } 1899 1894 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1900 1895 if (r) { 1901 - DRM_ERROR("bad EVENT_WRITE\n"); 1896 + dev_warn_once(p->dev, "bad EVENT_WRITE\n"); 1902 1897 return -EINVAL; 1903 1898 } 1904 1899 ··· 1916 1911 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) || 1917 1912 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 1918 1913 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 1919 - DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 1914 + dev_warn_once(p->dev, "bad PACKET3_SET_CONFIG_REG\n"); 1920 1915 return -EINVAL; 1921 1916 } 1922 1917 for (i = 0; i < pkt->count; i++) { ··· 1932 1927 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) || 1933 1928 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 1934 1929 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 1935 - DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 1930 + dev_warn_once(p->dev, "bad PACKET3_SET_CONTEXT_REG\n"); 1936 1931 return -EINVAL; 1937 1932 } 1938 1933 for (i = 0; i < pkt->count; i++) { ··· 1944 1939 break; 1945 1940 case PACKET3_SET_RESOURCE: 1946 1941 if (pkt->count % 7) { 1947 - DRM_ERROR("bad SET_RESOURCE\n"); 1942 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 1948 1943 return -EINVAL; 1949 1944 } 1950 1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; ··· 1952 1947 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) || 1953 1948 (start_reg >= PACKET3_SET_RESOURCE_END) || 1954 1949 (end_reg >= PACKET3_SET_RESOURCE_END)) { 1955 - DRM_ERROR("bad SET_RESOURCE\n"); 1950 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 1956 1951 return -EINVAL; 1957 1952 } 1958 1953 for (i = 0; i < (pkt->count / 7); i++) { ··· 1964 1959 /* tex base */ 1965 1960 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1966 1961 if (r) { 1967 - DRM_ERROR("bad SET_RESOURCE\n"); 1962 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 1968 1963 return -EINVAL; 1969 1964 } 1970 1965 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1978 1973 /* tex mip base */ 1979 1974 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1980 1975 if (r) { 1981 - DRM_ERROR("bad SET_RESOURCE\n"); 1976 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 1982 1977 return -EINVAL; 1983 1978 } 1984 1979 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 1999 1994 /* vtx base */ 2000 1995 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2001 1996 if (r) { 2002 - DRM_ERROR("bad SET_RESOURCE\n"); 1997 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 2003 1998 return -EINVAL; 2004 1999 } 2005 2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 2006 2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; 2007 2002 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2008 2003 /* force size to size of the buffer */ 2009 - dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2010 - size + offset, radeon_bo_size(reloc->robj)); 2004 + dev_warn_once(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", 2005 + size + offset, radeon_bo_size(reloc->robj)); 2011 2006 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; 2012 2007 } 2013 2008 ··· 2020 2015 case SQ_TEX_VTX_INVALID_TEXTURE: 2021 2016 case SQ_TEX_VTX_INVALID_BUFFER: 2022 2017 default: 2023 - DRM_ERROR("bad SET_RESOURCE\n"); 2018 + dev_warn_once(p->dev, "bad SET_RESOURCE\n"); 2024 2019 return -EINVAL; 2025 2020 } 2026 2021 } ··· 2032 2027 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) || 2033 2028 (start_reg >= PACKET3_SET_ALU_CONST_END) || 2034 2029 (end_reg >= PACKET3_SET_ALU_CONST_END)) { 2035 - DRM_ERROR("bad SET_ALU_CONST\n"); 2030 + dev_warn_once(p->dev, "bad SET_ALU_CONST\n"); 2036 2031 return -EINVAL; 2037 2032 } 2038 2033 } ··· 2043 2038 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) || 2044 2039 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2045 2040 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2046 - DRM_ERROR("bad SET_BOOL_CONST\n"); 2041 + dev_warn_once(p->dev, "bad SET_BOOL_CONST\n"); 2047 2042 return -EINVAL; 2048 2043 } 2049 2044 break; ··· 2053 2048 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) || 2054 2049 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2055 2050 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2056 - DRM_ERROR("bad SET_LOOP_CONST\n"); 2051 + dev_warn_once(p->dev, "bad SET_LOOP_CONST\n"); 2057 2052 return -EINVAL; 2058 2053 } 2059 2054 break; ··· 2063 2058 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) || 2064 2059 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2065 2060 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2066 - DRM_ERROR("bad SET_CTL_CONST\n"); 2061 + dev_warn_once(p->dev, "bad SET_CTL_CONST\n"); 2067 2062 return -EINVAL; 2068 2063 } 2069 2064 break; 2070 2065 case PACKET3_SET_SAMPLER: 2071 2066 if (pkt->count % 3) { 2072 - DRM_ERROR("bad SET_SAMPLER\n"); 2067 + dev_warn_once(p->dev, "bad SET_SAMPLER\n"); 2073 2068 return -EINVAL; 2074 2069 } 2075 2070 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET; ··· 2077 2072 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) || 2078 2073 (start_reg >= PACKET3_SET_SAMPLER_END) || 2079 2074 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2080 - DRM_ERROR("bad SET_SAMPLER\n"); 2075 + dev_warn_once(p->dev, "bad SET_SAMPLER\n"); 2081 2076 return -EINVAL; 2082 2077 } 2083 2078 break; 2084 2079 case PACKET3_STRMOUT_BASE_UPDATE: 2085 2080 /* RS780 and RS880 also need this */ 2086 2081 if (p->family < CHIP_RS780) { 2087 - DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n"); 2082 + dev_warn_once(p->dev, "STRMOUT_BASE_UPDATE only supported on 7xx\n"); 2088 2083 return -EINVAL; 2089 2084 } 2090 2085 if (pkt->count != 1) { 2091 - DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n"); 2086 + dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE packet count\n"); 2092 2087 return -EINVAL; 2093 2088 } 2094 2089 if (idx_value > 3) { 2095 - DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n"); 2090 + dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE index\n"); 2096 2091 return -EINVAL; 2097 2092 } 2098 2093 { ··· 2100 2095 2101 2096 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2102 2097 if (r) { 2103 - DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2098 + dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE reloc\n"); 2104 2099 return -EINVAL; 2105 2100 } 2106 2101 2107 2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) { 2108 - DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n"); 2103 + dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE, bo does not match\n"); 2109 2104 return -EINVAL; 2110 2105 } 2111 2106 2112 2107 offset = (u64)radeon_get_ib_value(p, idx+1) << 8; 2113 2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) { 2114 - DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n", 2115 - offset, track->vgt_strmout_bo_offset[idx_value]); 2109 + dev_warn_once(p->dev, 2110 + "bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n", 2111 + offset, track->vgt_strmout_bo_offset[idx_value]); 2116 2112 return -EINVAL; 2117 2113 } 2118 2114 2119 2115 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2120 - DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n", 2121 - offset + 4, radeon_bo_size(reloc->robj)); 2116 + dev_warn_once(p->dev, 2117 + "bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n", 2118 + offset + 4, radeon_bo_size(reloc->robj)); 2122 2119 return -EINVAL; 2123 2120 } 2124 2121 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); ··· 2128 2121 break; 2129 2122 case PACKET3_SURFACE_BASE_UPDATE: 2130 2123 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { 2131 - DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2124 + dev_warn_once(p->dev, "bad SURFACE_BASE_UPDATE\n"); 2132 2125 return -EINVAL; 2133 2126 } 2134 2127 if (pkt->count) { 2135 - DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2128 + dev_warn_once(p->dev, "bad SURFACE_BASE_UPDATE\n"); 2136 2129 return -EINVAL; 2137 2130 } 2138 2131 break; 2139 2132 case PACKET3_STRMOUT_BUFFER_UPDATE: 2140 2133 if (pkt->count != 4) { 2141 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2134 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2142 2135 return -EINVAL; 2143 2136 } 2144 2137 /* Updating memory at DST_ADDRESS. */ ··· 2146 2139 u64 offset; 2147 2140 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2148 2141 if (r) { 2149 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2142 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2150 2143 return -EINVAL; 2151 2144 } 2152 2145 offset = radeon_get_ib_value(p, idx+1); 2153 2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2154 2147 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2155 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2156 - offset + 4, radeon_bo_size(reloc->robj)); 2148 + dev_warn_once(p->dev, 2149 + "bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2150 + offset + 4, radeon_bo_size(reloc->robj)); 2157 2151 return -EINVAL; 2158 2152 } 2159 2153 offset += reloc->gpu_offset; ··· 2166 2158 u64 offset; 2167 2159 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2168 2160 if (r) { 2169 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2161 + dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2170 2162 return -EINVAL; 2171 2163 } 2172 2164 offset = radeon_get_ib_value(p, idx+3); 2173 2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2174 2166 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2175 - DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2176 - offset + 4, radeon_bo_size(reloc->robj)); 2167 + dev_warn_once(p->dev, 2168 + "bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2169 + offset + 4, radeon_bo_size(reloc->robj)); 2177 2170 return -EINVAL; 2178 2171 } 2179 2172 offset += reloc->gpu_offset; ··· 2187 2178 u64 offset; 2188 2179 2189 2180 if (pkt->count != 3) { 2190 - DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2181 + dev_warn_once(p->dev, "bad MEM_WRITE (invalid count)\n"); 2191 2182 return -EINVAL; 2192 2183 } 2193 2184 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2194 2185 if (r) { 2195 - DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2186 + dev_warn_once(p->dev, "bad MEM_WRITE (missing reloc)\n"); 2196 2187 return -EINVAL; 2197 2188 } 2198 2189 offset = radeon_get_ib_value(p, idx+0); 2199 2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; 2200 2191 if (offset & 0x7) { 2201 - DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); 2192 + dev_warn_once(p->dev, "bad MEM_WRITE (address not qwords aligned)\n"); 2202 2193 return -EINVAL; 2203 2194 } 2204 2195 if ((offset + 8) > radeon_bo_size(reloc->robj)) { 2205 - DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", 2206 - offset + 8, radeon_bo_size(reloc->robj)); 2196 + dev_warn_once(p->dev, "bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", 2197 + offset + 8, radeon_bo_size(reloc->robj)); 2207 2198 return -EINVAL; 2208 2199 } 2209 2200 offset += reloc->gpu_offset; ··· 2213 2204 } 2214 2205 case PACKET3_COPY_DW: 2215 2206 if (pkt->count != 4) { 2216 - DRM_ERROR("bad COPY_DW (invalid count)\n"); 2207 + dev_warn_once(p->dev, "bad COPY_DW (invalid count)\n"); 2217 2208 return -EINVAL; 2218 2209 } 2219 2210 if (idx_value & 0x1) { ··· 2221 2212 /* SRC is memory. */ 2222 2213 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2223 2214 if (r) { 2224 - DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2215 + dev_warn_once(p->dev, "bad COPY_DW (missing src reloc)\n"); 2225 2216 return -EINVAL; 2226 2217 } 2227 2218 offset = radeon_get_ib_value(p, idx+1); 2228 2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2229 2220 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2230 - DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2231 - offset + 4, radeon_bo_size(reloc->robj)); 2221 + dev_warn_once(p->dev, "bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2222 + offset + 4, radeon_bo_size(reloc->robj)); 2232 2223 return -EINVAL; 2233 2224 } 2234 2225 offset += reloc->gpu_offset; ··· 2245 2236 /* DST is memory. */ 2246 2237 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2247 2238 if (r) { 2248 - DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2239 + dev_warn_once(p->dev, "bad COPY_DW (missing dst reloc)\n"); 2249 2240 return -EINVAL; 2250 2241 } 2251 2242 offset = radeon_get_ib_value(p, idx+3); 2252 2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2253 2244 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2254 - DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2255 - offset + 4, radeon_bo_size(reloc->robj)); 2245 + dev_warn_once(p->dev, "bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2246 + offset + 4, radeon_bo_size(reloc->robj)); 2256 2247 return -EINVAL; 2257 2248 } 2258 2249 offset += reloc->gpu_offset; ··· 2268 2259 case PACKET3_NOP: 2269 2260 break; 2270 2261 default: 2271 - DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2262 + dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); 2272 2263 return -EINVAL; 2273 2264 } 2274 2265 return 0; ··· 2315 2306 r = r600_packet3_check(p, &pkt); 2316 2307 break; 2317 2308 default: 2318 - DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2309 + dev_warn_once(p->dev, "Unknown packet type %d !\n", pkt.type); 2319 2310 kfree(p->track); 2320 2311 p->track = NULL; 2321 2312 return -EINVAL; ··· 2355 2346 2356 2347 *cs_reloc = NULL; 2357 2348 if (p->chunk_relocs == NULL) { 2358 - DRM_ERROR("No relocation chunk !\n"); 2349 + dev_warn_once(p->dev, "No relocation chunk !\n"); 2359 2350 return -EINVAL; 2360 2351 } 2361 2352 idx = p->dma_reloc_idx; 2362 2353 if (idx >= p->nrelocs) { 2363 - DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 2364 - idx, p->nrelocs); 2354 + dev_warn_once(p->dev, "Relocs at %d after relocations chunk end %d !\n", 2355 + idx, p->nrelocs); 2365 2356 return -EINVAL; 2366 2357 } 2367 2358 *cs_reloc = &p->relocs[idx]; ··· 2394 2385 2395 2386 do { 2396 2387 if (p->idx >= ib_chunk->length_dw) { 2397 - DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 2398 - p->idx, ib_chunk->length_dw); 2388 + dev_warn_once(p->dev, "Can not parse packet at %d after CS end %d !\n", 2389 + p->idx, ib_chunk->length_dw); 2399 2390 return -EINVAL; 2400 2391 } 2401 2392 idx = p->idx; ··· 2408 2399 case DMA_PACKET_WRITE: 2409 2400 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2410 2401 if (r) { 2411 - DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2402 + dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); 2412 2403 return -EINVAL; 2413 2404 } 2414 2405 if (tiled) { ··· 2426 2417 p->idx += count + 3; 2427 2418 } 2428 2419 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2429 - dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", 2430 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2420 + dev_warn_once(p->dev, "DMA write buffer too small (%llu %lu)\n", 2421 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2431 2422 return -EINVAL; 2432 2423 } 2433 2424 break; 2434 2425 case DMA_PACKET_COPY: 2435 2426 r = r600_dma_cs_next_reloc(p, &src_reloc); 2436 2427 if (r) { 2437 - DRM_ERROR("bad DMA_PACKET_COPY\n"); 2428 + dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); 2438 2429 return -EINVAL; 2439 2430 } 2440 2431 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2441 2432 if (r) { 2442 - DRM_ERROR("bad DMA_PACKET_COPY\n"); 2433 + dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); 2443 2434 return -EINVAL; 2444 2435 } 2445 2436 if (tiled) { ··· 2493 2484 } 2494 2485 } 2495 2486 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2496 - dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n", 2497 - src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2487 + dev_warn_once(p->dev, "DMA copy src buffer too small (%llu %lu)\n", 2488 + src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2498 2489 return -EINVAL; 2499 2490 } 2500 2491 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2501 - dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n", 2502 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2492 + dev_warn_once(p->dev, "DMA write dst buffer too small (%llu %lu)\n", 2493 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2503 2494 return -EINVAL; 2504 2495 } 2505 2496 break; 2506 2497 case DMA_PACKET_CONSTANT_FILL: 2507 2498 if (p->family < CHIP_RV770) { 2508 - DRM_ERROR("Constant Fill is 7xx only !\n"); 2499 + dev_warn_once(p->dev, "Constant Fill is 7xx only !\n"); 2509 2500 return -EINVAL; 2510 2501 } 2511 2502 r = r600_dma_cs_next_reloc(p, &dst_reloc); 2512 2503 if (r) { 2513 - DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2504 + dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); 2514 2505 return -EINVAL; 2515 2506 } 2516 2507 dst_offset = radeon_get_ib_value(p, idx+1); 2517 2508 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; 2518 2509 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2519 - dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", 2520 - dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2510 + dev_warn_once(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", 2511 + dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2521 2512 return -EINVAL; 2522 2513 } 2523 2514 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); ··· 2528 2519 p->idx += 1; 2529 2520 break; 2530 2521 default: 2531 - DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); 2522 + dev_warn_once(p->dev, "Unknown packet type %d at %d !\n", cmd, idx); 2532 2523 return -EINVAL; 2533 2524 } 2534 2525 } while (p->idx < p->chunk_ib->length_dw);
+1 -1
drivers/gpu/drm/radeon/radeon_cs.c
··· 834 834 ib = p->ib.ptr; 835 835 idx = pkt->idx; 836 836 for (i = 0; i <= (pkt->count + 1); i++, idx++) 837 - DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 837 + dev_dbg(p->dev, "ib[%d]=0x%08X\n", idx, ib[idx]); 838 838 } 839 839 840 840 /**
+10 -10
drivers/gpu/drm/radeon/radeon_legacy_encoders.c
··· 136 136 } 137 137 138 138 if (rdev->is_atom_bios) 139 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 139 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 140 140 else 141 - radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 141 + radeon_combios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 142 142 143 143 } 144 144 ··· 545 545 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 546 546 547 547 if (rdev->is_atom_bios) 548 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 548 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 549 549 else 550 - radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 550 + radeon_combios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 551 551 552 552 } 553 553 ··· 742 742 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 743 743 744 744 if (rdev->is_atom_bios) 745 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 745 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 746 746 else 747 - radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 747 + radeon_combios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 748 748 749 749 } 750 750 ··· 908 908 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 909 909 910 910 if (rdev->is_atom_bios) 911 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 911 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 912 912 else 913 - radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 913 + radeon_combios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 914 914 915 915 } 916 916 ··· 1113 1113 } 1114 1114 1115 1115 if (rdev->is_atom_bios) 1116 - radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1116 + radeon_atombios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 1117 1117 else 1118 - radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1118 + radeon_combios_encoder_dpms_scratch_regs(encoder, mode == DRM_MODE_DPMS_ON); 1119 1119 1120 1120 } 1121 1121
+1 -2
drivers/gpu/drm/radeon/radeon_pm.c
··· 907 907 908 908 static bool radeon_dpm_single_display(struct radeon_device *rdev) 909 909 { 910 - bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 911 - true : false; 910 + bool single_display = rdev->pm.dpm.new_active_crtc_count < 2; 912 911 913 912 /* check if the vblank period is too short to adjust the mclk */ 914 913 if (single_display && rdev->asic->dpm.vblank_too_short) {
+54 -1
include/uapi/drm/amdgpu_drm.h
··· 57 57 #define DRM_AMDGPU_USERQ 0x16 58 58 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 59 59 #define DRM_AMDGPU_USERQ_WAIT 0x18 60 + #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 60 61 61 62 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 62 63 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) ··· 78 77 #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) 79 78 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) 80 79 #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) 80 + #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) 81 81 82 82 /** 83 83 * DOC: memory domains ··· 802 800 803 801 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 804 802 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 803 + #define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 804 + 805 + struct drm_amdgpu_gem_vm_entry { 806 + /* Start of mapping (in bytes) */ 807 + __u64 addr; 808 + 809 + /* Size of mapping (in bytes) */ 810 + __u64 size; 811 + 812 + /* Mapping offset */ 813 + __u64 offset; 814 + 815 + /* flags needed to recreate mapping */ 816 + __u64 flags; 817 + }; 805 818 806 819 /* Sets or returns a value associated with a buffer. */ 807 820 struct drm_amdgpu_gem_op { ··· 824 807 __u32 handle; 825 808 /** AMDGPU_GEM_OP_* */ 826 809 __u32 op; 827 - /** Input or return value */ 810 + /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ 828 811 __u64 value; 812 + /** For MAPPING_INFO op: number of mappings (in/out) */ 813 + __u32 num_entries; 814 + 815 + __u32 padding; 816 + }; 817 + 818 + #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) 819 + 820 + struct drm_amdgpu_gem_list_handles { 821 + /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ 822 + __u64 entries; 823 + 824 + /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ 825 + __u32 num_entries; 826 + 827 + __u32 padding; 828 + }; 829 + 830 + struct drm_amdgpu_gem_list_handles_entry { 831 + /* gem handle of buffer object */ 832 + __u32 gem_handle; 833 + 834 + /* Currently just one flag: IS_IMPORT */ 835 + __u32 flags; 836 + 837 + /* Size of bo */ 838 + __u64 size; 839 + 840 + /* Preferred domains for GEM_CREATE */ 841 + __u64 preferred_domains; 842 + 843 + /* GEM_CREATE flags for re-creation of buffer */ 844 + __u64 alloc_flags; 845 + 846 + /* physical start_addr alignment in bytes for some HW requirements */ 847 + __u64 alignment; 829 848 }; 830 849 831 850 #define AMDGPU_VA_OP_MAP 1