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drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched

[why]
1. With allow_0_dtb_clk enabled, the time required to latch DTBCLK to 600 MHz
depends on the SMU. If DTBCLK is not latched to 600 MHz before set_mode completes,
gating DTBCLK causes the DP2 sink to lose its clock source.

2. The existing DTBCLK gating sequence ungates DTBCLK based on both pix_clk and ref_dtbclk,
but gates DTBCLK when either pix_clk or ref_dtbclk is zero.
pix_clk can be zero outside the set_mode sequence before DTBCLK is properly latched,
which can lead to DTBCLK being gated by mistake.

[how]
Consider both pixel_clk and ref_dtbclk when determining when it is safe to gate DTBCLK;
this is more accurate.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4701
Fixes: 5949e7c4890c ("drm/amd/display: Enable Dynamic DTBCLK Switch")
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit d04eb0c402780ca037b62a6aecf23b863545ebca)
Cc: stable@vger.kernel.org

authored by

Fangzhi Zuo and committed by
Alex Deucher cfa0904a 6a23ae0a

+4 -2
+3 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
··· 394 394 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps); 395 395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) 396 396 new_clocks->ref_dtbclk_khz = 600000; 397 + else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000) 398 + new_clocks->ref_dtbclk_khz = 0; 397 399 398 400 /* 399 401 * if it is safe to lower, but we are already in the lower state, we don't have to do anything ··· 437 435 438 436 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT); 439 437 440 - if (actual_dtbclk) { 438 + if (actual_dtbclk > 590000) { 441 439 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; 442 440 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 443 441 }
+1 -1
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
··· 1411 1411 __func__, params->otg_inst, params->pixclk_khz, 1412 1412 params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo); 1413 1413 1414 - } else { 1414 + } else if (!params->ref_dtbclk_khz && !req_dtbclk_khz) { 1415 1415 switch (params->otg_inst) { 1416 1416 case 0: 1417 1417 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);