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dt-bindings: dma: fsl-edma: Convert to DT schema
Convert the eDMA controller binding to DT schema.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220620020002.3966343-1-peng.fan@oss.nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Peng Fan
and committed by
Vinod Koul
cfa1927f
a7a5c1a9
+155
-111
+155
Documentation/devicetree/bindings/dma/fsl,edma.yaml
+155
Documentation/devicetree/bindings/dma/fsl,edma.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale enhanced Direct Memory Access(eDMA) Controller
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description: |
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The eDMA channels have multiplex capability by programmable
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memory-mapped registers. channels are split into two groups, called
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DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
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by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,vf610-edma
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- fsl,imx7ulp-edma
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- items:
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- const: fsl,ls1028a-edma
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- const: fsl,vf610-edma
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reg:
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minItems: 2
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maxItems: 3
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interrupts:
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minItems: 2
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maxItems: 17
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interrupt-names:
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minItems: 2
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maxItems: 17
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+
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"#dma-cells":
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const: 2
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dma-channels:
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const: 32
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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big-endian:
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description: |
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If present registers and hardware scatter/gather descriptors of the
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eDMA are implemented in big endian mode, otherwise in little mode.
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type: boolean
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- dma-channels
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+
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allOf:
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- $ref: "dma-controller.yaml#"
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- if:
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properties:
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compatible:
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contains:
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const: fsl,vf610-edma
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then:
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properties:
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clock-names:
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items:
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- const: dmamux0
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- const: dmamux1
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: edma-tx
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- const: edma-err
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reg:
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maxItems: 3
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+
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx7ulp-edma
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then:
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properties:
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clock-names:
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items:
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- const: dma
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- const: dmamux0
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interrupts:
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maxItems: 17
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reg:
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maxItems: 2
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/vf610-clock.h>
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edma0: dma-controller@40018000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40018000 0x2000>,
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<0x40024000 0x1000>,
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<0x40025000 0x1000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx7ulp-clock.h>
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edma1: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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/* last is eDMA2-ERR interrupt */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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};
-111
Documentation/devicetree/bindings/dma/fsl-edma.txt
-111
Documentation/devicetree/bindings/dma/fsl-edma.txt
···
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* Freescale enhanced Direct Memory Access(eDMA) Controller
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The eDMA channels have multiplex capability by programmble memory-mapped
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registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
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specific DMA request source can only be multiplexed by any channel of certain
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group, DMAMUX0 or DMAMUX1, but not both.
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* eDMA Controller
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Required properties:
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- compatible :
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- "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
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- "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp
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- "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the
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LS1028A SoC.
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- reg : Specifies base physical address(s) and size of the eDMA registers.
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The 1st region is eDMA control register's address and size.
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The 2nd and the 3rd regions are programmable channel multiplexing
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control register's address and size.
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- interrupts : A list of interrupt-specifiers, one for each entry in
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interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel
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per transmission interrupt, total 16 channel interrupt and 1
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error interrupt(located in the last), no interrupt-names list on
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i.mx7ulp for clean on dts.
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- #dma-cells : Must be <2>.
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The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
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Specific request source can only be multiplexed by specific channels
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group called DMAMUX.
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The 2nd cell specifies the request source(slot) ID.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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- clock-names : A list of channel group clock names. Should contain:
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"dmamux0" - clock name of mux0 group
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"dmamux1" - clock name of mux1 group
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Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp.
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- clocks : A list of phandle and clock-specifier pairs, one for each entry in
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clock-names.
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Optional properties:
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- big-endian: If present registers and hardware scatter/gather descriptors
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of the eDMA are implemented in big endian mode, otherwise in little
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mode.
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- interrupt-names : Should contain the below on vf610 similar SoC but not used
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on i.mx7ulp similar SoC:
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"edma-tx" - the transmission interrupt
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"edma-err" - the error interrupt
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-
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Examples:
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edma0: dma-controller@40018000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40018000 0x2000>,
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<0x40024000 0x1000>,
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<0x40025000 0x1000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX0>,
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<&clks VF610_CLK_DMAMUX1>;
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}; /* vf610 */
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edma1: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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/* last is eDMA2-ERR interrupt */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
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<&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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}; /* i.mx7ulp */
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* DMA clients
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DMA client drivers that uses the DMA function must use the format described
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in the dma.txt file, using a two-cell specifier for each channel: the 1st
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specifies the channel group(DMAMUX) in which this request can be multiplexed,
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and the 2nd specifies the request source.
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Examples:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "sai";
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clocks = <&clks VF610_CLK_SAI2>;
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dma-names = "tx", "rx";
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dmas = <&edma0 0 21>,
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<&edma0 0 20>;
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};