tjh.dev / kernel
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Merge branch 'net-stmmac-rk-second-chunk-of-cleanups'

Russell King says:

====================
net: stmmac: rk: second chunk of cleanups

This series is a cut-down installment of the dwmac-rk cleanups, covering
up to the point that the AI review had its first issue with the patches.
Unfortunately, this means that we introduce ->init but do not add any
users for it yet. That will be in the next round once this has got
through AI review and merged.
====================

Link: https://patch.msgid.link/aXnrzIbZN-gaZTia@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski cff3e7c6 0e4d7df2

+57 -63
+57 -63
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
··· 35 35 }; 36 36 37 37 struct rk_gmac_ops { 38 + int (*init)(struct rk_priv_data *bsp_priv); 38 39 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, 39 40 int tx_delay, int rx_delay); 40 41 void (*set_to_rmii)(struct rk_priv_data *bsp_priv); ··· 91 90 struct regmap *grf; 92 91 struct regmap *php_grf; 93 92 }; 93 + 94 + #define GMAC_CLK_DIV1_125M 0 95 + #define GMAC_CLK_DIV50_2_5M 2 96 + #define GMAC_CLK_DIV5_25M 3 94 97 95 98 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv, 96 99 const struct rk_reg_speed_data *rsd, ··· 304 299 #define RK3128_GMAC_SPEED_100M GRF_BIT(10) 305 300 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) 306 301 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 307 - #define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0) 308 - #define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3) 309 - #define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2) 302 + #define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val) 310 303 #define RK3128_GMAC_RMII_MODE GRF_BIT(14) 311 304 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 312 305 ··· 328 325 } 329 326 330 327 static const struct rk_reg_speed_data rk3128_reg_speed_data = { 331 - .rgmii_10 = RK3128_GMAC_CLK_2_5M, 332 - .rgmii_100 = RK3128_GMAC_CLK_25M, 333 - .rgmii_1000 = RK3128_GMAC_CLK_125M, 328 + .rgmii_10 = RK3128_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 329 + .rgmii_100 = RK3128_GMAC_CLK(GMAC_CLK_DIV5_25M), 330 + .rgmii_1000 = RK3128_GMAC_CLK(GMAC_CLK_DIV1_125M), 334 331 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M, 335 332 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M, 336 333 }; ··· 365 362 #define RK3228_GMAC_SPEED_100M GRF_BIT(2) 366 363 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) 367 364 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 368 - #define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0) 369 - #define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3) 370 - #define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2) 365 + #define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val) 371 366 #define RK3228_GMAC_RMII_MODE GRF_BIT(10) 372 367 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) 373 368 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) ··· 400 399 } 401 400 402 401 static const struct rk_reg_speed_data rk3228_reg_speed_data = { 403 - .rgmii_10 = RK3228_GMAC_CLK_2_5M, 404 - .rgmii_100 = RK3228_GMAC_CLK_25M, 405 - .rgmii_1000 = RK3228_GMAC_CLK_125M, 402 + .rgmii_10 = RK3228_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 403 + .rgmii_100 = RK3228_GMAC_CLK(GMAC_CLK_DIV5_25M), 404 + .rgmii_1000 = RK3228_GMAC_CLK(GMAC_CLK_DIV1_125M), 406 405 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M, 407 406 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M, 408 407 }; ··· 441 440 #define RK3288_GMAC_SPEED_100M GRF_BIT(10) 442 441 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) 443 442 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) 444 - #define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0) 445 - #define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3) 446 - #define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2) 443 + #define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val) 447 444 #define RK3288_GMAC_RMII_MODE GRF_BIT(14) 448 445 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) 449 446 ··· 473 474 } 474 475 475 476 static const struct rk_reg_speed_data rk3288_reg_speed_data = { 476 - .rgmii_10 = RK3288_GMAC_CLK_2_5M, 477 - .rgmii_100 = RK3288_GMAC_CLK_25M, 478 - .rgmii_1000 = RK3288_GMAC_CLK_125M, 477 + .rgmii_10 = RK3288_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 478 + .rgmii_100 = RK3288_GMAC_CLK(GMAC_CLK_DIV5_25M), 479 + .rgmii_1000 = RK3288_GMAC_CLK(GMAC_CLK_DIV1_125M), 479 480 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M, 480 481 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M, 481 482 }; ··· 542 543 #define RK3328_GMAC_SPEED_100M GRF_BIT(2) 543 544 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) 544 545 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) 545 - #define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0) 546 - #define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3) 547 - #define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2) 546 + #define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val) 548 547 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 549 548 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 550 549 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) ··· 577 580 } 578 581 579 582 static const struct rk_reg_speed_data rk3328_reg_speed_data = { 580 - .rgmii_10 = RK3328_GMAC_CLK_2_5M, 581 - .rgmii_100 = RK3328_GMAC_CLK_25M, 582 - .rgmii_1000 = RK3328_GMAC_CLK_125M, 583 + .rgmii_10 = RK3328_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 584 + .rgmii_100 = RK3328_GMAC_CLK(GMAC_CLK_DIV5_25M), 585 + .rgmii_1000 = RK3328_GMAC_CLK(GMAC_CLK_DIV1_125M), 583 586 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M, 584 587 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M, 585 588 }; ··· 629 632 #define RK3366_GMAC_SPEED_100M GRF_BIT(7) 630 633 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) 631 634 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 632 - #define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 633 - #define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 634 - #define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 635 + #define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 635 636 #define RK3366_GMAC_RMII_MODE GRF_BIT(6) 636 637 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 637 638 ··· 661 666 } 662 667 663 668 static const struct rk_reg_speed_data rk3366_reg_speed_data = { 664 - .rgmii_10 = RK3366_GMAC_CLK_2_5M, 665 - .rgmii_100 = RK3366_GMAC_CLK_25M, 666 - .rgmii_1000 = RK3366_GMAC_CLK_125M, 669 + .rgmii_10 = RK3366_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 670 + .rgmii_100 = RK3366_GMAC_CLK(GMAC_CLK_DIV5_25M), 671 + .rgmii_1000 = RK3366_GMAC_CLK(GMAC_CLK_DIV1_125M), 667 672 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M, 668 673 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M, 669 674 }; ··· 692 697 #define RK3368_GMAC_SPEED_100M GRF_BIT(7) 693 698 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) 694 699 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 695 - #define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 696 - #define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 697 - #define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 700 + #define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 698 701 #define RK3368_GMAC_RMII_MODE GRF_BIT(6) 699 702 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 700 703 ··· 724 731 } 725 732 726 733 static const struct rk_reg_speed_data rk3368_reg_speed_data = { 727 - .rgmii_10 = RK3368_GMAC_CLK_2_5M, 728 - .rgmii_100 = RK3368_GMAC_CLK_25M, 729 - .rgmii_1000 = RK3368_GMAC_CLK_125M, 734 + .rgmii_10 = RK3368_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 735 + .rgmii_100 = RK3368_GMAC_CLK(GMAC_CLK_DIV5_25M), 736 + .rgmii_1000 = RK3368_GMAC_CLK(GMAC_CLK_DIV1_125M), 730 737 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M, 731 738 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M, 732 739 }; ··· 755 762 #define RK3399_GMAC_SPEED_100M GRF_BIT(7) 756 763 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) 757 764 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) 758 - #define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0) 759 - #define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3) 760 - #define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2) 765 + #define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val) 761 766 #define RK3399_GMAC_RMII_MODE GRF_BIT(6) 762 767 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) 763 768 ··· 787 796 } 788 797 789 798 static const struct rk_reg_speed_data rk3399_reg_speed_data = { 790 - .rgmii_10 = RK3399_GMAC_CLK_2_5M, 791 - .rgmii_100 = RK3399_GMAC_CLK_25M, 792 - .rgmii_1000 = RK3399_GMAC_CLK_125M, 799 + .rgmii_10 = RK3399_GMAC_CLK(GMAC_CLK_DIV50_2_5M), 800 + .rgmii_100 = RK3399_GMAC_CLK(GMAC_CLK_DIV5_25M), 801 + .rgmii_1000 = RK3399_GMAC_CLK(GMAC_CLK_DIV1_125M), 793 802 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M, 794 803 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M, 795 804 }; ··· 896 905 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) 897 906 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) 898 907 899 - #define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0) 900 - #define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3) 901 - #define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2) 908 + #define RK3528_GMAC1_CLK_RGMII(val) GRF_FIELD_CONST(11, 10, val) 902 909 903 910 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) 904 911 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) ··· 934 945 }; 935 946 936 947 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = { 937 - .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50, 938 - .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5, 939 - .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1, 948 + .rgmii_10 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV50_2_5M), 949 + .rgmii_100 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV5_25M), 950 + .rgmii_1000 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV1_125M), 940 951 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20, 941 952 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2, 942 953 }; ··· 1088 1099 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5) 1089 1100 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5) 1090 1101 1091 - #define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0) 1092 - #define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3) 1093 - #define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2) 1102 + #define RK3576_GMAC_CLK_RGMII(val) GRF_FIELD_CONST(6, 5, val) 1094 1103 1095 1104 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4) 1096 1105 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4) ··· 1132 1145 } 1133 1146 1134 1147 static const struct rk_reg_speed_data rk3578_reg_speed_data = { 1135 - .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50, 1136 - .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5, 1137 - .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1, 1148 + .rgmii_10 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV50_2_5M), 1149 + .rgmii_100 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV5_25M), 1150 + .rgmii_1000 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV1_125M), 1138 1151 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20, 1139 1152 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2, 1140 1153 }; ··· 1210 1223 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) 1211 1224 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) 1212 1225 1213 - #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ 1214 - (GRF_FIELD_CONST(3, 2, 0) << ((id) * 5)) 1215 - #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ 1216 - (GRF_FIELD_CONST(3, 2, 3) << ((id) * 5)) 1217 - #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ 1218 - (GRF_FIELD_CONST(3, 2, 2) << ((id) * 5)) 1226 + #define RK3588_GMAC_CLK_RGMII(id, val) \ 1227 + (GRF_FIELD_CONST(3, 2, val) << ((id) * 5)) 1219 1228 1220 1229 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) 1221 1230 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) ··· 1258 1275 if (interface == PHY_INTERFACE_MODE_RMII) 1259 1276 val = RK3588_GMA_CLK_RMII_DIV20(id); 1260 1277 else 1261 - val = RK3588_GMAC_CLK_RGMII_DIV50(id); 1278 + val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV50_2_5M); 1262 1279 break; 1263 1280 case 100: 1264 1281 if (interface == PHY_INTERFACE_MODE_RMII) 1265 1282 val = RK3588_GMA_CLK_RMII_DIV2(id); 1266 1283 else 1267 - val = RK3588_GMAC_CLK_RGMII_DIV5(id); 1284 + val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV5_25M); 1268 1285 break; 1269 1286 case 1000: 1270 1287 if (interface != PHY_INTERFACE_MODE_RMII) 1271 - val = RK3588_GMAC_CLK_RGMII_DIV1(id); 1288 + val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV1_125M); 1272 1289 else 1273 1290 goto err; 1274 1291 break; ··· 1619 1636 1620 1637 bsp_priv->dev = dev; 1621 1638 1639 + if (ops->init) { 1640 + ret = ops->init(bsp_priv); 1641 + if (ret) { 1642 + reset_control_put(bsp_priv->phy_reset); 1643 + dev_err_probe(dev, ret, "failed to init BSP\n"); 1644 + return ERR_PTR(ret); 1645 + } 1646 + } 1647 + 1622 1648 return bsp_priv; 1623 1649 } 1624 1650 ··· 1776 1784 1777 1785 if (priv->plat->phy_node && bsp_priv->integrated_phy) 1778 1786 clk_put(bsp_priv->clk_phy); 1787 + 1788 + reset_control_put(bsp_priv->phy_reset); 1779 1789 } 1780 1790 1781 1791 static int rk_gmac_probe(struct platform_device *pdev)