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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
ASoC: fsl_mqs: Add i.MX95 platform support
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>:
There are two MQS instances on the i.MX95 platform.
The definition of bit positions in the control register are
different. In order to support these MQS modules, define
two compatible strings to distinguish them.
+42
-6
+2
Documentation/devicetree/bindings/sound/fsl,mqs.yaml
+2
Documentation/devicetree/bindings/sound/fsl,mqs.yaml
+40
-6
sound/soc/fsl/fsl_mqs.c
+40
-6
sound/soc/fsl/fsl_mqs.c
···
28
28
#define MQS_CLK_DIV_MASK (0xFF << 0)
29
29
#define MQS_CLK_DIV_SHIFT (0)
30
30
31
+
enum reg_type {
32
+
TYPE_REG_OWN, /* module own register space */
33
+
TYPE_REG_GPR, /* register in GPR space */
34
+
TYPE_REG_SM, /* System Manager controls the register */
35
+
};
36
+
31
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/**
32
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* struct fsl_mqs_soc_data - soc specific data
33
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*
34
-
* @use_gpr: control register is in General Purpose Register group
40
+
* @type: control register space type
35
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* @ctrl_off: control register offset
36
42
* @en_mask: enable bit mask
37
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* @en_shift: enable bit shift
···
49
43
* @div_shift: clock divider bit shift
50
44
*/
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struct fsl_mqs_soc_data {
52
-
bool use_gpr;
46
+
enum reg_type type;
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int ctrl_off;
54
48
int en_mask;
55
49
int en_shift;
···
206
200
*/
207
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mqs_priv->soc = of_device_get_match_data(&pdev->dev);
208
202
209
-
if (mqs_priv->soc->use_gpr) {
203
+
if (mqs_priv->soc->type == TYPE_REG_GPR) {
210
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gpr_np = of_parse_phandle(np, "gpr", 0);
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if (!gpr_np) {
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dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
···
310
304
};
311
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static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
313
-
.use_gpr = false,
307
+
.type = TYPE_REG_OWN,
314
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.ctrl_off = REG_MQS_CTRL,
315
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.en_mask = MQS_EN_MASK,
316
310
.en_shift = MQS_EN_SHIFT,
···
323
317
};
324
318
325
319
static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
326
-
.use_gpr = true,
320
+
.type = TYPE_REG_GPR,
327
321
.ctrl_off = IOMUXC_GPR2,
328
322
.en_mask = IMX6SX_GPR2_MQS_EN_MASK,
329
323
.en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
···
336
330
};
337
331
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static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
339
-
.use_gpr = true,
333
+
.type = TYPE_REG_GPR,
340
334
.ctrl_off = 0x20,
341
335
.en_mask = BIT(1),
342
336
.en_shift = 1,
···
348
342
.div_shift = 8,
349
343
};
350
344
345
+
static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = {
346
+
.type = TYPE_REG_SM,
347
+
.ctrl_off = 0x88,
348
+
.en_mask = BIT(1),
349
+
.en_shift = 1,
350
+
.rst_mask = BIT(2),
351
+
.rst_shift = 2,
352
+
.osr_mask = BIT(3),
353
+
.osr_shift = 3,
354
+
.div_mask = GENMASK(15, 8),
355
+
.div_shift = 8,
356
+
};
357
+
358
+
static const struct fsl_mqs_soc_data fsl_mqs_imx95_netc_data = {
359
+
.type = TYPE_REG_GPR,
360
+
.ctrl_off = 0x0,
361
+
.en_mask = BIT(2),
362
+
.en_shift = 2,
363
+
.rst_mask = BIT(3),
364
+
.rst_shift = 3,
365
+
.osr_mask = BIT(4),
366
+
.osr_shift = 4,
367
+
.div_mask = GENMASK(16, 9),
368
+
.div_shift = 9,
369
+
};
370
+
351
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static const struct of_device_id fsl_mqs_dt_ids[] = {
352
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{ .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
353
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{ .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
354
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{ .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
375
+
{ .compatible = "fsl,imx95-aonmix-mqs", .data = &fsl_mqs_imx95_aon_data },
376
+
{ .compatible = "fsl,imx95-netcmix-mqs", .data = &fsl_mqs_imx95_netc_data },
355
377
{}
356
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};
357
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MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);