Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'spi/next' of git://git.secretlab.ca/git/linux-2.6
* 'spi/next' of git://git.secretlab.ca/git/linux-2.6:
spi/spi_bfin_sport: new driver for a SPI bus via the Blackfin SPORT peripheral
spi/tle620x: add missing device_remove_file()
+964
-1
+9
drivers/spi/Kconfig
+9
drivers/spi/Kconfig
···
80
80
help
81
81
This is the SPI controller master driver for Blackfin 5xx processor.
82
82
83
+
config SPI_BFIN_SPORT
84
+
tristate "SPI bus via Blackfin SPORT"
85
+
depends on BLACKFIN
86
+
help
87
+
Enable support for a SPI bus via the Blackfin SPORT peripheral.
88
+
89
+
This driver can also be built as a module. If so, the module
90
+
will be called spi_bfin_sport.
91
+
83
92
config SPI_AU1550
84
93
tristate "Au1550/Au12x0 SPI Controller"
85
94
depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL
+1
drivers/spi/Makefile
+1
drivers/spi/Makefile
···
13
13
obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
14
14
obj-$(CONFIG_SPI_ATH79) += ath79_spi.o
15
15
obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
16
+
obj-$(CONFIG_SPI_BFIN_SPORT) += spi_bfin_sport.o
16
17
obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
17
18
obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
18
19
obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
+952
drivers/spi/spi_bfin_sport.c
+952
drivers/spi/spi_bfin_sport.c
···
1
+
/*
2
+
* SPI bus via the Blackfin SPORT peripheral
3
+
*
4
+
* Enter bugs at http://blackfin.uclinux.org/
5
+
*
6
+
* Copyright 2009-2011 Analog Devices Inc.
7
+
*
8
+
* Licensed under the GPL-2 or later.
9
+
*/
10
+
11
+
#include <linux/init.h>
12
+
#include <linux/module.h>
13
+
#include <linux/delay.h>
14
+
#include <linux/device.h>
15
+
#include <linux/gpio.h>
16
+
#include <linux/io.h>
17
+
#include <linux/ioport.h>
18
+
#include <linux/irq.h>
19
+
#include <linux/errno.h>
20
+
#include <linux/interrupt.h>
21
+
#include <linux/platform_device.h>
22
+
#include <linux/spi/spi.h>
23
+
#include <linux/workqueue.h>
24
+
25
+
#include <asm/portmux.h>
26
+
#include <asm/bfin5xx_spi.h>
27
+
#include <asm/blackfin.h>
28
+
#include <asm/bfin_sport.h>
29
+
#include <asm/cacheflush.h>
30
+
31
+
#define DRV_NAME "bfin-sport-spi"
32
+
#define DRV_DESC "SPI bus via the Blackfin SPORT"
33
+
34
+
MODULE_AUTHOR("Cliff Cai");
35
+
MODULE_DESCRIPTION(DRV_DESC);
36
+
MODULE_LICENSE("GPL");
37
+
MODULE_ALIAS("platform:bfin-sport-spi");
38
+
39
+
enum bfin_sport_spi_state {
40
+
START_STATE,
41
+
RUNNING_STATE,
42
+
DONE_STATE,
43
+
ERROR_STATE,
44
+
};
45
+
46
+
struct bfin_sport_spi_master_data;
47
+
48
+
struct bfin_sport_transfer_ops {
49
+
void (*write) (struct bfin_sport_spi_master_data *);
50
+
void (*read) (struct bfin_sport_spi_master_data *);
51
+
void (*duplex) (struct bfin_sport_spi_master_data *);
52
+
};
53
+
54
+
struct bfin_sport_spi_master_data {
55
+
/* Driver model hookup */
56
+
struct device *dev;
57
+
58
+
/* SPI framework hookup */
59
+
struct spi_master *master;
60
+
61
+
/* Regs base of SPI controller */
62
+
struct sport_register __iomem *regs;
63
+
int err_irq;
64
+
65
+
/* Pin request list */
66
+
u16 *pin_req;
67
+
68
+
/* Driver message queue */
69
+
struct workqueue_struct *workqueue;
70
+
struct work_struct pump_messages;
71
+
spinlock_t lock;
72
+
struct list_head queue;
73
+
int busy;
74
+
bool run;
75
+
76
+
/* Message Transfer pump */
77
+
struct tasklet_struct pump_transfers;
78
+
79
+
/* Current message transfer state info */
80
+
enum bfin_sport_spi_state state;
81
+
struct spi_message *cur_msg;
82
+
struct spi_transfer *cur_transfer;
83
+
struct bfin_sport_spi_slave_data *cur_chip;
84
+
union {
85
+
void *tx;
86
+
u8 *tx8;
87
+
u16 *tx16;
88
+
};
89
+
void *tx_end;
90
+
union {
91
+
void *rx;
92
+
u8 *rx8;
93
+
u16 *rx16;
94
+
};
95
+
void *rx_end;
96
+
97
+
int cs_change;
98
+
struct bfin_sport_transfer_ops *ops;
99
+
};
100
+
101
+
struct bfin_sport_spi_slave_data {
102
+
u16 ctl_reg;
103
+
u16 baud;
104
+
u16 cs_chg_udelay; /* Some devices require > 255usec delay */
105
+
u32 cs_gpio;
106
+
u16 idle_tx_val;
107
+
struct bfin_sport_transfer_ops *ops;
108
+
};
109
+
110
+
static void
111
+
bfin_sport_spi_enable(struct bfin_sport_spi_master_data *drv_data)
112
+
{
113
+
bfin_write_or(&drv_data->regs->tcr1, TSPEN);
114
+
bfin_write_or(&drv_data->regs->rcr1, TSPEN);
115
+
SSYNC();
116
+
}
117
+
118
+
static void
119
+
bfin_sport_spi_disable(struct bfin_sport_spi_master_data *drv_data)
120
+
{
121
+
bfin_write_and(&drv_data->regs->tcr1, ~TSPEN);
122
+
bfin_write_and(&drv_data->regs->rcr1, ~TSPEN);
123
+
SSYNC();
124
+
}
125
+
126
+
/* Caculate the SPI_BAUD register value based on input HZ */
127
+
static u16
128
+
bfin_sport_hz_to_spi_baud(u32 speed_hz)
129
+
{
130
+
u_long clk, sclk = get_sclk();
131
+
int div = (sclk / (2 * speed_hz)) - 1;
132
+
133
+
if (div < 0)
134
+
div = 0;
135
+
136
+
clk = sclk / (2 * (div + 1));
137
+
138
+
if (clk > speed_hz)
139
+
div++;
140
+
141
+
return div;
142
+
}
143
+
144
+
/* Chip select operation functions for cs_change flag */
145
+
static void
146
+
bfin_sport_spi_cs_active(struct bfin_sport_spi_slave_data *chip)
147
+
{
148
+
gpio_direction_output(chip->cs_gpio, 0);
149
+
}
150
+
151
+
static void
152
+
bfin_sport_spi_cs_deactive(struct bfin_sport_spi_slave_data *chip)
153
+
{
154
+
gpio_direction_output(chip->cs_gpio, 1);
155
+
/* Move delay here for consistency */
156
+
if (chip->cs_chg_udelay)
157
+
udelay(chip->cs_chg_udelay);
158
+
}
159
+
160
+
static void
161
+
bfin_sport_spi_stat_poll_complete(struct bfin_sport_spi_master_data *drv_data)
162
+
{
163
+
unsigned long timeout = jiffies + HZ;
164
+
while (!(bfin_read(&drv_data->regs->stat) & RXNE)) {
165
+
if (!time_before(jiffies, timeout))
166
+
break;
167
+
}
168
+
}
169
+
170
+
static void
171
+
bfin_sport_spi_u8_writer(struct bfin_sport_spi_master_data *drv_data)
172
+
{
173
+
u16 dummy;
174
+
175
+
while (drv_data->tx < drv_data->tx_end) {
176
+
bfin_write(&drv_data->regs->tx16, *drv_data->tx8++);
177
+
bfin_sport_spi_stat_poll_complete(drv_data);
178
+
dummy = bfin_read(&drv_data->regs->rx16);
179
+
}
180
+
}
181
+
182
+
static void
183
+
bfin_sport_spi_u8_reader(struct bfin_sport_spi_master_data *drv_data)
184
+
{
185
+
u16 tx_val = drv_data->cur_chip->idle_tx_val;
186
+
187
+
while (drv_data->rx < drv_data->rx_end) {
188
+
bfin_write(&drv_data->regs->tx16, tx_val);
189
+
bfin_sport_spi_stat_poll_complete(drv_data);
190
+
*drv_data->rx8++ = bfin_read(&drv_data->regs->rx16);
191
+
}
192
+
}
193
+
194
+
static void
195
+
bfin_sport_spi_u8_duplex(struct bfin_sport_spi_master_data *drv_data)
196
+
{
197
+
while (drv_data->rx < drv_data->rx_end) {
198
+
bfin_write(&drv_data->regs->tx16, *drv_data->tx8++);
199
+
bfin_sport_spi_stat_poll_complete(drv_data);
200
+
*drv_data->rx8++ = bfin_read(&drv_data->regs->rx16);
201
+
}
202
+
}
203
+
204
+
static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u8 = {
205
+
.write = bfin_sport_spi_u8_writer,
206
+
.read = bfin_sport_spi_u8_reader,
207
+
.duplex = bfin_sport_spi_u8_duplex,
208
+
};
209
+
210
+
static void
211
+
bfin_sport_spi_u16_writer(struct bfin_sport_spi_master_data *drv_data)
212
+
{
213
+
u16 dummy;
214
+
215
+
while (drv_data->tx < drv_data->tx_end) {
216
+
bfin_write(&drv_data->regs->tx16, *drv_data->tx16++);
217
+
bfin_sport_spi_stat_poll_complete(drv_data);
218
+
dummy = bfin_read(&drv_data->regs->rx16);
219
+
}
220
+
}
221
+
222
+
static void
223
+
bfin_sport_spi_u16_reader(struct bfin_sport_spi_master_data *drv_data)
224
+
{
225
+
u16 tx_val = drv_data->cur_chip->idle_tx_val;
226
+
227
+
while (drv_data->rx < drv_data->rx_end) {
228
+
bfin_write(&drv_data->regs->tx16, tx_val);
229
+
bfin_sport_spi_stat_poll_complete(drv_data);
230
+
*drv_data->rx16++ = bfin_read(&drv_data->regs->rx16);
231
+
}
232
+
}
233
+
234
+
static void
235
+
bfin_sport_spi_u16_duplex(struct bfin_sport_spi_master_data *drv_data)
236
+
{
237
+
while (drv_data->rx < drv_data->rx_end) {
238
+
bfin_write(&drv_data->regs->tx16, *drv_data->tx16++);
239
+
bfin_sport_spi_stat_poll_complete(drv_data);
240
+
*drv_data->rx16++ = bfin_read(&drv_data->regs->rx16);
241
+
}
242
+
}
243
+
244
+
static struct bfin_sport_transfer_ops bfin_sport_transfer_ops_u16 = {
245
+
.write = bfin_sport_spi_u16_writer,
246
+
.read = bfin_sport_spi_u16_reader,
247
+
.duplex = bfin_sport_spi_u16_duplex,
248
+
};
249
+
250
+
/* stop controller and re-config current chip */
251
+
static void
252
+
bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data)
253
+
{
254
+
struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
255
+
unsigned int bits = (drv_data->ops == &bfin_sport_transfer_ops_u8 ? 7 : 15);
256
+
257
+
bfin_sport_spi_disable(drv_data);
258
+
dev_dbg(drv_data->dev, "restoring spi ctl state\n");
259
+
260
+
bfin_write(&drv_data->regs->tcr1, chip->ctl_reg);
261
+
bfin_write(&drv_data->regs->tcr2, bits);
262
+
bfin_write(&drv_data->regs->tclkdiv, chip->baud);
263
+
bfin_write(&drv_data->regs->tfsdiv, bits);
264
+
SSYNC();
265
+
266
+
bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS));
267
+
bfin_write(&drv_data->regs->rcr2, bits);
268
+
SSYNC();
269
+
270
+
bfin_sport_spi_cs_active(chip);
271
+
}
272
+
273
+
/* test if there is more transfer to be done */
274
+
static enum bfin_sport_spi_state
275
+
bfin_sport_spi_next_transfer(struct bfin_sport_spi_master_data *drv_data)
276
+
{
277
+
struct spi_message *msg = drv_data->cur_msg;
278
+
struct spi_transfer *trans = drv_data->cur_transfer;
279
+
280
+
/* Move to next transfer */
281
+
if (trans->transfer_list.next != &msg->transfers) {
282
+
drv_data->cur_transfer =
283
+
list_entry(trans->transfer_list.next,
284
+
struct spi_transfer, transfer_list);
285
+
return RUNNING_STATE;
286
+
}
287
+
288
+
return DONE_STATE;
289
+
}
290
+
291
+
/*
292
+
* caller already set message->status;
293
+
* dma and pio irqs are blocked give finished message back
294
+
*/
295
+
static void
296
+
bfin_sport_spi_giveback(struct bfin_sport_spi_master_data *drv_data)
297
+
{
298
+
struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
299
+
unsigned long flags;
300
+
struct spi_message *msg;
301
+
302
+
spin_lock_irqsave(&drv_data->lock, flags);
303
+
msg = drv_data->cur_msg;
304
+
drv_data->state = START_STATE;
305
+
drv_data->cur_msg = NULL;
306
+
drv_data->cur_transfer = NULL;
307
+
drv_data->cur_chip = NULL;
308
+
queue_work(drv_data->workqueue, &drv_data->pump_messages);
309
+
spin_unlock_irqrestore(&drv_data->lock, flags);
310
+
311
+
if (!drv_data->cs_change)
312
+
bfin_sport_spi_cs_deactive(chip);
313
+
314
+
if (msg->complete)
315
+
msg->complete(msg->context);
316
+
}
317
+
318
+
static irqreturn_t
319
+
sport_err_handler(int irq, void *dev_id)
320
+
{
321
+
struct bfin_sport_spi_master_data *drv_data = dev_id;
322
+
u16 status;
323
+
324
+
dev_dbg(drv_data->dev, "%s enter\n", __func__);
325
+
status = bfin_read(&drv_data->regs->stat) & (TOVF | TUVF | ROVF | RUVF);
326
+
327
+
if (status) {
328
+
bfin_write(&drv_data->regs->stat, status);
329
+
SSYNC();
330
+
331
+
bfin_sport_spi_disable(drv_data);
332
+
dev_err(drv_data->dev, "status error:%s%s%s%s\n",
333
+
status & TOVF ? " TOVF" : "",
334
+
status & TUVF ? " TUVF" : "",
335
+
status & ROVF ? " ROVF" : "",
336
+
status & RUVF ? " RUVF" : "");
337
+
}
338
+
339
+
return IRQ_HANDLED;
340
+
}
341
+
342
+
static void
343
+
bfin_sport_spi_pump_transfers(unsigned long data)
344
+
{
345
+
struct bfin_sport_spi_master_data *drv_data = (void *)data;
346
+
struct spi_message *message = NULL;
347
+
struct spi_transfer *transfer = NULL;
348
+
struct spi_transfer *previous = NULL;
349
+
struct bfin_sport_spi_slave_data *chip = NULL;
350
+
unsigned int bits_per_word;
351
+
u32 tranf_success = 1;
352
+
u32 transfer_speed;
353
+
u8 full_duplex = 0;
354
+
355
+
/* Get current state information */
356
+
message = drv_data->cur_msg;
357
+
transfer = drv_data->cur_transfer;
358
+
chip = drv_data->cur_chip;
359
+
360
+
if (transfer->speed_hz)
361
+
transfer_speed = bfin_sport_hz_to_spi_baud(transfer->speed_hz);
362
+
else
363
+
transfer_speed = chip->baud;
364
+
bfin_write(&drv_data->regs->tclkdiv, transfer_speed);
365
+
SSYNC();
366
+
367
+
/*
368
+
* if msg is error or done, report it back using complete() callback
369
+
*/
370
+
371
+
/* Handle for abort */
372
+
if (drv_data->state == ERROR_STATE) {
373
+
dev_dbg(drv_data->dev, "transfer: we've hit an error\n");
374
+
message->status = -EIO;
375
+
bfin_sport_spi_giveback(drv_data);
376
+
return;
377
+
}
378
+
379
+
/* Handle end of message */
380
+
if (drv_data->state == DONE_STATE) {
381
+
dev_dbg(drv_data->dev, "transfer: all done!\n");
382
+
message->status = 0;
383
+
bfin_sport_spi_giveback(drv_data);
384
+
return;
385
+
}
386
+
387
+
/* Delay if requested at end of transfer */
388
+
if (drv_data->state == RUNNING_STATE) {
389
+
dev_dbg(drv_data->dev, "transfer: still running ...\n");
390
+
previous = list_entry(transfer->transfer_list.prev,
391
+
struct spi_transfer, transfer_list);
392
+
if (previous->delay_usecs)
393
+
udelay(previous->delay_usecs);
394
+
}
395
+
396
+
if (transfer->len == 0) {
397
+
/* Move to next transfer of this msg */
398
+
drv_data->state = bfin_sport_spi_next_transfer(drv_data);
399
+
/* Schedule next transfer tasklet */
400
+
tasklet_schedule(&drv_data->pump_transfers);
401
+
}
402
+
403
+
if (transfer->tx_buf != NULL) {
404
+
drv_data->tx = (void *)transfer->tx_buf;
405
+
drv_data->tx_end = drv_data->tx + transfer->len;
406
+
dev_dbg(drv_data->dev, "tx_buf is %p, tx_end is %p\n",
407
+
transfer->tx_buf, drv_data->tx_end);
408
+
} else
409
+
drv_data->tx = NULL;
410
+
411
+
if (transfer->rx_buf != NULL) {
412
+
full_duplex = transfer->tx_buf != NULL;
413
+
drv_data->rx = transfer->rx_buf;
414
+
drv_data->rx_end = drv_data->rx + transfer->len;
415
+
dev_dbg(drv_data->dev, "rx_buf is %p, rx_end is %p\n",
416
+
transfer->rx_buf, drv_data->rx_end);
417
+
} else
418
+
drv_data->rx = NULL;
419
+
420
+
drv_data->cs_change = transfer->cs_change;
421
+
422
+
/* Bits per word setup */
423
+
bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
424
+
if (bits_per_word == 8)
425
+
drv_data->ops = &bfin_sport_transfer_ops_u8;
426
+
else
427
+
drv_data->ops = &bfin_sport_transfer_ops_u16;
428
+
429
+
drv_data->state = RUNNING_STATE;
430
+
431
+
if (drv_data->cs_change)
432
+
bfin_sport_spi_cs_active(chip);
433
+
434
+
dev_dbg(drv_data->dev,
435
+
"now pumping a transfer: width is %d, len is %d\n",
436
+
bits_per_word, transfer->len);
437
+
438
+
/* PIO mode write then read */
439
+
dev_dbg(drv_data->dev, "doing IO transfer\n");
440
+
441
+
bfin_sport_spi_enable(drv_data);
442
+
if (full_duplex) {
443
+
/* full duplex mode */
444
+
BUG_ON((drv_data->tx_end - drv_data->tx) !=
445
+
(drv_data->rx_end - drv_data->rx));
446
+
drv_data->ops->duplex(drv_data);
447
+
448
+
if (drv_data->tx != drv_data->tx_end)
449
+
tranf_success = 0;
450
+
} else if (drv_data->tx != NULL) {
451
+
/* write only half duplex */
452
+
453
+
drv_data->ops->write(drv_data);
454
+
455
+
if (drv_data->tx != drv_data->tx_end)
456
+
tranf_success = 0;
457
+
} else if (drv_data->rx != NULL) {
458
+
/* read only half duplex */
459
+
460
+
drv_data->ops->read(drv_data);
461
+
if (drv_data->rx != drv_data->rx_end)
462
+
tranf_success = 0;
463
+
}
464
+
bfin_sport_spi_disable(drv_data);
465
+
466
+
if (!tranf_success) {
467
+
dev_dbg(drv_data->dev, "IO write error!\n");
468
+
drv_data->state = ERROR_STATE;
469
+
} else {
470
+
/* Update total byte transfered */
471
+
message->actual_length += transfer->len;
472
+
/* Move to next transfer of this msg */
473
+
drv_data->state = bfin_sport_spi_next_transfer(drv_data);
474
+
if (drv_data->cs_change)
475
+
bfin_sport_spi_cs_deactive(chip);
476
+
}
477
+
478
+
/* Schedule next transfer tasklet */
479
+
tasklet_schedule(&drv_data->pump_transfers);
480
+
}
481
+
482
+
/* pop a msg from queue and kick off real transfer */
483
+
static void
484
+
bfin_sport_spi_pump_messages(struct work_struct *work)
485
+
{
486
+
struct bfin_sport_spi_master_data *drv_data;
487
+
unsigned long flags;
488
+
struct spi_message *next_msg;
489
+
490
+
drv_data = container_of(work, struct bfin_sport_spi_master_data, pump_messages);
491
+
492
+
/* Lock queue and check for queue work */
493
+
spin_lock_irqsave(&drv_data->lock, flags);
494
+
if (list_empty(&drv_data->queue) || !drv_data->run) {
495
+
/* pumper kicked off but no work to do */
496
+
drv_data->busy = 0;
497
+
spin_unlock_irqrestore(&drv_data->lock, flags);
498
+
return;
499
+
}
500
+
501
+
/* Make sure we are not already running a message */
502
+
if (drv_data->cur_msg) {
503
+
spin_unlock_irqrestore(&drv_data->lock, flags);
504
+
return;
505
+
}
506
+
507
+
/* Extract head of queue */
508
+
next_msg = list_entry(drv_data->queue.next,
509
+
struct spi_message, queue);
510
+
511
+
drv_data->cur_msg = next_msg;
512
+
513
+
/* Setup the SSP using the per chip configuration */
514
+
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
515
+
516
+
list_del_init(&drv_data->cur_msg->queue);
517
+
518
+
/* Initialize message state */
519
+
drv_data->cur_msg->state = START_STATE;
520
+
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
521
+
struct spi_transfer, transfer_list);
522
+
bfin_sport_spi_restore_state(drv_data);
523
+
dev_dbg(drv_data->dev, "got a message to pump, "
524
+
"state is set to: baud %d, cs_gpio %i, ctl 0x%x\n",
525
+
drv_data->cur_chip->baud, drv_data->cur_chip->cs_gpio,
526
+
drv_data->cur_chip->ctl_reg);
527
+
528
+
dev_dbg(drv_data->dev,
529
+
"the first transfer len is %d\n",
530
+
drv_data->cur_transfer->len);
531
+
532
+
/* Mark as busy and launch transfers */
533
+
tasklet_schedule(&drv_data->pump_transfers);
534
+
535
+
drv_data->busy = 1;
536
+
spin_unlock_irqrestore(&drv_data->lock, flags);
537
+
}
538
+
539
+
/*
540
+
* got a msg to transfer, queue it in drv_data->queue.
541
+
* And kick off message pumper
542
+
*/
543
+
static int
544
+
bfin_sport_spi_transfer(struct spi_device *spi, struct spi_message *msg)
545
+
{
546
+
struct bfin_sport_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
547
+
unsigned long flags;
548
+
549
+
spin_lock_irqsave(&drv_data->lock, flags);
550
+
551
+
if (!drv_data->run) {
552
+
spin_unlock_irqrestore(&drv_data->lock, flags);
553
+
return -ESHUTDOWN;
554
+
}
555
+
556
+
msg->actual_length = 0;
557
+
msg->status = -EINPROGRESS;
558
+
msg->state = START_STATE;
559
+
560
+
dev_dbg(&spi->dev, "adding an msg in transfer()\n");
561
+
list_add_tail(&msg->queue, &drv_data->queue);
562
+
563
+
if (drv_data->run && !drv_data->busy)
564
+
queue_work(drv_data->workqueue, &drv_data->pump_messages);
565
+
566
+
spin_unlock_irqrestore(&drv_data->lock, flags);
567
+
568
+
return 0;
569
+
}
570
+
571
+
/* Called every time common spi devices change state */
572
+
static int
573
+
bfin_sport_spi_setup(struct spi_device *spi)
574
+
{
575
+
struct bfin_sport_spi_slave_data *chip, *first = NULL;
576
+
int ret;
577
+
578
+
/* Only alloc (or use chip_info) on first setup */
579
+
chip = spi_get_ctldata(spi);
580
+
if (chip == NULL) {
581
+
struct bfin5xx_spi_chip *chip_info;
582
+
583
+
chip = first = kzalloc(sizeof(*chip), GFP_KERNEL);
584
+
if (!chip)
585
+
return -ENOMEM;
586
+
587
+
/* platform chip_info isn't required */
588
+
chip_info = spi->controller_data;
589
+
if (chip_info) {
590
+
/*
591
+
* DITFS and TDTYPE are only thing we don't set, but
592
+
* they probably shouldn't be changed by people.
593
+
*/
594
+
if (chip_info->ctl_reg || chip_info->enable_dma) {
595
+
ret = -EINVAL;
596
+
dev_err(&spi->dev, "don't set ctl_reg/enable_dma fields");
597
+
goto error;
598
+
}
599
+
chip->cs_chg_udelay = chip_info->cs_chg_udelay;
600
+
chip->idle_tx_val = chip_info->idle_tx_val;
601
+
spi->bits_per_word = chip_info->bits_per_word;
602
+
}
603
+
}
604
+
605
+
if (spi->bits_per_word != 8 && spi->bits_per_word != 16) {
606
+
ret = -EINVAL;
607
+
goto error;
608
+
}
609
+
610
+
/* translate common spi framework into our register
611
+
* following configure contents are same for tx and rx.
612
+
*/
613
+
614
+
if (spi->mode & SPI_CPHA)
615
+
chip->ctl_reg &= ~TCKFE;
616
+
else
617
+
chip->ctl_reg |= TCKFE;
618
+
619
+
if (spi->mode & SPI_LSB_FIRST)
620
+
chip->ctl_reg |= TLSBIT;
621
+
else
622
+
chip->ctl_reg &= ~TLSBIT;
623
+
624
+
/* Sport in master mode */
625
+
chip->ctl_reg |= ITCLK | ITFS | TFSR | LATFS | LTFS;
626
+
627
+
chip->baud = bfin_sport_hz_to_spi_baud(spi->max_speed_hz);
628
+
629
+
chip->cs_gpio = spi->chip_select;
630
+
ret = gpio_request(chip->cs_gpio, spi->modalias);
631
+
if (ret)
632
+
goto error;
633
+
634
+
dev_dbg(&spi->dev, "setup spi chip %s, width is %d\n",
635
+
spi->modalias, spi->bits_per_word);
636
+
dev_dbg(&spi->dev, "ctl_reg is 0x%x, GPIO is %i\n",
637
+
chip->ctl_reg, spi->chip_select);
638
+
639
+
spi_set_ctldata(spi, chip);
640
+
641
+
bfin_sport_spi_cs_deactive(chip);
642
+
643
+
return ret;
644
+
645
+
error:
646
+
kfree(first);
647
+
return ret;
648
+
}
649
+
650
+
/*
651
+
* callback for spi framework.
652
+
* clean driver specific data
653
+
*/
654
+
static void
655
+
bfin_sport_spi_cleanup(struct spi_device *spi)
656
+
{
657
+
struct bfin_sport_spi_slave_data *chip = spi_get_ctldata(spi);
658
+
659
+
if (!chip)
660
+
return;
661
+
662
+
gpio_free(chip->cs_gpio);
663
+
664
+
kfree(chip);
665
+
}
666
+
667
+
static int
668
+
bfin_sport_spi_init_queue(struct bfin_sport_spi_master_data *drv_data)
669
+
{
670
+
INIT_LIST_HEAD(&drv_data->queue);
671
+
spin_lock_init(&drv_data->lock);
672
+
673
+
drv_data->run = false;
674
+
drv_data->busy = 0;
675
+
676
+
/* init transfer tasklet */
677
+
tasklet_init(&drv_data->pump_transfers,
678
+
bfin_sport_spi_pump_transfers, (unsigned long)drv_data);
679
+
680
+
/* init messages workqueue */
681
+
INIT_WORK(&drv_data->pump_messages, bfin_sport_spi_pump_messages);
682
+
drv_data->workqueue =
683
+
create_singlethread_workqueue(dev_name(drv_data->master->dev.parent));
684
+
if (drv_data->workqueue == NULL)
685
+
return -EBUSY;
686
+
687
+
return 0;
688
+
}
689
+
690
+
static int
691
+
bfin_sport_spi_start_queue(struct bfin_sport_spi_master_data *drv_data)
692
+
{
693
+
unsigned long flags;
694
+
695
+
spin_lock_irqsave(&drv_data->lock, flags);
696
+
697
+
if (drv_data->run || drv_data->busy) {
698
+
spin_unlock_irqrestore(&drv_data->lock, flags);
699
+
return -EBUSY;
700
+
}
701
+
702
+
drv_data->run = true;
703
+
drv_data->cur_msg = NULL;
704
+
drv_data->cur_transfer = NULL;
705
+
drv_data->cur_chip = NULL;
706
+
spin_unlock_irqrestore(&drv_data->lock, flags);
707
+
708
+
queue_work(drv_data->workqueue, &drv_data->pump_messages);
709
+
710
+
return 0;
711
+
}
712
+
713
+
static inline int
714
+
bfin_sport_spi_stop_queue(struct bfin_sport_spi_master_data *drv_data)
715
+
{
716
+
unsigned long flags;
717
+
unsigned limit = 500;
718
+
int status = 0;
719
+
720
+
spin_lock_irqsave(&drv_data->lock, flags);
721
+
722
+
/*
723
+
* This is a bit lame, but is optimized for the common execution path.
724
+
* A wait_queue on the drv_data->busy could be used, but then the common
725
+
* execution path (pump_messages) would be required to call wake_up or
726
+
* friends on every SPI message. Do this instead
727
+
*/
728
+
drv_data->run = false;
729
+
while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
730
+
spin_unlock_irqrestore(&drv_data->lock, flags);
731
+
msleep(10);
732
+
spin_lock_irqsave(&drv_data->lock, flags);
733
+
}
734
+
735
+
if (!list_empty(&drv_data->queue) || drv_data->busy)
736
+
status = -EBUSY;
737
+
738
+
spin_unlock_irqrestore(&drv_data->lock, flags);
739
+
740
+
return status;
741
+
}
742
+
743
+
static inline int
744
+
bfin_sport_spi_destroy_queue(struct bfin_sport_spi_master_data *drv_data)
745
+
{
746
+
int status;
747
+
748
+
status = bfin_sport_spi_stop_queue(drv_data);
749
+
if (status)
750
+
return status;
751
+
752
+
destroy_workqueue(drv_data->workqueue);
753
+
754
+
return 0;
755
+
}
756
+
757
+
static int __devinit
758
+
bfin_sport_spi_probe(struct platform_device *pdev)
759
+
{
760
+
struct device *dev = &pdev->dev;
761
+
struct bfin5xx_spi_master *platform_info;
762
+
struct spi_master *master;
763
+
struct resource *res, *ires;
764
+
struct bfin_sport_spi_master_data *drv_data;
765
+
int status;
766
+
767
+
platform_info = dev->platform_data;
768
+
769
+
/* Allocate master with space for drv_data */
770
+
master = spi_alloc_master(dev, sizeof(*master) + 16);
771
+
if (!master) {
772
+
dev_err(dev, "cannot alloc spi_master\n");
773
+
return -ENOMEM;
774
+
}
775
+
776
+
drv_data = spi_master_get_devdata(master);
777
+
drv_data->master = master;
778
+
drv_data->dev = dev;
779
+
drv_data->pin_req = platform_info->pin_req;
780
+
781
+
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
782
+
master->bus_num = pdev->id;
783
+
master->num_chipselect = platform_info->num_chipselect;
784
+
master->cleanup = bfin_sport_spi_cleanup;
785
+
master->setup = bfin_sport_spi_setup;
786
+
master->transfer = bfin_sport_spi_transfer;
787
+
788
+
/* Find and map our resources */
789
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
790
+
if (res == NULL) {
791
+
dev_err(dev, "cannot get IORESOURCE_MEM\n");
792
+
status = -ENOENT;
793
+
goto out_error_get_res;
794
+
}
795
+
796
+
drv_data->regs = ioremap(res->start, resource_size(res));
797
+
if (drv_data->regs == NULL) {
798
+
dev_err(dev, "cannot map registers\n");
799
+
status = -ENXIO;
800
+
goto out_error_ioremap;
801
+
}
802
+
803
+
ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
804
+
if (!ires) {
805
+
dev_err(dev, "cannot get IORESOURCE_IRQ\n");
806
+
status = -ENODEV;
807
+
goto out_error_get_ires;
808
+
}
809
+
drv_data->err_irq = ires->start;
810
+
811
+
/* Initial and start queue */
812
+
status = bfin_sport_spi_init_queue(drv_data);
813
+
if (status) {
814
+
dev_err(dev, "problem initializing queue\n");
815
+
goto out_error_queue_alloc;
816
+
}
817
+
818
+
status = bfin_sport_spi_start_queue(drv_data);
819
+
if (status) {
820
+
dev_err(dev, "problem starting queue\n");
821
+
goto out_error_queue_alloc;
822
+
}
823
+
824
+
status = request_irq(drv_data->err_irq, sport_err_handler,
825
+
0, "sport_spi_err", drv_data);
826
+
if (status) {
827
+
dev_err(dev, "unable to request sport err irq\n");
828
+
goto out_error_irq;
829
+
}
830
+
831
+
status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
832
+
if (status) {
833
+
dev_err(dev, "requesting peripherals failed\n");
834
+
goto out_error_peripheral;
835
+
}
836
+
837
+
/* Register with the SPI framework */
838
+
platform_set_drvdata(pdev, drv_data);
839
+
status = spi_register_master(master);
840
+
if (status) {
841
+
dev_err(dev, "problem registering spi master\n");
842
+
goto out_error_master;
843
+
}
844
+
845
+
dev_info(dev, "%s, regs_base@%p\n", DRV_DESC, drv_data->regs);
846
+
return 0;
847
+
848
+
out_error_master:
849
+
peripheral_free_list(drv_data->pin_req);
850
+
out_error_peripheral:
851
+
free_irq(drv_data->err_irq, drv_data);
852
+
out_error_irq:
853
+
out_error_queue_alloc:
854
+
bfin_sport_spi_destroy_queue(drv_data);
855
+
out_error_get_ires:
856
+
iounmap(drv_data->regs);
857
+
out_error_ioremap:
858
+
out_error_get_res:
859
+
spi_master_put(master);
860
+
861
+
return status;
862
+
}
863
+
864
+
/* stop hardware and remove the driver */
865
+
static int __devexit
866
+
bfin_sport_spi_remove(struct platform_device *pdev)
867
+
{
868
+
struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev);
869
+
int status = 0;
870
+
871
+
if (!drv_data)
872
+
return 0;
873
+
874
+
/* Remove the queue */
875
+
status = bfin_sport_spi_destroy_queue(drv_data);
876
+
if (status)
877
+
return status;
878
+
879
+
/* Disable the SSP at the peripheral and SOC level */
880
+
bfin_sport_spi_disable(drv_data);
881
+
882
+
/* Disconnect from the SPI framework */
883
+
spi_unregister_master(drv_data->master);
884
+
885
+
peripheral_free_list(drv_data->pin_req);
886
+
887
+
/* Prevent double remove */
888
+
platform_set_drvdata(pdev, NULL);
889
+
890
+
return 0;
891
+
}
892
+
893
+
#ifdef CONFIG_PM
894
+
static int
895
+
bfin_sport_spi_suspend(struct platform_device *pdev, pm_message_t state)
896
+
{
897
+
struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev);
898
+
int status;
899
+
900
+
status = bfin_sport_spi_stop_queue(drv_data);
901
+
if (status)
902
+
return status;
903
+
904
+
/* stop hardware */
905
+
bfin_sport_spi_disable(drv_data);
906
+
907
+
return status;
908
+
}
909
+
910
+
static int
911
+
bfin_sport_spi_resume(struct platform_device *pdev)
912
+
{
913
+
struct bfin_sport_spi_master_data *drv_data = platform_get_drvdata(pdev);
914
+
int status;
915
+
916
+
/* Enable the SPI interface */
917
+
bfin_sport_spi_enable(drv_data);
918
+
919
+
/* Start the queue running */
920
+
status = bfin_sport_spi_start_queue(drv_data);
921
+
if (status)
922
+
dev_err(drv_data->dev, "problem resuming queue\n");
923
+
924
+
return status;
925
+
}
926
+
#else
927
+
# define bfin_sport_spi_suspend NULL
928
+
# define bfin_sport_spi_resume NULL
929
+
#endif
930
+
931
+
static struct platform_driver bfin_sport_spi_driver = {
932
+
.driver = {
933
+
.name = DRV_NAME,
934
+
.owner = THIS_MODULE,
935
+
},
936
+
.probe = bfin_sport_spi_probe,
937
+
.remove = __devexit_p(bfin_sport_spi_remove),
938
+
.suspend = bfin_sport_spi_suspend,
939
+
.resume = bfin_sport_spi_resume,
940
+
};
941
+
942
+
static int __init bfin_sport_spi_init(void)
943
+
{
944
+
return platform_driver_register(&bfin_sport_spi_driver);
945
+
}
946
+
module_init(bfin_sport_spi_init);
947
+
948
+
static void __exit bfin_sport_spi_exit(void)
949
+
{
950
+
platform_driver_unregister(&bfin_sport_spi_driver);
951
+
}
952
+
module_exit(bfin_sport_spi_exit);
+2
-1
drivers/spi/tle62x0.c
+2
-1
drivers/spi/tle62x0.c
···
283
283
return 0;
284
284
285
285
err_gpios:
286
-
for (; ptr > 0; ptr--)
286
+
while (--ptr >= 0)
287
287
device_remove_file(&spi->dev, gpio_attrs[ptr]);
288
288
289
289
device_remove_file(&spi->dev, &dev_attr_status_show);
···
301
301
for (ptr = 0; ptr < st->nr_gpio; ptr++)
302
302
device_remove_file(&spi->dev, gpio_attrs[ptr]);
303
303
304
+
device_remove_file(&spi->dev, &dev_attr_status_show);
304
305
kfree(st);
305
306
return 0;
306
307
}