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linux
Merge branch 'net-stmmac-further-cleanups'
Russell King says:
====================
net: stmmac: further cleanups
Yet another bunch of patches cleaning up the stmmac driver.
We start off by cleaning up the formatting for stmmac_mac_finish(). Then
remove a plat_dat->port_node which is redundant, followed by several
descriptor methods that aren't called.
We then remove useless dwmac4 interrupt definitions, and realise that
v4.10 definitions are the same as v4.0, so get rid of those as well.
We also remove the write-only priv->hw->xlgmac member.
Next, we change priv->extend_desc and priv->chain_mode to be a boolean
and document what each of these are doing. Also do the same for
dma_cfg->fixed_burst and dma_cfg->mixed_burst.
Then, move the initialisation of dma_cfg->atds into stmmac_hw_init()
as this is where we have all the dependencies for this known, and
simplify its initialisation. Also comment what this is doing.
Finally, move the check that priv->plat->dma_cfg is present and the
programmable burst limit is set into the driver probe rather than
checking it each time we are just about to reset the dwmac core.
It is unnecessary to keep checking this. This makes a platform glue
driver fail early when it hasn't setup everything that's required
rather than when attempting to bring the netdev up for the first time.
====================
Link: https://patch.msgid.link/aaFpZvuIzOLaNM0m@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+37
-170
-1
drivers/net/ethernet/stmicro/stmmac/common.h
-1
drivers/net/ethernet/stmicro/stmmac/common.h
+1
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+1
-3
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
636
636
637
637
plat->dma_cfg->pbl = 32;
638
638
plat->dma_cfg->pblx8 = true;
639
-
plat->dma_cfg->fixed_burst = 0;
640
-
plat->dma_cfg->mixed_burst = 0;
641
639
plat->dma_cfg->aal = 0;
642
640
plat->dma_cfg->dche = true;
643
641
···
1104
1106
1105
1107
plat->dma_cfg->pbl = 16;
1106
1108
plat->dma_cfg->pblx8 = true;
1107
-
plat->dma_cfg->fixed_burst = 1;
1109
+
plat->dma_cfg->fixed_burst = true;
1108
1110
/* AXI (TODO) */
1109
1111
1110
1112
return 0;
-19
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
-19
drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c
···
171
171
return ret;
172
172
}
173
173
174
-
static int dwmac4_rd_get_tx_len(struct dma_desc *p)
175
-
{
176
-
return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
177
-
}
178
-
179
-
static int dwmac4_get_tx_owner(struct dma_desc *p)
180
-
{
181
-
return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
182
-
}
183
-
184
174
static void dwmac4_set_tx_owner(struct dma_desc *p)
185
175
{
186
176
p->des3 |= cpu_to_le32(TDES3_OWN);
···
184
194
flags |= RDES3_INT_ON_COMPLETION_EN;
185
195
186
196
p->des3 |= cpu_to_le32(flags);
187
-
}
188
-
189
-
static int dwmac4_get_tx_ls(struct dma_desc *p)
190
-
{
191
-
return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
192
-
>> TDES3_LAST_DESCRIPTOR_SHIFT;
193
197
}
194
198
195
199
static u16 dwmac4_wrback_get_rx_vlan_tci(struct dma_desc *p)
···
535
551
const struct stmmac_desc_ops dwmac4_desc_ops = {
536
552
.tx_status = dwmac4_wrback_get_tx_status,
537
553
.rx_status = dwmac4_wrback_get_rx_status,
538
-
.get_tx_len = dwmac4_rd_get_tx_len,
539
-
.get_tx_owner = dwmac4_get_tx_owner,
540
554
.set_tx_owner = dwmac4_set_tx_owner,
541
555
.set_rx_owner = dwmac4_set_rx_owner,
542
-
.get_tx_ls = dwmac4_get_tx_ls,
543
556
.get_rx_vlan_tci = dwmac4_wrback_get_rx_vlan_tci,
544
557
.get_rx_vlan_valid = dwmac4_wrback_get_rx_vlan_valid,
545
558
.get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
+1
-1
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
···
582
582
.dump_regs = dwmac4_dump_dma_regs,
583
583
.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
584
584
.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
585
-
.enable_dma_irq = dwmac410_enable_dma_irq,
585
+
.enable_dma_irq = dwmac4_enable_dma_irq,
586
586
.disable_dma_irq = dwmac4_disable_dma_irq,
587
587
.start_tx = dwmac4_dma_start_tx,
588
588
.stop_tx = dwmac4_dma_stop_tx,
-8
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
-8
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
···
111
111
/* DMA default interrupt mask for 4.00 */
112
112
#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
113
113
DMA_CHAN_INTR_ABNORMAL)
114
-
#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
115
-
#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
116
114
117
115
#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
118
116
DMA_CHAN_INTR_ENA_RIE | \
···
121
123
/* DMA default interrupt mask for 4.10a */
122
124
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
123
125
DMA_CHAN_INTR_ABNORMAL_4_10)
124
-
#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
125
-
#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
126
126
127
127
#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
128
128
#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
···
170
174
int dwmac4_dma_reset(void __iomem *ioaddr);
171
175
void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
172
176
u32 chan, bool rx, bool tx);
173
-
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
174
-
u32 chan, bool rx, bool tx);
175
177
void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
176
178
u32 chan, bool rx, bool tx);
177
-
void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
178
-
u32 chan, bool rx, bool tx);
179
179
void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
180
180
u32 chan);
181
181
void dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr,
+4
-32
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
+4
-32
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
···
116
116
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
117
117
118
118
if (rx)
119
-
value |= DMA_CHAN_INTR_DEFAULT_RX;
119
+
value |= DMA_CHAN_INTR_ENA_RIE;
120
120
if (tx)
121
-
value |= DMA_CHAN_INTR_DEFAULT_TX;
122
-
123
-
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
124
-
}
125
-
126
-
void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
127
-
u32 chan, bool rx, bool tx)
128
-
{
129
-
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
130
-
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
131
-
132
-
if (rx)
133
-
value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
134
-
if (tx)
135
-
value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;
121
+
value |= DMA_CHAN_INTR_ENA_TIE;
136
122
137
123
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
138
124
}
···
130
144
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
131
145
132
146
if (rx)
133
-
value &= ~DMA_CHAN_INTR_DEFAULT_RX;
147
+
value &= ~DMA_CHAN_INTR_ENA_RIE;
134
148
if (tx)
135
-
value &= ~DMA_CHAN_INTR_DEFAULT_TX;
136
-
137
-
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
138
-
}
139
-
140
-
void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
141
-
u32 chan, bool rx, bool tx)
142
-
{
143
-
const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
144
-
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
145
-
146
-
if (rx)
147
-
value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
148
-
if (tx)
149
-
value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
149
+
value &= ~DMA_CHAN_INTR_ENA_TIE;
150
150
151
151
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
152
152
}
-18
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
-18
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
···
40
40
return good_frame;
41
41
}
42
42
43
-
static int dwxgmac2_get_tx_len(struct dma_desc *p)
44
-
{
45
-
return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
46
-
}
47
-
48
-
static int dwxgmac2_get_tx_owner(struct dma_desc *p)
49
-
{
50
-
return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
51
-
}
52
-
53
43
static void dwxgmac2_set_tx_owner(struct dma_desc *p)
54
44
{
55
45
p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
···
53
63
flags |= XGMAC_RDES3_IOC;
54
64
55
65
p->des3 |= cpu_to_le32(flags);
56
-
}
57
-
58
-
static int dwxgmac2_get_tx_ls(struct dma_desc *p)
59
-
{
60
-
return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
61
66
}
62
67
63
68
static u16 dwxgmac2_wrback_get_rx_vlan_tci(struct dma_desc *p)
···
340
355
const struct stmmac_desc_ops dwxgmac210_desc_ops = {
341
356
.tx_status = dwxgmac2_get_tx_status,
342
357
.rx_status = dwxgmac2_get_rx_status,
343
-
.get_tx_len = dwxgmac2_get_tx_len,
344
-
.get_tx_owner = dwxgmac2_get_tx_owner,
345
358
.set_tx_owner = dwxgmac2_set_tx_owner,
346
359
.set_rx_owner = dwxgmac2_set_rx_owner,
347
-
.get_tx_ls = dwxgmac2_get_tx_ls,
348
360
.get_rx_vlan_tci = dwxgmac2_wrback_get_rx_vlan_tci,
349
361
.get_rx_vlan_valid = dwxgmac2_wrback_get_rx_vlan_valid,
350
362
.get_rx_frame_len = dwxgmac2_get_rx_frame_len,
-18
drivers/net/ethernet/stmicro/stmmac/enh_desc.c
-18
drivers/net/ethernet/stmicro/stmmac/enh_desc.c
···
76
76
return ret;
77
77
}
78
78
79
-
static int enh_desc_get_tx_len(struct dma_desc *p)
80
-
{
81
-
return (le32_to_cpu(p->des1) & ETDES1_BUFFER1_SIZE_MASK);
82
-
}
83
-
84
79
static int enh_desc_coe_rdes0(int ipc_err, int type, int payload_err)
85
80
{
86
81
int ret = good_frame;
···
272
277
enh_desc_end_tx_desc_on_ring(p, end);
273
278
}
274
279
275
-
static int enh_desc_get_tx_owner(struct dma_desc *p)
276
-
{
277
-
return (le32_to_cpu(p->des0) & ETDES0_OWN) >> 31;
278
-
}
279
-
280
280
static void enh_desc_set_tx_owner(struct dma_desc *p)
281
281
{
282
282
p->des0 |= cpu_to_le32(ETDES0_OWN);
···
280
290
static void enh_desc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
281
291
{
282
292
p->des0 |= cpu_to_le32(RDES0_OWN);
283
-
}
284
-
285
-
static int enh_desc_get_tx_ls(struct dma_desc *p)
286
-
{
287
-
return (le32_to_cpu(p->des0) & ETDES0_LAST_SEGMENT) >> 29;
288
293
}
289
294
290
295
static void enh_desc_release_tx_desc(struct dma_desc *p, int mode)
···
430
445
const struct stmmac_desc_ops enh_desc_ops = {
431
446
.tx_status = enh_desc_get_tx_status,
432
447
.rx_status = enh_desc_get_rx_status,
433
-
.get_tx_len = enh_desc_get_tx_len,
434
448
.init_rx_desc = enh_desc_init_rx_desc,
435
449
.init_tx_desc = enh_desc_init_tx_desc,
436
-
.get_tx_owner = enh_desc_get_tx_owner,
437
450
.release_tx_desc = enh_desc_release_tx_desc,
438
451
.prepare_tx_desc = enh_desc_prepare_tx_desc,
439
452
.set_tx_ic = enh_desc_set_tx_ic,
440
-
.get_tx_ls = enh_desc_get_tx_ls,
441
453
.set_tx_owner = enh_desc_set_tx_owner,
442
454
.set_rx_owner = enh_desc_set_rx_owner,
443
455
.get_rx_frame_len = enh_desc_get_rx_frame_len,
+1
-8
drivers/net/ethernet/stmicro/stmmac/hwif.c
+1
-8
drivers/net/ethernet/stmicro/stmmac/hwif.c
···
76
76
/* GMAC older than 3.50 has no extended descriptors */
77
77
if (priv->synopsys_id >= DWMAC_CORE_3_50) {
78
78
dev_info(priv->device, "Enabled extended descriptors\n");
79
-
priv->extend_desc = 1;
79
+
priv->extend_desc = true;
80
80
} else {
81
81
dev_warn(priv->device, "Extended descriptors not supported\n");
82
82
}
···
94
94
static int stmmac_dwmac4_quirks(struct stmmac_priv *priv)
95
95
{
96
96
stmmac_dwmac_mode_quirk(priv);
97
-
return 0;
98
-
}
99
-
100
-
static int stmmac_dwxlgmac_quirks(struct stmmac_priv *priv)
101
-
{
102
-
priv->hw->xlgmac = true;
103
97
return 0;
104
98
}
105
99
···
287
293
.mmc = &dwxgmac_mmc_ops,
288
294
.est = &dwmac510_est_ops,
289
295
.setup = dwxlgmac2_setup,
290
-
.quirks = stmmac_dwxlgmac_quirks,
291
296
},
292
297
};
293
298
-11
drivers/net/ethernet/stmicro/stmmac/hwif.h
-11
drivers/net/ethernet/stmicro/stmmac/hwif.h
···
51
51
unsigned int tcppayloadlen);
52
52
/* Set/get the owner of the descriptor */
53
53
void (*set_tx_owner)(struct dma_desc *p);
54
-
int (*get_tx_owner)(struct dma_desc *p);
55
54
/* Clean the tx descriptor as soon as the tx irq is received */
56
55
void (*release_tx_desc)(struct dma_desc *p, int mode);
57
56
/* Clear interrupt on tx frame completion. When this bit is
58
57
* set an interrupt happens as soon as the frame is transmitted */
59
58
void (*set_tx_ic)(struct dma_desc *p);
60
-
/* Last tx segment reports the transmit status */
61
-
int (*get_tx_ls)(struct dma_desc *p);
62
59
/* Get the tag of the descriptor */
63
60
u16 (*get_rx_vlan_tci)(struct dma_desc *p);
64
61
/* Get the valid status of descriptor */
···
63
66
/* Return the transmit status looking at the TDES1 */
64
67
int (*tx_status)(struct stmmac_extra_stats *x,
65
68
struct dma_desc *p, void __iomem *ioaddr);
66
-
/* Get the buffer size from the descriptor */
67
-
int (*get_tx_len)(struct dma_desc *p);
68
69
/* Handle extra events on specific interrupts hw dependent */
69
70
void (*set_rx_owner)(struct dma_desc *p, int disable_rx_ic);
70
71
/* Get the receive frame size */
···
111
116
stmmac_do_void_callback(__priv, desc, prepare_tso_tx_desc, __args)
112
117
#define stmmac_set_tx_owner(__priv, __args...) \
113
118
stmmac_do_void_callback(__priv, desc, set_tx_owner, __args)
114
-
#define stmmac_get_tx_owner(__priv, __args...) \
115
-
stmmac_do_callback(__priv, desc, get_tx_owner, __args)
116
119
#define stmmac_release_tx_desc(__priv, __args...) \
117
120
stmmac_do_void_callback(__priv, desc, release_tx_desc, __args)
118
121
#define stmmac_set_tx_ic(__priv, __args...) \
119
122
stmmac_do_void_callback(__priv, desc, set_tx_ic, __args)
120
-
#define stmmac_get_tx_ls(__priv, __args...) \
121
-
stmmac_do_callback(__priv, desc, get_tx_ls, __args)
122
123
#define stmmac_get_rx_vlan_tci(__priv, __args...) \
123
124
stmmac_do_callback(__priv, desc, get_rx_vlan_tci, __args)
124
125
#define stmmac_get_rx_vlan_valid(__priv, __args...) \
125
126
stmmac_do_callback(__priv, desc, get_rx_vlan_valid, __args)
126
127
#define stmmac_tx_status(__priv, __args...) \
127
128
stmmac_do_callback(__priv, desc, tx_status, __args)
128
-
#define stmmac_get_tx_len(__priv, __args...) \
129
-
stmmac_do_callback(__priv, desc, get_tx_len, __args)
130
129
#define stmmac_set_rx_owner(__priv, __args...) \
131
130
stmmac_do_void_callback(__priv, desc, set_rx_owner, __args)
132
131
#define stmmac_get_rx_frame_len(__priv, __args...) \
-18
drivers/net/ethernet/stmicro/stmmac/norm_desc.c
-18
drivers/net/ethernet/stmicro/stmmac/norm_desc.c
···
55
55
return ret;
56
56
}
57
57
58
-
static int ndesc_get_tx_len(struct dma_desc *p)
59
-
{
60
-
return (le32_to_cpu(p->des1) & RDES1_BUFFER1_SIZE_MASK);
61
-
}
62
-
63
58
/* This function verifies if each incoming frame has some errors
64
59
* and, if required, updates the multicast statistics.
65
60
* In case of success, it returns good_frame because the GMAC device
···
136
141
ndesc_end_tx_desc_on_ring(p, end);
137
142
}
138
143
139
-
static int ndesc_get_tx_owner(struct dma_desc *p)
140
-
{
141
-
return (le32_to_cpu(p->des0) & TDES0_OWN) >> 31;
142
-
}
143
-
144
144
static void ndesc_set_tx_owner(struct dma_desc *p)
145
145
{
146
146
p->des0 |= cpu_to_le32(TDES0_OWN);
···
144
154
static void ndesc_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
145
155
{
146
156
p->des0 |= cpu_to_le32(RDES0_OWN);
147
-
}
148
-
149
-
static int ndesc_get_tx_ls(struct dma_desc *p)
150
-
{
151
-
return (le32_to_cpu(p->des1) & TDES1_LAST_SEGMENT) >> 30;
152
157
}
153
158
154
159
static void ndesc_release_tx_desc(struct dma_desc *p, int mode)
···
276
291
const struct stmmac_desc_ops ndesc_ops = {
277
292
.tx_status = ndesc_get_tx_status,
278
293
.rx_status = ndesc_get_rx_status,
279
-
.get_tx_len = ndesc_get_tx_len,
280
294
.init_rx_desc = ndesc_init_rx_desc,
281
295
.init_tx_desc = ndesc_init_tx_desc,
282
-
.get_tx_owner = ndesc_get_tx_owner,
283
296
.release_tx_desc = ndesc_release_tx_desc,
284
297
.prepare_tx_desc = ndesc_prepare_tx_desc,
285
298
.set_tx_ic = ndesc_set_tx_ic,
286
-
.get_tx_ls = ndesc_get_tx_ls,
287
299
.set_tx_owner = ndesc_set_tx_owner,
288
300
.set_rx_owner = ndesc_set_rx_owner,
289
301
.get_rx_frame_len = ndesc_get_rx_frame_len,
+7
-2
drivers/net/ethernet/stmicro/stmmac/stmmac.h
+7
-2
drivers/net/ethernet/stmicro/stmmac/stmmac.h
···
302
302
bool eee_active;
303
303
bool eee_sw_timer_en;
304
304
bool legacy_serdes_is_powered;
305
+
/* descriptor format:
306
+
* when clear: struct dma_desc or for tx TBS struct dma_edesc
307
+
* when set, struct dma_extended_desc
308
+
*/
309
+
bool extend_desc;
310
+
/* chain_mode: requested descriptor mode */
311
+
bool chain_mode;
305
312
unsigned int mode;
306
-
unsigned int chain_mode;
307
-
int extend_desc;
308
313
struct kernel_hwtstamp_config tstamp_config;
309
314
struct ptp_clock *ptp_clock;
310
315
struct ptp_clock_info ptp_clock_ops;
+19
-20
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+19
-20
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
968
968
struct stmmac_priv *priv = netdev_priv(ndev);
969
969
970
970
if (priv->plat->mac_finish)
971
-
priv->plat->mac_finish(ndev, priv->plat->bsp_priv, mode, interface);
971
+
priv->plat->mac_finish(ndev, priv->plat->bsp_priv, mode,
972
+
interface);
972
973
973
974
return 0;
974
975
}
···
1252
1251
xpcs_get_an_mode(priv->hw->xpcs, mode) == DW_AN_C73)
1253
1252
return 0;
1254
1253
1255
-
fwnode = priv->plat->port_node;
1256
-
if (!fwnode)
1257
-
fwnode = dev_fwnode(priv->device);
1258
-
1254
+
fwnode = dev_fwnode(priv->device);
1259
1255
if (fwnode)
1260
1256
phy_fwnode = fwnode_get_phy_node(fwnode);
1261
1257
else
···
1310
1312
{
1311
1313
struct stmmac_mdio_bus_data *mdio_bus_data;
1312
1314
struct phylink_config *config;
1313
-
struct fwnode_handle *fwnode;
1314
1315
struct phylink_pcs *pcs;
1315
1316
struct phylink *phylink;
1316
1317
···
1396
1399
config->wol_mac_support |= WAKE_MAGIC;
1397
1400
}
1398
1401
1399
-
fwnode = priv->plat->port_node;
1400
-
if (!fwnode)
1401
-
fwnode = dev_fwnode(priv->device);
1402
-
1403
-
phylink = phylink_create(config, fwnode, priv->plat->phy_interface,
1402
+
phylink = phylink_create(config, dev_fwnode(priv->device),
1403
+
priv->plat->phy_interface,
1404
1404
&stmmac_phylink_mac_ops);
1405
1405
if (IS_ERR(phylink))
1406
1406
return PTR_ERR(phylink);
···
3243
3249
struct stmmac_tx_queue *tx_q;
3244
3250
u32 chan = 0;
3245
3251
int ret = 0;
3246
-
3247
-
if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
3248
-
netdev_err(priv->dev, "Invalid DMA configuration\n");
3249
-
return -EINVAL;
3250
-
}
3251
-
3252
-
if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
3253
-
priv->plat->dma_cfg->atds = 1;
3254
3252
3255
3253
ret = stmmac_prereset_configure(priv);
3256
3254
if (ret)
···
7331
7345
/* dwmac-sun8i only work in chain mode */
7332
7346
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
7333
7347
chain_mode = 1;
7334
-
priv->chain_mode = chain_mode;
7348
+
priv->chain_mode = !!chain_mode;
7335
7349
7336
7350
/* Initialize HW Interface */
7337
7351
ret = stmmac_hwif_init(priv);
···
7435
7449
if (ret)
7436
7450
return ret;
7437
7451
}
7452
+
7453
+
/* Set alternate descriptor size (which tells the hardware that
7454
+
* descriptors are 8 32-bit words) when using extended descriptors
7455
+
* with ring mode. Only applicable for pre-v4.0 cores. Platform glue
7456
+
* is not expected to change this.
7457
+
*/
7458
+
priv->plat->dma_cfg->atds = priv->extend_desc &&
7459
+
priv->mode == STMMAC_RING_MODE;
7438
7460
7439
7461
/* Rx Watchdog is available in the COREs newer than the 3.40.
7440
7462
* In some case, for example on bugged HW this feature
···
7722
7728
struct stmmac_priv *priv;
7723
7729
u32 rxq;
7724
7730
int i, ret = 0;
7731
+
7732
+
if (!plat_dat->dma_cfg || !plat_dat->dma_cfg->pbl) {
7733
+
dev_err(device, "invalid DMA configuration\n");
7734
+
return -EINVAL;
7735
+
}
7725
7736
7726
7737
ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
7727
7738
MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
+2
-5
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+2
-5
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
···
430
430
struct dw_xpcs *xpcs = NULL;
431
431
int addr, ret;
432
432
433
-
devnode = priv->plat->port_node;
433
+
devnode = dev_fwnode(priv->device);
434
434
435
435
if (priv->plat->pcs_init) {
436
436
ret = priv->plat->pcs_init(priv);
···
649
649
stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0);
650
650
651
651
/* If fixed-link is set, skip PHY scanning */
652
-
fwnode = priv->plat->port_node;
653
-
if (!fwnode)
654
-
fwnode = dev_fwnode(priv->device);
655
-
652
+
fwnode = dev_fwnode(priv->device);
656
653
if (fwnode) {
657
654
fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
658
655
if (fixed_node) {
-3
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
-3
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
···
446
446
* they are not converted to phylink. */
447
447
plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
448
448
449
-
/* PHYLINK automatically parses the phy-handle property */
450
-
plat->port_node = of_fwnode_handle(np);
451
-
452
449
/* Get max speed of operation from device tree */
453
450
of_property_read_u32(np, "max-speed", &plat->max_speed);
454
451
+2
-3
include/linux/stmmac.h
+2
-3
include/linux/stmmac.h
···
97
97
int txpbl;
98
98
int rxpbl;
99
99
bool pblx8;
100
-
int fixed_burst;
101
-
int mixed_burst;
100
+
bool fixed_burst;
101
+
bool mixed_burst;
102
102
bool aal;
103
103
bool eame;
104
104
bool multi_msi_en;
···
225
225
phy_interface_t phy_interface;
226
226
struct stmmac_mdio_bus_data *mdio_bus_data;
227
227
struct device_node *phy_node;
228
-
struct fwnode_handle *port_node;
229
228
struct device_node *mdio_node;
230
229
struct stmmac_dma_cfg *dma_cfg;
231
230
struct stmmac_safety_feature_cfg *safety_feat_cfg;