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clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP

Add the LHS_ACEL gate clock to the HSI0 clock controller. This clock is
critical for USB functionality and mark it as critical to keep it enabled.

Update CLK_NR_TOP to include the new clock.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250831-usb-v2-2-00b9c0559733@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

authored by

Denzeel Oliva and committed by
Krzysztof Kozlowski d0563d32 eb9bc162

+5 -1
+5 -1
drivers/clk/samsung/clk-exynos990.c
··· 18 18 19 19 /* NOTE: Must be equal to the last clock ID increased by one */ 20 20 #define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1) 21 - #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) 21 + #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1) 22 22 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) 23 23 24 24 /* ---- CMU_TOP ------------------------------------------------------------- */ ··· 1332 1332 "gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user", 1333 1333 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK, 1334 1334 21, CLK_IGNORE_UNUSED, 0), 1335 + GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK, 1336 + "gout_hsi0_lhs_acel_d_hsi0_clk", "mout_hsi0_bus_user", 1337 + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 1338 + 21, CLK_IS_CRITICAL, 0), 1335 1339 }; 1336 1340 1337 1341 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {