Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: DML2.1 Reintegration for Various Fixes
[Why and How]
DML2.1 reintegration for several fixes and updates to the DML
code.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Roman Li <roman.li@amd
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Austin Zheng
and committed by
Alex Deucher
d07722e1
20b5a8f9
+1011
-287
-3
drivers/gpu/drm/amd/display/dc/dml2/Makefile
-3
drivers/gpu/drm/amd/display/dc/dml2/Makefile
···
79
79
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags)
80
80
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)
81
81
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags)
82
-
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_ccflags) $(frame_warn_flag)
83
82
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)
84
83
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)
85
84
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)
···
100
101
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags)
101
102
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)
102
103
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags)
103
-
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_rcflags)
104
104
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)
105
105
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)
106
106
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)
···
120
122
DML21 += src/dml2_core/dml2_core_dcn4.o
121
123
DML21 += src/dml2_core/dml2_core_factory.o
122
124
DML21 += src/dml2_core/dml2_core_dcn4_calcs.o
123
-
DML21 += src/dml2_core/dml2_core_shared.o
124
125
DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o
125
126
DML21 += src/dml2_dpmm/dml2_dpmm_factory.o
126
127
DML21 += src/dml2_mcg/dml2_mcg_dcn4.o
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h
···
355
355
.fams2 = {
356
356
.max_allow_delay_us = 100 * 1000,
357
357
.scheduling_delay_us = 125,
358
-
.vertical_interrupt_ack_delay_us = 18,
358
+
.vertical_interrupt_ack_delay_us = 40,
359
359
.allow_programming_delay_us = 18,
360
360
.min_allow_width_us = 20,
361
361
.subvp_df_throttle_delay_us = 100,
+1
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
+1
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c
···
273
273
programming->fams2_required = display_cfg->stage3.fams2_required;
274
274
275
275
dml2_core_calcs_get_global_fams2_programming(&core->clean_me_up.mode_lib, display_cfg, &programming->fams2_global_config);
276
-
programming->fams2_global_config.features.bits.enable = display_cfg->stage3.fams2_required;
277
276
}
278
277
279
278
// Only loop over all the main streams (the implicit svp streams will be packed as part of the main stream)
+264
-218
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+264
-218
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
···
8
8
#include "dml2_debug.h"
9
9
#include "lib_float_math.h"
10
10
#include "dml_top_types.h"
11
-
#include "dml2_core_shared.h"
12
11
13
-
//#define DML_TVM_UPDATE_EN
14
12
#define DML2_MAX_FMT_420_BUFFER_WIDTH 4096
15
13
#define DML_MAX_NUM_OF_SLICES_PER_DSC 4
16
14
17
-
static void dml2_print_dml_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
15
+
const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)
16
+
{
17
+
switch (bw_type) {
18
+
case (dml2_core_internal_bw_sdp):
19
+
return("dml2_core_internal_bw_sdp");
20
+
case (dml2_core_internal_bw_dram):
21
+
return("dml2_core_internal_bw_dram");
22
+
case (dml2_core_internal_bw_max):
23
+
return("dml2_core_internal_bw_max");
24
+
default:
25
+
return("dml2_core_internal_bw_unknown");
26
+
}
27
+
}
28
+
29
+
const char *dml2_core_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type)
30
+
{
31
+
switch (dml2_core_internal_soc_state_type) {
32
+
case (dml2_core_internal_soc_state_sys_idle):
33
+
return("dml2_core_internal_soc_state_sys_idle");
34
+
case (dml2_core_internal_soc_state_sys_active):
35
+
return("dml2_core_internal_soc_state_sys_active");
36
+
case (dml2_core_internal_soc_state_svp_prefetch):
37
+
return("dml2_core_internal_soc_state_svp_prefetch");
38
+
case dml2_core_internal_soc_state_max:
39
+
default:
40
+
return("dml2_core_internal_soc_state_unknown");
41
+
}
42
+
}
43
+
44
+
static double dml2_core_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)
45
+
{
46
+
*remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0);
47
+
return dividend / divisor;
48
+
}
49
+
50
+
static void dml2_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
18
51
{
19
52
dml2_printf("DML: ===================================== \n");
20
53
dml2_printf("DML: DML_MODE_SUPPORT_INFO_ST\n");
21
-
if (!fail_only || support->ImmediateFlipSupport == 0)
22
-
dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);
23
-
if (!fail_only || support->WritebackLatencySupport == 0)
24
-
dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);
25
54
if (!fail_only || support->ScaleRatioAndTapsSupport == 0)
26
55
dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport);
27
56
if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)
28
57
dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport);
29
-
if (!fail_only || support->P2IWith420 == 1)
30
-
dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420);
31
-
if (!fail_only || support->DSCOnlyIfNecessaryWithBPP == 1)
32
-
dml2_printf("DML: support: DSCOnlyIfNecessaryWithBPP = %d\n", support->DSCOnlyIfNecessaryWithBPP);
33
-
if (!fail_only || support->DSC422NativeNotSupported == 1)
34
-
dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);
35
-
if (!fail_only || support->DSCSlicesODMModeSupported == 0)
36
-
dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);
58
+
if (!fail_only || support->ViewportSizeSupport == 0)
59
+
dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);
37
60
if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)
38
61
dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion);
39
62
if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)
···
65
42
dml2_printf("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated);
66
43
if (!fail_only || support->MultistreamWithHDMIOreDP == 1)
67
44
dml2_printf("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP);
45
+
if (!fail_only || support->ExceededMultistreamSlots == 1)
46
+
dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);
68
47
if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)
69
48
dml2_printf("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink);
70
49
if (!fail_only || support->NotEnoughLanesForMSO == 1)
71
50
dml2_printf("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO);
72
-
if (!fail_only || support->NumberOfOTGSupport == 0)
73
-
dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);
74
-
if (!fail_only || support->NumberOfHDMIFRLSupport == 0)
75
-
dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);
76
-
if (!fail_only || support->NumberOfDP2p0Support == 0)
77
-
dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);
78
-
if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)
79
-
dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);
80
-
if (!fail_only || support->CursorSupport == 0)
81
-
dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport);
82
-
if (!fail_only || support->PitchSupport == 0)
83
-
dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport);
84
-
if (!fail_only || support->ViewportExceedsSurface == 1)
85
-
dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);
86
-
if (!fail_only || support->ExceededMALLSize == 1)
87
-
dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);
88
-
if (!fail_only || support->EnoughWritebackUnits == 0)
89
-
dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);
90
-
if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)
91
-
dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);
92
-
if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)
93
-
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);
94
-
if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)
95
-
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);
96
-
if (!fail_only || support->ExceededMultistreamSlots == 1)
97
-
dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);
51
+
if (!fail_only || support->P2IWith420 == 1)
52
+
dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420);
53
+
if (!fail_only || support->DSC422NativeNotSupported == 1)
54
+
dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);
55
+
if (!fail_only || support->DSCSlicesODMModeSupported == 0)
56
+
dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);
98
57
if (!fail_only || support->NotEnoughDSCUnits == 1)
99
58
dml2_printf("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits);
100
59
if (!fail_only || support->NotEnoughDSCSlices == 1)
101
60
dml2_printf("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices);
102
-
if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)
103
-
dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);
61
+
if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)
62
+
dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);
63
+
if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)
64
+
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);
104
65
if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)
105
66
dml2_printf("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported);
67
+
if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)
68
+
dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);
106
69
if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)
107
70
dml2_printf("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported);
108
-
if (!fail_only || support->LinkCapacitySupport == 0)
109
-
dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);
71
+
if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)
72
+
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);
110
73
if (!fail_only || support->ROBSupport == 0)
111
74
dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport);
112
75
if (!fail_only || support->OutstandingRequestsSupport == 0)
113
76
dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);
114
77
if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)
115
78
dml2_printf("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance);
116
-
if (!fail_only || support->PTEBufferSizeNotExceeded == 0)
117
-
dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);
118
-
if (!fail_only || support->AvgBandwidthSupport == 0)
119
-
dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);
120
-
if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)
121
-
dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);
122
-
if (!fail_only || support->PrefetchSupported == 0)
123
-
dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);
124
-
if (!fail_only || support->DynamicMetadataSupported == 0)
125
-
dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);
126
-
if (!fail_only || support->VRatioInPrefetchSupported == 0)
127
-
dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);
128
79
if (!fail_only || support->DISPCLK_DPPCLK_Support == 0)
129
80
dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support);
130
81
if (!fail_only || support->TotalAvailablePipesSupport == 0)
131
82
dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport);
83
+
if (!fail_only || support->NumberOfOTGSupport == 0)
84
+
dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);
85
+
if (!fail_only || support->NumberOfHDMIFRLSupport == 0)
86
+
dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);
87
+
if (!fail_only || support->NumberOfDP2p0Support == 0)
88
+
dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);
89
+
if (!fail_only || support->EnoughWritebackUnits == 0)
90
+
dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);
91
+
if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)
92
+
dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);
93
+
if (!fail_only || support->WritebackLatencySupport == 0)
94
+
dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);
95
+
if (!fail_only || support->CursorSupport == 0)
96
+
dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport);
97
+
if (!fail_only || support->PitchSupport == 0)
98
+
dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport);
99
+
if (!fail_only || support->ViewportExceedsSurface == 1)
100
+
dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);
101
+
if (!fail_only || support->PrefetchSupported == 0)
102
+
dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);
103
+
if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)
104
+
dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);
105
+
if (!fail_only || support->AvgBandwidthSupport == 0)
106
+
dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);
107
+
if (!fail_only || support->DynamicMetadataSupported == 0)
108
+
dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);
109
+
if (!fail_only || support->VRatioInPrefetchSupported == 0)
110
+
dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);
111
+
if (!fail_only || support->PTEBufferSizeNotExceeded == 1)
112
+
dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);
113
+
if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 1)
114
+
dml2_printf("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded);
115
+
if (!fail_only || support->ExceededMALLSize == 1)
116
+
dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);
117
+
if (!fail_only || support->g6_temp_read_support == 0)
118
+
dml2_printf("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);
119
+
if (!fail_only || support->ImmediateFlipSupport == 0)
120
+
dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);
121
+
if (!fail_only || support->LinkCapacitySupport == 0)
122
+
dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);
123
+
132
124
if (!fail_only || support->ModeSupport == 0)
133
125
dml2_printf("DML: support: ModeSupport = %d\n", support->ModeSupport);
134
-
if (!fail_only || support->ViewportSizeSupport == 0)
135
-
dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);
136
126
dml2_printf("DML: ===================================== \n");
137
127
}
138
128
···
2885
2849
s->HostVMDynamicLevels = CalculateHostVMDynamicLevels(p->display_cfg->gpuvm_enable, p->display_cfg->hostvm_enable, p->HostVMMinPageSize, p->display_cfg->hostvm_max_non_cached_page_table_levels);
2886
2850
2887
2851
for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) {
2888
-
if (p->display_cfg->hostvm_enable == true) {
2852
+
if (p->display_cfg->gpuvm_enable == true) {
2889
2853
p->vm_group_bytes[k] = 512;
2890
2854
p->dpte_group_bytes[k] = 512;
2891
-
} else if (p->display_cfg->gpuvm_enable == true) {
2892
-
p->vm_group_bytes[k] = 2048;
2893
-
if (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes >= 64 && dml_is_vertical_rotation(p->myPipe[k].RotationAngle)) {
2894
-
p->dpte_group_bytes[k] = 512;
2895
-
} else {
2896
-
p->dpte_group_bytes[k] = 2048;
2897
-
}
2898
2855
} else {
2899
2856
p->vm_group_bytes[k] = 0;
2900
2857
p->dpte_group_bytes[k] = 0;
···
4585
4556
return;
4586
4557
}
4587
4558
4588
-
4589
-
if (!p->setup_for_tdlut) {
4590
-
*p->tdlut_groups_per_2row_ub = 0;
4591
-
*p->tdlut_opt_time = 0;
4592
-
*p->tdlut_drain_time = 0;
4593
-
*p->tdlut_bytes_per_group = 0;
4594
-
return;
4595
-
}
4596
-
4597
4559
if (p->tdlut_mpc_width_flag) {
4598
4560
tdlut_mpc_width = 33;
4599
4561
tdlut_bytes_per_group_simple = 39*256;
···
4644
4624
4645
4625
//the tdlut is fetched during the 2 row times of prefetch.
4646
4626
if (p->setup_for_tdlut) {
4647
-
*p->tdlut_groups_per_2row_ub = (unsigned int)math_ceil2(*p->tdlut_bytes_per_frame / *p->tdlut_bytes_per_group, 1);
4627
+
*p->tdlut_groups_per_2row_ub = (unsigned int)math_ceil2((double) *p->tdlut_bytes_per_frame / *p->tdlut_bytes_per_group, 1);
4648
4628
*p->tdlut_opt_time = (*p->tdlut_bytes_per_frame - p->cursor_buffer_size * 1024) / tdlut_drain_rate;
4649
4629
*p->tdlut_drain_time = p->cursor_buffer_size * 1024 / tdlut_drain_rate;
4650
4630
}
···
4657
4637
4658
4638
dml2_printf("DML::%s: dispclk_mhz = %f\n", __func__, p->dispclk_mhz);
4659
4639
dml2_printf("DML::%s: tdlut_width = %u\n", __func__, tdlut_width);
4660
-
dml2_printf("DML::%s: tdlut_addressing_mode = %u\n", __func__, p->tdlut_addressing_mode);
4640
+
dml2_printf("DML::%s: tdlut_addressing_mode = %s\n", __func__, (p->tdlut_addressing_mode == dml2_tdlut_sw_linear) ? "sw_linear" : "simple_linear");
4661
4641
dml2_printf("DML::%s: tdlut_pitch_bytes = %u\n", __func__, tdlut_pitch_bytes);
4662
4642
dml2_printf("DML::%s: tdlut_footprint_bytes = %u\n", __func__, tdlut_footprint_bytes);
4663
4643
dml2_printf("DML::%s: tdlut_bytes_per_frame = %u\n", __func__, *p->tdlut_bytes_per_frame);
···
4723
4703
static double CalculateTWait(
4724
4704
long reserved_vblank_time_ns,
4725
4705
double UrgentLatency,
4726
-
double Ttrip)
4706
+
double Ttrip,
4707
+
double g6_temp_read_blackout_us)
4727
4708
{
4728
4709
double TWait;
4729
4710
double t_urg_trip = math_max2(UrgentLatency, Ttrip);
4730
-
TWait = reserved_vblank_time_ns/1000.0 + t_urg_trip;
4711
+
TWait = math_max2(reserved_vblank_time_ns/1000.0, g6_temp_read_blackout_us) + t_urg_trip;
4731
4712
4732
4713
#ifdef __DML_VBA_DEBUG__
4733
4714
dml2_printf("DML::%s: reserved_vblank_time_ns = %d\n", __func__, reserved_vblank_time_ns);
···
4876
4855
}
4877
4856
4878
4857
if (!exclude_this_plane) {
4879
-
surface_required_bw[k] = math_max4(NumberOfDPP[k] * prefetch_vmrow_bw[k],
4880
-
l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur,
4881
-
l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre,
4882
-
(ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k]);
4858
+
l->vm_row_bw = NumberOfDPP[k] * prefetch_vmrow_bw[k];
4859
+
l->flip_and_active_bw = l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur;
4860
+
l->flip_and_prefetch_bw = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre;
4861
+
l->active_and_excess_bw = (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k];
4862
+
surface_required_bw[k] = math_max4(l->vm_row_bw, l->flip_and_active_bw, l->flip_and_prefetch_bw, l->active_and_excess_bw);
4883
4863
4884
4864
/* export peak required bandwidth for the surface */
4885
4865
surface_peak_required_bw[k] = math_max2(surface_required_bw[k], surface_peak_required_bw[k]);
4866
+
4867
+
#ifdef __DML_VBA_DEBUG__
4868
+
dml2_printf("DML::%s: k=%d, max1: vm_row_bw=%f\n", __func__, k, l->vm_row_bw);
4869
+
dml2_printf("DML::%s: k=%d, max2: flip_and_active_bw=%f\n", __func__, k, l->flip_and_active_bw);
4870
+
dml2_printf("DML::%s: k=%d, max3: flip_and_prefetch_bw=%f\n", __func__, k, l->flip_and_prefetch_bw);
4871
+
dml2_printf("DML::%s: k=%d, max4: active_and_excess_bw=%f\n", __func__, k, l->active_and_excess_bw);
4872
+
dml2_printf("DML::%s: k=%d, surface_required_bw=%f\n", __func__, k, surface_required_bw[k]);
4873
+
dml2_printf("DML::%s: k=%d, surface_peak_required_bw=%f\n", __func__, k, surface_peak_required_bw[k]);
4874
+
#endif
4886
4875
} else {
4887
4876
surface_required_bw[k] = 0.0;
4888
4877
}
···
4901
4870
4902
4871
#ifdef __DML_VBA_DEBUG__
4903
4872
dml2_printf("DML::%s: k=%d, NumberOfDPP=%d\n", __func__, k, NumberOfDPP[k]);
4873
+
dml2_printf("DML::%s: k=%d, use_qual_row_bw=%d\n", __func__, k, use_qual_row_bw);
4874
+
dml2_printf("DML::%s: k=%d, immediate_flip=%d\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip);
4904
4875
dml2_printf("DML::%s: k=%d, mall_svp_prefetch_factor=%f\n", __func__, k, l->mall_svp_prefetch_factor);
4905
4876
dml2_printf("DML::%s: k=%d, adj_factor_p0=%f\n", __func__, k, l->adj_factor_p0);
4906
4877
dml2_printf("DML::%s: k=%d, adj_factor_p1=%f\n", __func__, k, l->adj_factor_p1);
···
4916
4883
dml2_printf("DML::%s: k=%d, prefetch_vmrow_bw=%f\n", __func__, k, prefetch_vmrow_bw[k]);
4917
4884
dml2_printf("DML::%s: k=%d, ReadBandwidthLuma=%f\n", __func__, k, ReadBandwidthLuma[k]);
4918
4885
dml2_printf("DML::%s: k=%d, ReadBandwidthChroma=%f\n", __func__, k, ReadBandwidthChroma[k]);
4886
+
dml2_printf("DML::%s: k=%d, excess_vactive_fill_bw_l=%f\n", __func__, k, excess_vactive_fill_bw_l[k]);
4887
+
dml2_printf("DML::%s: k=%d, excess_vactive_fill_bw_c=%f\n", __func__, k, excess_vactive_fill_bw_c[k]);
4919
4888
dml2_printf("DML::%s: k=%d, cursor_bw=%f\n", __func__, k, cursor_bw[k]);
4920
4889
4921
4890
dml2_printf("DML::%s: k=%d, meta_row_bw=%f\n", __func__, k, meta_row_bw[k]);
···
5072
5037
s->bytes_pp = 0.0;
5073
5038
s->dep_bytes = 0.0;
5074
5039
s->min_Lsw_oto = 0.0;
5040
+
s->min_Lsw_equ = 0.0;
5075
5041
s->Tsw_est1 = 0.0;
5042
+
s->Tsw_est2 = 0.0;
5076
5043
s->Tsw_est3 = 0.0;
5077
5044
s->cursor_prefetch_bytes = 0;
5078
5045
*p->prefetch_cursor_bw = 0;
···
5096
5059
dml2_printf("DML::%s: GPUVMPageTableLevels = %u\n", __func__, p->display_cfg->gpuvm_max_page_table_levels);
5097
5060
dml2_printf("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable);
5098
5061
dml2_printf("DML::%s: VStartup = %u\n", __func__, p->VStartup);
5099
-
dml2_printf("DML::%s: MaxVStartup = %u\n", __func__, p->MaxVStartup);
5100
5062
dml2_printf("DML::%s: HostVMEnable = %u\n", __func__, p->display_cfg->hostvm_enable);
5101
5063
dml2_printf("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p->HostVMInefficiencyFactor);
5102
5064
dml2_printf("DML::%s: TWait = %f\n", __func__, p->TWait);
···
5128
5092
5129
5093
s->LineTime = p->myPipe->HTotal / p->myPipe->PixelClock;
5130
5094
s->trip_to_mem = p->Ttrip;
5131
-
#ifdef DML_TVM_UPDATE_EN
5132
5095
*p->Tvm_trips = p->ExtraLatencyPrefetch + math_max2(s->trip_to_mem * (p->display_cfg->gpuvm_max_page_table_levels * (s->HostVMDynamicLevelsTrips + 1)), p->Turg);
5133
5096
if (dcc_mrq_enable)
5134
5097
*p->Tvm_trips_flip = *p->Tvm_trips;
5135
5098
else
5136
5099
*p->Tvm_trips_flip = *p->Tvm_trips - s->trip_to_mem;
5137
-
#else
5138
-
*p->Tvm_trips = p->ExtraLatencyPrefetch + s->trip_to_mem * (p->display_cfg->gpuvm_max_page_table_levels * (s->HostVMDynamicLevelsTrips + 1));
5139
-
*p->Tvm_trips_flip = *p->Tvm_trips - s->trip_to_mem;
5140
-
#endif
5141
5100
5142
5101
*p->Tr0_trips_flip = s->trip_to_mem * (s->HostVMDynamicLevelsTrips + 1);
5143
5102
*p->Tr0_trips = math_max2(*p->Tr0_trips_flip, p->tdlut_opt_time / 2);
5144
5103
5145
-
#ifdef DML_TVM_UPDATE_EN
5146
5104
if (p->DynamicMetadataVMEnabled == true) {
5147
5105
*p->Tdmdl_vm = s->TWait_p + *p->Tvm_trips;
5148
5106
*p->Tdmdl = *p->Tdmdl_vm + p->Ttrip;
···
5144
5114
*p->Tdmdl_vm = 0;
5145
5115
*p->Tdmdl = s->TWait_p + p->ExtraLatencyPrefetch + p->Ttrip; // Tex
5146
5116
}
5147
-
#else
5148
-
if (p->DynamicMetadataVMEnabled == true) {
5149
-
*p->Tdmdl_vm = s->TWait_p + *p->Tvm_trips;
5150
-
*p->Tdmdl = *p->Tdmdl_vm + p->Ttrip;
5151
-
} else {
5152
-
*p->Tdmdl_vm = 0;
5153
-
*p->Tdmdl = p->TWait + p->ExtraLatencyPrefetch; // Tex
5154
-
}
5155
-
#endif
5156
5117
5157
5118
if (p->DynamicMetadataEnable == true) {
5158
5119
if (p->VStartup * s->LineTime < *p->TSetup + *p->Tdmdl + s->Tdmbf + s->Tdmec + s->Tdmsks) {
···
5207
5186
dml2_printf("DML::%s: DSTYAfterScaler = %u (final)\n", __func__, *p->DSTYAfterScaler);
5208
5187
#endif
5209
5188
5210
-
s->NoTimeToPrefetch = false;
5211
5189
#ifdef __DML_VBA_DEBUG__
5212
5190
dml2_printf("DML::%s: Tr0_trips = %f\n", __func__, *p->Tr0_trips);
5213
5191
dml2_printf("DML::%s: Tvm_trips = %f\n", __func__, *p->Tvm_trips);
···
5219
5199
s->Tvm_trips_rounded = math_ceil2(4.0 * *p->Tvm_trips / s->LineTime, 1.0) / 4.0 * s->LineTime;
5220
5200
*p->Tvm_trips_flip_rounded = math_ceil2(4.0 * *p->Tvm_trips_flip / s->LineTime, 1.0) / 4.0 * s->LineTime;
5221
5201
} else {
5222
-
#ifdef DML_TVM_UPDATE_EN
5223
5202
if (p->DynamicMetadataEnable || dcc_mrq_enable || p->setup_for_tdlut)
5224
5203
s->Tvm_trips_rounded = math_max2(s->LineTime * math_ceil2(4.0*math_max3(p->ExtraLatencyPrefetch, p->Turg, s->trip_to_mem)/s->LineTime, 1)/4, s->LineTime/4.0);
5225
5204
else
5226
-
s->Tvm_trips_rounded = s->LineTime / 4.0;
5227
-
#else
5228
-
s->Tvm_trips_rounded = s->LineTime / 4.0;
5229
-
#endif
5205
+
s->Tvm_trips_rounded = s->LineTime / 4.0;
5230
5206
*p->Tvm_trips_flip_rounded = s->LineTime / 4.0;
5231
5207
}
5232
5208
···
5251
5235
*p->Tno_bw = 0;
5252
5236
}
5253
5237
5254
-
#ifdef DML_TVM_UPDATE_EN
5255
5238
if (p->mrq_present || p->display_cfg->gpuvm_max_page_table_levels >= 3)
5256
5239
*p->Tno_bw_flip = *p->Tno_bw;
5257
5240
else
5258
5241
*p->Tno_bw_flip = 0; //because there is no 3DLUT for iFlip
5259
-
#else
5260
-
*p->Tno_bw_flip = 0;
5261
-
if (p->display_cfg->gpuvm_enable == true)
5262
-
*p->Tno_bw_flip = *p->Tno_bw;
5263
-
#endif
5264
5242
5265
5243
if (dml_is_420(p->myPipe->SourcePixelFormat)) {
5266
5244
s->bytes_pp = p->myPipe->BytePerPixelY + p->myPipe->BytePerPixelC / 4.0;
···
5275
5265
s->min_Lsw_oto = math_max2(p->PrefetchSourceLinesY, p->PrefetchSourceLinesC) / __DML2_CALCS_MAX_VRATIO_PRE_OTO__;
5276
5266
s->min_Lsw_oto = math_max2(s->min_Lsw_oto, 2.0);
5277
5267
s->min_Lsw_oto = math_max2(s->min_Lsw_oto, p->tdlut_drain_time / s->LineTime);
5268
+
5269
+
s->min_Lsw_equ = math_max2(p->PrefetchSourceLinesY, p->PrefetchSourceLinesC) / __DML2_CALCS_MAX_VRATIO_PRE_EQU__;
5270
+
s->min_Lsw_equ = math_max2(s->min_Lsw_equ, 2.0);
5271
+
s->min_Lsw_equ = math_max2(s->min_Lsw_equ, p->tdlut_drain_time / s->LineTime);
5278
5272
5279
5273
vm_bytes = p->vm_bytes; // vm_bytes is dpde0_bytes_per_frame_ub_l + dpde0_bytes_per_frame_ub_c + 2*extra_dpde_bytes;
5280
5274
extra_tdpe_bytes = (unsigned int)math_max2(0, (p->display_cfg->gpuvm_max_page_table_levels - 1) * 128);
···
5303
5289
dml2_printf("DML::%s: Tvm_oto max2 = %f\n", __func__, s->LineTime / 4.0);
5304
5290
#endif
5305
5291
} else {
5306
-
#ifdef DML_TVM_UPDATE_EN
5307
5292
s->Tvm_oto = s->Tvm_trips_rounded;
5308
-
#else
5309
-
s->Tvm_oto = s->LineTime / 4.0;
5310
-
#endif
5311
5293
}
5312
5294
5313
5295
if ((p->display_cfg->gpuvm_enable == true || p->setup_for_tdlut || dcc_mrq_enable)) {
···
5327
5317
Lo = (unsigned int)(*p->DSTYAfterScaler + (double)*p->DSTXAfterScaler / (double)p->myPipe->HTotal);
5328
5318
5329
5319
//Tpre_equ in line time
5330
-
#ifdef DML_TVM_UPDATE_EN
5331
5320
if (p->DynamicMetadataVMEnabled && p->DynamicMetadataEnable)
5332
5321
s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(p->TCalc, *p->Tvm_trips) + s->TWait_p) / s->LineTime - Lo;
5333
5322
else
5334
5323
s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(p->TCalc, p->ExtraLatencyPrefetch) + s->TWait_p) / s->LineTime - Lo;
5335
-
#else
5336
-
s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(s->TWait_p + p->TCalc, *p->Tdmdl - p->Ttrip)) / s->LineTime - Lo;
5337
-
#endif
5338
5324
s->dst_y_prefetch_equ = math_min2(s->dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
5339
5325
5340
5326
#ifdef __DML_VBA_DEBUG__
5341
5327
dml2_printf("DML::%s: HTotal = %u\n", __func__, p->myPipe->HTotal);
5342
5328
dml2_printf("DML::%s: min_Lsw_oto = %f\n", __func__, s->min_Lsw_oto);
5329
+
dml2_printf("DML::%s: min_Lsw_equ = %f\n", __func__, s->min_Lsw_equ);
5343
5330
dml2_printf("DML::%s: Tno_bw = %f\n", __func__, *p->Tno_bw);
5344
5331
dml2_printf("DML::%s: Tno_bw_flip = %f\n", __func__, *p->Tno_bw_flip);
5345
5332
dml2_printf("DML::%s: ExtraLatencyPrefetch = %f\n", __func__, p->ExtraLatencyPrefetch);
···
5374
5367
s->dst_y_prefetch_equ = math_floor2(4.0 * (s->dst_y_prefetch_equ + 0.125), 1) / 4.0;
5375
5368
s->Tpre_rounded = s->dst_y_prefetch_equ * s->LineTime;
5376
5369
5370
+
#ifdef __DML_VBA_DEBUG__
5377
5371
dml2_printf("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, s->dst_y_prefetch_equ);
5378
5372
dml2_printf("DML::%s: LineTime: %f\n", __func__, s->LineTime);
5379
5373
dml2_printf("DML::%s: VStartup: %u\n", __func__, p->VStartup);
···
5395
5387
dml2_printf("DML::%s: Ttrip: %fus\n", __func__, p->Ttrip);
5396
5388
dml2_printf("DML::%s: DSTXAfterScaler: %u pixels - number of pixel clocks pipeline and buffer delay after scaler \n", __func__, *p->DSTXAfterScaler);
5397
5389
dml2_printf("DML::%s: DSTYAfterScaler: %u lines - number of lines of pipeline and buffer delay after scaler \n", __func__, *p->DSTYAfterScaler);
5398
-
5399
-
s->dep_bytes = math_max2(vm_bytes * p->HostVMInefficiencyFactor, p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes);
5400
-
5401
-
dml2_printf("DML::%s: dep_bytes: %f\n", __func__, s->dep_bytes);
5402
-
dml2_printf("DML::%s: prefetch_sw_bytes: %f\n", __func__, s->prefetch_sw_bytes);
5403
5390
dml2_printf("DML::%s: vm_bytes: %f (hvm inefficiency scaled)\n", __func__, vm_bytes*p->HostVMInefficiencyFactor);
5404
5391
dml2_printf("DML::%s: row_bytes: %f (hvm inefficiency scaled, 1 row)\n", __func__, p->PixelPTEBytesPerRow*p->HostVMInefficiencyFactor+p->meta_row_bytes+tdlut_row_bytes);
5405
-
5406
-
if (s->prefetch_sw_bytes < s->dep_bytes) {
5407
-
s->prefetch_sw_bytes = 2 * s->dep_bytes;
5408
-
dml2_printf("DML::%s: bump prefetch_sw_bytes to %f\n", __func__, s->prefetch_sw_bytes);
5409
-
}
5392
+
dml2_printf("DML::%s: Tno_bw: %f\n", __func__, *p->Tno_bw);
5393
+
dml2_printf("DML::%s: Tpre=%f Tpre_rounded: %f, delta=%f\n", __func__, Tpre, s->Tpre_rounded, (s->Tpre_rounded - Tpre));
5394
+
dml2_printf("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p->Tvm_trips, s->Tvm_trips_rounded, (s->Tvm_trips_rounded - *p->Tvm_trips));
5395
+
#endif
5410
5396
5411
5397
*p->dst_y_per_vm_vblank = 0;
5412
5398
*p->dst_y_per_row_vblank = 0;
···
5413
5411
// Tvm_trips_rounded is Tvm_trips ceiling to 1/4 line time
5414
5412
// Tr0_trips_rounded is Tr0_trips ceiling to 1/4 line time
5415
5413
// So that means prefetch bw calculated can be higher since the total time availabe for prefetch is less
5416
-
if (s->dst_y_prefetch_equ > 1) {
5414
+
bool min_Lsw_equ_ok = s->Tpre_rounded >= s->Tvm_trips_rounded + 2.0*s->Tr0_trips_rounded + s->min_Lsw_equ*s->LineTime;
5415
+
5416
+
if (s->dst_y_prefetch_equ > 1 && min_Lsw_equ_ok) {
5417
5417
s->prefetch_bw1 = 0.;
5418
5418
s->prefetch_bw2 = 0.;
5419
5419
s->prefetch_bw3 = 0.;
···
5432
5428
s->prefetch_bw1 = 0;
5433
5429
5434
5430
dml2_printf("DML::%s: prefetch_bw1: %f\n", __func__, s->prefetch_bw1);
5435
-
if ((p->VStartup == p->MaxVStartup) && (s->Tsw_est1 / s->LineTime < s->min_Lsw_oto) && (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw > 0)) {
5431
+
if ((s->Tsw_est1 < s->min_Lsw_equ * s->LineTime) && (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw > 0)) {
5436
5432
s->prefetch_bw1 = (vm_bytes * p->HostVMInefficiencyFactor + 2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) /
5437
-
(s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw);
5433
+
(s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw);
5438
5434
#ifdef __DML_VBA_DEBUG__
5439
5435
dml2_printf("DML::%s: vm and 2 rows bytes = %f\n", __func__, (vm_bytes * p->HostVMInefficiencyFactor + 2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)));
5440
5436
dml2_printf("DML::%s: Tpre_rounded = %f\n", __func__, s->Tpre_rounded);
5441
-
dml2_printf("DML::%s: minus term = %f\n", __func__, s->min_Lsw_oto * s->LineTime + 0.75 * s->LineTime + *p->Tno_bw);
5442
-
dml2_printf("DML::%s: min_Lsw_oto = %f\n", __func__, s->min_Lsw_oto);
5437
+
dml2_printf("DML::%s: minus term = %f\n", __func__, s->min_Lsw_equ * s->LineTime + 0.75 * s->LineTime + *p->Tno_bw);
5438
+
dml2_printf("DML::%s: min_Lsw_equ = %f\n", __func__, s->min_Lsw_equ);
5443
5439
dml2_printf("DML::%s: LineTime = %f\n", __func__, s->LineTime);
5444
5440
dml2_printf("DML::%s: Tno_bw = %f\n", __func__, *p->Tno_bw);
5445
-
dml2_printf("DML::%s: Time to fetch vm and 2 rows = %f\n", __func__, (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw));
5441
+
dml2_printf("DML::%s: Time to fetch vm and 2 rows = %f\n", __func__, (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw));
5446
5442
dml2_printf("DML::%s: prefetch_bw1: %f (updated)\n", __func__, s->prefetch_bw1);
5447
5443
#endif
5448
5444
}
5449
5445
5450
5446
// prefetch_bw2: VM + SW
5451
-
if (s->Tpre_rounded - *p->Tno_bw - 2 * s->Tr0_trips_rounded > 0)
5447
+
if (s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded > 0) {
5452
5448
s->prefetch_bw2 = (vm_bytes * p->HostVMInefficiencyFactor + s->prefetch_sw_bytes) /
5453
-
(s->Tpre_rounded - *p->Tno_bw - 2 * s->Tr0_trips_rounded);
5454
-
else
5449
+
(s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded);
5450
+
s->Tsw_est2 = s->prefetch_sw_bytes / s->prefetch_bw2;
5451
+
} else
5455
5452
s->prefetch_bw2 = 0;
5453
+
5454
+
dml2_printf("DML::%s: prefetch_bw2: %f\n", __func__, s->prefetch_bw2);
5455
+
if ((s->Tsw_est2 < s->min_Lsw_equ * s->LineTime) && ((s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded - s->min_Lsw_equ * s->LineTime - 0.25 * s->LineTime) > 0)) {
5456
+
s->prefetch_bw2 = vm_bytes * p->HostVMInefficiencyFactor / (s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded - s->min_Lsw_equ * s->LineTime - 0.25 * s->LineTime);
5457
+
dml2_printf("DML::%s: prefetch_bw2: %f (updated)\n", __func__, s->prefetch_bw2);
5458
+
}
5456
5459
5457
5460
// prefetch_bw3: 2*R0 + SW
5458
5461
if (s->Tpre_rounded - s->Tvm_trips_rounded > 0) {
···
5470
5459
s->prefetch_bw3 = 0;
5471
5460
5472
5461
dml2_printf("DML::%s: prefetch_bw3: %f\n", __func__, s->prefetch_bw3);
5473
-
if (p->VStartup == p->MaxVStartup && (s->Tsw_est3 / s->LineTime < s->min_Lsw_oto) && ((s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded) > 0)) {
5474
-
s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) / (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded);
5462
+
if ((s->Tsw_est3 < s->min_Lsw_equ * s->LineTime) && ((s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded) > 0)) {
5463
+
s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) / (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded);
5475
5464
dml2_printf("DML::%s: prefetch_bw3: %f (updated)\n", __func__, s->prefetch_bw3);
5476
5465
}
5477
5466
···
5487
5476
dml2_printf("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p->Tvm_trips, s->Tvm_trips_rounded, (s->Tvm_trips_rounded - *p->Tvm_trips));
5488
5477
dml2_printf("DML::%s: Tr0_trips=%f Tr0_trips_rounded: %f, delta=%f\n", __func__, *p->Tr0_trips, s->Tr0_trips_rounded, (s->Tr0_trips_rounded - *p->Tr0_trips));
5489
5478
dml2_printf("DML::%s: Tsw_est1: %f\n", __func__, s->Tsw_est1);
5479
+
dml2_printf("DML::%s: Tsw_est2: %f\n", __func__, s->Tsw_est2);
5490
5480
dml2_printf("DML::%s: Tsw_est3: %f\n", __func__, s->Tsw_est3);
5491
5481
dml2_printf("DML::%s: prefetch_bw1: %f (final)\n", __func__, s->prefetch_bw1);
5492
5482
dml2_printf("DML::%s: prefetch_bw2: %f (final)\n", __func__, s->prefetch_bw2);
···
5508
5496
// here is to make sure equ bw wont be more agressive than the latency-based requirement.
5509
5497
// check vm time >= vm_trips
5510
5498
// check r0 time >= r0_trips
5499
+
5500
+
double total_row_bytes = (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes);
5501
+
5502
+
dml2_printf("DML::%s: Tvm_trips_rounded = %f\n", __func__, s->Tvm_trips_rounded);
5503
+
dml2_printf("DML::%s: Tr0_trips_rounded = %f\n", __func__, s->Tr0_trips_rounded);
5504
+
5511
5505
if (s->prefetch_bw1 > 0) {
5512
-
if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw1 >= s->Tvm_trips_rounded &&
5513
-
(p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw1 >= s->Tr0_trips_rounded) {
5506
+
double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw1;
5507
+
double row_transfer_time = total_row_bytes / s->prefetch_bw1;
5508
+
dml2_printf("DML::%s: Case1: vm_transfer_time = %f\n", __func__, vm_transfer_time);
5509
+
dml2_printf("DML::%s: Case1: row_transfer_time = %f\n", __func__, row_transfer_time);
5510
+
if (vm_transfer_time >= s->Tvm_trips_rounded && row_transfer_time >= s->Tr0_trips_rounded) {
5514
5511
Case1OK = true;
5515
5512
}
5516
5513
}
···
5529
5508
// check vm time >= vm_trips
5530
5509
// check r0 time < r0_trips
5531
5510
if (s->prefetch_bw2 > 0) {
5532
-
if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw2 >= s->Tvm_trips_rounded &&
5533
-
(p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw2 < s->Tr0_trips_rounded) {
5511
+
double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw2;
5512
+
double row_transfer_time = total_row_bytes / s->prefetch_bw2;
5513
+
dml2_printf("DML::%s: Case2: vm_transfer_time = %f\n", __func__, vm_transfer_time);
5514
+
dml2_printf("DML::%s: Case2: row_transfer_time = %f\n", __func__, row_transfer_time);
5515
+
if (vm_transfer_time >= s->Tvm_trips_rounded && row_transfer_time < s->Tr0_trips_rounded) {
5534
5516
Case2OK = true;
5535
5517
}
5536
5518
}
···
5542
5518
// check vm time < vm_trips
5543
5519
// check r0 time >= r0_trips
5544
5520
if (s->prefetch_bw3 > 0) {
5545
-
if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw3 < s->Tvm_trips_rounded &&
5546
-
(p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw3 >= s->Tr0_trips_rounded) {
5521
+
double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw3;
5522
+
double row_transfer_time = total_row_bytes / s->prefetch_bw3;
5523
+
dml2_printf("DML::%s: Case3: vm_transfer_time = %f\n", __func__, vm_transfer_time);
5524
+
dml2_printf("DML::%s: Case3: row_transfer_time = %f\n", __func__, row_transfer_time);
5525
+
if (vm_transfer_time < s->Tvm_trips_rounded && row_transfer_time >= s->Tr0_trips_rounded) {
5547
5526
Case3OK = true;
5548
5527
}
5549
5528
}
···
5612
5585
s->TimeForFetchingVM = s->Tvm_equ;
5613
5586
s->TimeForFetchingRowInVBlank = s->Tr0_equ;
5614
5587
5615
-
if (p->VStartup == p->MaxVStartup) {
5616
-
*p->dst_y_per_vm_vblank = math_floor2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0;
5617
-
*p->dst_y_per_row_vblank = math_floor2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0;
5618
-
} else {
5619
-
*p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0;
5620
-
*p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0;
5621
-
}
5588
+
*p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0;
5589
+
*p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0;
5590
+
5622
5591
#ifdef __DML_VBA_DEBUG__
5623
5592
dml2_printf("DML::%s: Using equ bw scheduling for prefetch\n", __func__);
5624
5593
#endif
···
5658
5635
(double)p->MaxNumSwathY * p->SwathHeightY / (s->LinesToRequestPrefetchPixelData - (p->VInitPreFillY - 3.0) / 2.0));
5659
5636
} else {
5660
5637
s->NoTimeToPrefetch = true;
5661
-
dml2_printf("DML::%s: MyErr set. LinesToRequestPrefetchPixelData=%f VinitPreFillY=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillY);
5638
+
dml2_printf("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VinitPreFillY=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillY);
5662
5639
*p->VRatioPrefetchY = 0;
5663
5640
}
5664
5641
#ifdef __DML_VBA_DEBUG__
···
5681
5658
*p->VRatioPrefetchC = math_max2(*p->VRatioPrefetchC, (double)p->MaxNumSwathC * p->SwathHeightC / (s->LinesToRequestPrefetchPixelData - (p->VInitPreFillC - 3.0) / 2.0));
5682
5659
} else {
5683
5660
s->NoTimeToPrefetch = true;
5684
-
dml2_printf("DML::%s: MyErr set. LinesToRequestPrefetchPixelData=%f VInitPreFillC=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillC);
5661
+
dml2_printf("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VInitPreFillC=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillC);
5685
5662
*p->VRatioPrefetchC = 0;
5686
5663
}
5687
5664
#ifdef __DML_VBA_DEBUG__
···
5703
5680
#endif
5704
5681
} else {
5705
5682
s->NoTimeToPrefetch = true;
5706
-
dml2_printf("DML::%s: MyErr set, LinesToRequestPrefetchPixelData: %f, should be >= %d\n", __func__, s->LinesToRequestPrefetchPixelData, min_lsw_required);
5707
-
dml2_printf("DML::%s: MyErr set, prefetch_bw_equ: %f, should be > 0\n", __func__, s->prefetch_bw_equ);
5683
+
dml2_printf("DML::%s: No time to prefetch!, LinesToRequestPrefetchPixelData: %f, should be >= %d\n", __func__, s->LinesToRequestPrefetchPixelData, min_lsw_required);
5684
+
dml2_printf("DML::%s: No time to prefetch!, prefetch_bw_equ: %f, should be > 0\n", __func__, s->prefetch_bw_equ);
5708
5685
*p->VRatioPrefetchY = 0;
5709
5686
*p->VRatioPrefetchC = 0;
5710
5687
*p->RequiredPrefetchPixelDataBWLuma = 0;
5711
5688
*p->RequiredPrefetchPixelDataBWChroma = 0;
5712
5689
}
5713
-
5714
5690
dml2_printf("DML: Tpre: %fus - sum of time to request 2 x data pte, swaths\n", (double)s->LinesToRequestPrefetchPixelData * s->LineTime + 2.0 * s->TimeForFetchingRowInVBlank + s->TimeForFetchingVM);
5715
5691
dml2_printf("DML: Tvm: %fus - time to fetch vm\n", s->TimeForFetchingVM);
5716
5692
dml2_printf("DML: Tr0: %fus - time to fetch first row of data pagetables\n", s->TimeForFetchingRowInVBlank);
···
5720
5698
dml2_printf("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %u\n", p->PixelPTEBytesPerRow);
5721
5699
5722
5700
} else {
5723
-
dml2_printf("DML::%s: MyErr set, dst_y_prefetch_equ = %f (should be > 1)\n", __func__, s->dst_y_prefetch_equ);
5701
+
dml2_printf("DML::%s: No time to prefetch! dst_y_prefetch_equ = %f (should be > 1)\n", __func__, s->dst_y_prefetch_equ);
5702
+
dml2_printf("DML::%s: No time to prefetch! min_Lsw_equ_ok = %d, Tpre_rounded (%f) should be >= Tvm_trips_rounded (%f) + 2.0*Tr0_trips_rounded (%f) + min_Tsw_equ (%f)\n",
5703
+
__func__, min_Lsw_equ_ok, s->Tpre_rounded, s->Tvm_trips_rounded, 2.0*s->Tr0_trips_rounded, s->min_Lsw_equ*s->LineTime);
5724
5704
s->NoTimeToPrefetch = true;
5725
5705
s->TimeForFetchingVM = 0;
5726
5706
s->TimeForFetchingRowInVBlank = 0;
···
5754
5730
} else {
5755
5731
prefetch_vm_bw = 0;
5756
5732
s->NoTimeToPrefetch = true;
5757
-
dml2_printf("DML::%s: MyErr set. dst_y_per_vm_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_vm_vblank);
5733
+
dml2_printf("DML::%s: No time to prefetch!. dst_y_per_vm_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_vm_vblank);
5758
5734
}
5759
5735
5760
5736
if (p->PixelPTEBytesPerRow == 0 && tdlut_row_bytes == 0) {
···
5770
5746
} else {
5771
5747
prefetch_row_bw = 0;
5772
5748
s->NoTimeToPrefetch = true;
5773
-
dml2_printf("DML::%s: MyErr set. dst_y_per_row_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_row_vblank);
5749
+
dml2_printf("DML::%s: No time to prefetch!. dst_y_per_row_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_row_vblank);
5774
5750
}
5775
5751
5776
5752
*p->prefetch_vmrow_bw = math_max2(prefetch_vm_bw, prefetch_row_bw);
···
5787
5763
*p->VRatioPrefetchC = 0;
5788
5764
*p->RequiredPrefetchPixelDataBWLuma = 0;
5789
5765
*p->RequiredPrefetchPixelDataBWChroma = 0;
5766
+
*p->prefetch_vmrow_bw = 0;
5790
5767
}
5791
5768
5792
5769
dml2_printf("DML::%s: dst_y_per_vm_vblank = %f (final)\n", __func__, *p->dst_y_per_vm_vblank);
5793
5770
dml2_printf("DML::%s: dst_y_per_row_vblank = %f (final)\n", __func__, *p->dst_y_per_row_vblank);
5771
+
dml2_printf("DML::%s: prefetch_vmrow_bw = %f (final)\n", __func__, *p->prefetch_vmrow_bw);
5772
+
dml2_printf("DML::%s: RequiredPrefetchPixelDataBWLuma = %f (final)\n", __func__, *p->RequiredPrefetchPixelDataBWLuma);
5773
+
dml2_printf("DML::%s: RequiredPrefetchPixelDataBWChroma = %f (final)\n", __func__, *p->RequiredPrefetchPixelDataBWChroma);
5794
5774
dml2_printf("DML::%s: NoTimeToPrefetch=%d\n", __func__, s->NoTimeToPrefetch);
5775
+
5795
5776
return s->NoTimeToPrefetch;
5796
5777
}
5797
5778
···
6203
6174
{
6204
6175
struct dml2_core_shared_CalculateFlipSchedule_locals *l = &s->CalculateFlipSchedule_locals;
6205
6176
6206
-
l->dual_plane = dml2_core_shared_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha;
6177
+
l->dual_plane = dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha;
6207
6178
l->dpte_row_bytes = DPTEBytesPerRow;
6208
6179
6209
6180
#ifdef __DML_VBA_DEBUG__
···
6279
6250
#ifdef __DML_VBA_DEBUG__
6280
6251
dml2_printf("DML::%s: max_flip_time = %f\n", __func__, l->max_flip_time);
6281
6252
dml2_printf("DML::%s: total vm bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_vm_bytes);
6282
-
dml2_printf("DML::%s: total row bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_row_bytes);
6253
+
dml2_printf("DML::%s: total row bytes (%d row, hvm ineff scaled) = %f\n", __func__, l->num_rows, l->hvm_scaled_row_bytes);
6283
6254
dml2_printf("DML::%s: total vm+row bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_vm_row_bytes);
6284
6255
dml2_printf("DML::%s: lb_flip_bw for vm and row = %f\n", __func__, l->hvm_scaled_vm_row_bytes / (l->max_flip_time - Tno_bw_flip));
6285
6256
dml2_printf("DML::%s: lb_flip_bw for vm = %f\n", __func__, l->hvm_scaled_vm_bytes / (l->max_flip_time - Tno_bw_flip - 2 * Tr0_trips_flip_rounded));
···
6290
6261
dml2_printf("DML::%s: mode_support est Tr0_flip = %f (bw-based)\n", __func__, l->hvm_scaled_row_bytes / l->lb_flip_bw / l->num_rows);
6291
6262
dml2_printf("DML::%s: mode_support est dst_y_per_vm_flip = %f (bw-based)\n", __func__, Tno_bw_flip + l->hvm_scaled_vm_bytes / l->lb_flip_bw / LineTime);
6292
6263
dml2_printf("DML::%s: mode_support est dst_y_per_row_flip = %f (bw-based)\n", __func__, l->hvm_scaled_row_bytes / l->lb_flip_bw / LineTime / l->num_rows);
6264
+
dml2_printf("DML::%s: Tvm_trips_flip_rounded + 2*Tr0_trips_flip_rounded = %f\n", __func__, (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded));
6293
6265
}
6294
6266
#endif
6295
6267
l->lb_flip_bw = math_max3(l->lb_flip_bw,
···
6307
6277
6308
6278
*dst_y_per_vm_flip = 1; // not used
6309
6279
*dst_y_per_row_flip = 1; // not used
6310
-
*ImmediateFlipSupportedForPipe = true;
6280
+
*ImmediateFlipSupportedForPipe = l->min_row_time >= (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded);
6311
6281
} else {
6312
6282
if (iflip_enable) {
6313
6283
l->ImmediateFlipBW = (double)per_pipe_flip_bytes * BandwidthAvailableForImmediateFlip / (double)TotImmediateFlipBytes; // flip_bw(i)
···
6373
6343
dml2_printf("DML::%s: dst_y_per_row_flip = %f (should be < 16)\n", __func__, *dst_y_per_row_flip);
6374
6344
dml2_printf("DML::%s: Tvm_flip = %f (final)\n", __func__, l->Tvm_flip);
6375
6345
dml2_printf("DML::%s: Tr0_flip = %f (final)\n", __func__, l->Tr0_flip);
6346
+
dml2_printf("DML::%s: Tvm_flip + 2*Tr0_flip = %f (should be <= min_row_time=%f)\n", __func__, l->Tvm_flip + 2 * l->Tr0_flip, l->min_row_time);
6376
6347
}
6377
6348
dml2_printf("DML::%s: final_flip_bw = %f\n", __func__, *final_flip_bw);
6378
6349
dml2_printf("DML::%s: ImmediateFlipSupportedForPipe = %u\n", __func__, *ImmediateFlipSupportedForPipe);
···
6404
6373
p->Watermark->StutterEnterPlusExitWatermark = p->mmSOCParameters.SREnterPlusExitTime + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep;
6405
6374
p->Watermark->Z8StutterExitWatermark = p->mmSOCParameters.SRExitZ8Time + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep;
6406
6375
p->Watermark->Z8StutterEnterPlusExitWatermark = p->mmSOCParameters.SREnterPlusExitZ8Time + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep;
6376
+
if (p->mmSOCParameters.qos_type == dml2_qos_param_type_dcn4x) {
6377
+
p->Watermark->StutterExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us;
6378
+
p->Watermark->StutterEnterPlusExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us;
6379
+
p->Watermark->Z8StutterExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us;
6380
+
p->Watermark->Z8StutterEnterPlusExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us;
6381
+
}
6407
6382
p->Watermark->g6_temp_read_watermark_us = p->mmSOCParameters.g6_temp_read_blackout_us + p->Watermark->UrgentWatermark;
6408
6383
6409
6384
#ifdef __DML_VBA_DEBUG__
···
6616
6579
s->src_y_ahead_c = (unsigned int)(math_floor2(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]);
6617
6580
s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_c[k];
6618
6581
6619
-
if (dml2_core_shared_is_420(p->display_cfg->plane_descriptors[k].pixel_format))
6582
+
if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format))
6620
6583
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, 2 * s->sub_vp_lines_c));
6621
6584
else
6622
6585
p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, s->sub_vp_lines_c));
6623
6586
6624
6587
#ifdef __DML_VBA_DEBUG__
6625
-
dml2_printf("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, p->meta_row_height_c[k]);
6588
+
dml2_printf("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, k, p->meta_row_height_c[k]);
6626
6589
dml2_printf("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c);
6627
6590
dml2_printf("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c);
6628
6591
dml2_printf("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c);
···
6952
6915
return (double)blackout_us;
6953
6916
}
6954
6917
6918
+
static double get_max_urgent_latency_us(
6919
+
struct dml2_dcn4x_soc_qos_params *dcn4x,
6920
+
double uclk_freq_mhz,
6921
+
double FabricClock,
6922
+
unsigned int min_clk_index)
6923
+
{
6924
+
double latency;
6925
+
latency = dcn4x->per_uclk_dpm_params[min_clk_index].maximum_latency_when_urgent_uclk_cycles / uclk_freq_mhz
6926
+
* (1 + dcn4x->umc_max_latency_margin / 100.0)
6927
+
+ dcn4x->mall_overhead_fclk_cycles / FabricClock
6928
+
+ dcn4x->max_round_trip_to_furthest_cs_fclk_cycles / FabricClock
6929
+
* (1 + dcn4x->fabric_max_transport_latency_margin / 100.0);
6930
+
return latency;
6931
+
}
6932
+
6955
6933
static void calculate_pstate_keepout_dst_lines(
6956
6934
const struct dml2_display_cfg *display_cfg,
6957
6935
const struct dml2_core_internal_watermarks *watermarks,
···
7049
6997
dml2_printf("DML::%s: max_dscclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dscclk_freq_mhz);
7050
6998
dml2_printf("DML::%s: max_dppclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dppclk_freq_mhz);
7051
6999
dml2_printf("DML::%s: MaxFabricClock = %f\n", __func__, mode_lib->ms.MaxFabricClock);
7052
-
dml2_printf("DML::%s: max_dscclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dscclk_freq_mhz);
7053
7000
dml2_printf("DML::%s: ip.compressed_buffer_segment_size_in_kbytes = %u\n", __func__, mode_lib->ip.compressed_buffer_segment_size_in_kbytes);
7054
7001
dml2_printf("DML::%s: ip.dcn_mrq_present = %u\n", __func__, mode_lib->ip.dcn_mrq_present);
7055
7002
···
7274
7223
}
7275
7224
#endif
7276
7225
*/
7277
-
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /*FIXME_STAGE2 was: LBBitPerPixel*/ /
7226
+
mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /
7278
7227
(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio, 1.0) - 2, 0.0));
7279
7228
if (mode_lib->ms.BytePerPixelC[k] == 0.0) {
7280
7229
mode_lib->ms.MaximumSwathWidthInLineBufferChroma = 0;
7281
7230
} else {
7282
-
mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /*FIXME_STAGE2 was: LBBitPerPixel*/ /
7231
+
mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /
7283
7232
(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio, 1.0) - 2, 0.0));
7284
7233
}
7285
7234
···
7361
7310
mode_lib->ms.support.ViewportExceedsSurface = false;
7362
7311
if (!display_cfg->overrides.hw.surface_viewport_size_check_disable) {
7363
7312
for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
7364
-
if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width || display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) {
7313
+
if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width ||
7314
+
display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) {
7365
7315
mode_lib->ms.support.ViewportExceedsSurface = true;
7366
7316
#if defined(__DML_VBA_DEBUG__)
7367
7317
dml2_printf("DML::%s: k=%u ViewportWidth = %d\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width);
···
7371
7319
dml2_printf("DML::%s: k=%u SurfaceHeightY = %d\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.height);
7372
7320
dml2_printf("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib->ms.support.ViewportExceedsSurface);
7373
7321
#endif
7374
-
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
7375
-
if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width ||
7376
-
display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) {
7377
-
mode_lib->ms.support.ViewportExceedsSurface = true;
7378
-
}
7322
+
}
7323
+
if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) {
7324
+
if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width ||
7325
+
display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) {
7326
+
mode_lib->ms.support.ViewportExceedsSurface = true;
7379
7327
}
7380
7328
}
7381
7329
}
···
7651
7599
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.h_taps,
7652
7600
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.v_taps,
7653
7601
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.input_width,
7654
-
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.output_height,
7602
+
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.output_width,
7655
7603
display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total,
7656
7604
mode_lib->ip.writeback_line_buffer_buffer_size));
7657
7605
}
···
7736
7684
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true)
7737
7685
mode_lib->ms.support.P2IWith420 = true;
7738
7686
7739
-
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary && s->OutputBpp[k] != 0)
7740
-
mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = true;
7741
7687
if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support)
7742
7688
mode_lib->ms.support.DSC422NativeNotSupported = true;
7743
7689
···
8533
8483
{
8534
8484
mode_lib->ms.TimeCalc = 24 / mode_lib->ms.dcfclk_deepsleep;
8535
8485
8536
-
8537
8486
calculate_hostvm_inefficiency_factor(
8538
8487
&s->HostVMInefficiencyFactor,
8539
8488
&s->HostVMInefficiencyFactorPrefetch,
···
8617
8568
mode_lib->ms.TWait[k] = CalculateTWait(
8618
8569
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
8619
8570
mode_lib->ms.UrgLatency,
8620
-
mode_lib->ms.TripToMemory);
8571
+
mode_lib->ms.TripToMemory,
8572
+
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
8573
+
get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0);
8621
8574
8622
8575
myPipe->Dppclk = mode_lib->ms.RequiredDPPCLK[k];
8623
8576
myPipe->Dispclk = mode_lib->ms.RequiredDISPCLK;
···
8666
8615
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
8667
8616
CalculatePrefetchSchedule_params->MaxInterDCNTileRepeaters = mode_lib->ip.max_inter_dcn_tile_repeaters;
8668
8617
CalculatePrefetchSchedule_params->VStartup = s->MaximumVStartup[k];
8669
-
CalculatePrefetchSchedule_params->MaxVStartup = s->MaximumVStartup[k];
8670
8618
CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->soc.hostvm_min_page_size_kbytes;
8671
8619
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
8672
8620
CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ip.dynamic_metadata_vm_enabled;
···
8747
8697
dml2_printf("DML::%s: k=%d, dst_y_prefetch=%f (should not be < 2)\n", __func__, k, mode_lib->ms.dst_y_prefetch[k]);
8748
8698
dml2_printf("DML::%s: k=%d, LinesForVM=%f (should not be >= 32)\n", __func__, k, mode_lib->ms.LinesForVM[k]);
8749
8699
dml2_printf("DML::%s: k=%d, LinesForDPTERow=%f (should not be >= 16)\n", __func__, k, mode_lib->ms.LinesForDPTERow[k]);
8750
-
dml2_printf("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]);
8751
8700
dml2_printf("DML::%s: k=%d, DSTYAfterScaler=%d (should be <= 8)\n", __func__, k, s->DSTYAfterScaler[k]);
8701
+
dml2_printf("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]);
8752
8702
}
8753
8703
}
8754
8704
···
8761
8711
8762
8712
mode_lib->ms.support.VRatioInPrefetchSupported = true;
8763
8713
for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) {
8764
-
if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
8765
-
mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__) {
8714
+
if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
8715
+
mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
8766
8716
mode_lib->ms.support.VRatioInPrefetchSupported = false;
8717
+
dml2_printf("DML::%s: k=%d VRatioPreY = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
8718
+
dml2_printf("DML::%s: k=%d VRatioPreC = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
8767
8719
dml2_printf("DML::%s: VRatioInPrefetchSupported = %u\n", __func__, mode_lib->ms.support.VRatioInPrefetchSupported);
8768
-
}
8769
-
}
8770
-
8771
-
s->AnyLinesForVMOrRowTooLarge = false;
8772
-
for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
8773
-
if (mode_lib->ms.LinesForDPTERow[k] >= 16 || mode_lib->ms.LinesForVM[k] >= 32) {
8774
-
s->AnyLinesForVMOrRowTooLarge = true;
8775
8720
}
8776
8721
}
8777
8722
···
9006
8961
s->mSOCParameters.USRRetrainingLatency = 0;
9007
8962
s->mSOCParameters.SMNLatency = 0;
9008
8963
s->mSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index);
8964
+
s->mSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&mode_lib->soc.qos_parameters.qos_params.dcn4x, mode_lib->ms.uclk_freq_mhz, mode_lib->ms.FabricClock, in_out_params->min_clk_index);
8965
+
s->mSOCParameters.df_response_time_us = mode_lib->soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib->ms.FabricClock;
8966
+
s->mSOCParameters.qos_type = mode_lib->soc.qos_parameters.qos_type;
9009
8967
9010
8968
CalculateWatermarks_params->display_cfg = display_cfg;
9011
8969
CalculateWatermarks_params->USRRetrainingRequired = false;
···
9028
8980
CalculateWatermarks_params->DETBufferSizeC = mode_lib->ms.DETBufferSizeC;
9029
8981
CalculateWatermarks_params->SwathHeightY = mode_lib->ms.SwathHeightY;
9030
8982
CalculateWatermarks_params->SwathHeightC = mode_lib->ms.SwathHeightC;
9031
-
//CalculateWatermarks_params->LBBitPerPixel = 57; // FIXME_STAGE2, need a new ip param?
9032
8983
CalculateWatermarks_params->SwathWidthY = mode_lib->ms.SwathWidthY;
9033
8984
CalculateWatermarks_params->SwathWidthC = mode_lib->ms.SwathWidthC;
9034
8985
CalculateWatermarks_params->DPPPerSurface = mode_lib->ms.NoOfDPP;
···
9058
9011
9059
9012
calculate_pstate_keepout_dst_lines(display_cfg, &mode_lib->ms.support.watermarks, s->dummy_integer_array[0]);
9060
9013
}
9061
-
9014
+
dml2_printf("DML::%s: Done prefetch calculation\n", __func__);
9062
9015
// End of Prefetch Check
9063
9016
9064
-
dml2_printf("DML::%s: Done prefetch calculation\n", __func__);
9017
+
mode_lib->ms.support.max_urgent_latency_us = s->mSOCParameters.max_urgent_latency_us;
9065
9018
9066
9019
//Re-ordering Buffer Support Check
9067
-
mode_lib->ms.support.max_urgent_latency_us
9068
-
= mode_lib->soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib->ms.qos_param_index].maximum_latency_when_urgent_uclk_cycles / mode_lib->ms.uclk_freq_mhz
9069
-
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin / 100.0)
9070
-
+ mode_lib->soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles / mode_lib->ms.FabricClock
9071
-
+ mode_lib->soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->ms.FabricClock
9072
-
* (1 + mode_lib->soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin / 100.0);
9073
-
9074
9020
if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x) {
9075
9021
if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024
9076
-
/ mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= mode_lib->ms.support.max_urgent_latency_us) {
9022
+
/ mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= s->mSOCParameters.max_urgent_latency_us) {
9077
9023
mode_lib->ms.support.ROBSupport = true;
9078
9024
} else {
9079
9025
mode_lib->ms.support.ROBSupport = false;
···
9095
9055
mode_lib->ms.dram_change_vactive_det_fill_delay_us);
9096
9056
9097
9057
#ifdef __DML_VBA_DEBUG__
9098
-
dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.max_urgent_latency_us);
9058
+
dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, s->mSOCParameters.max_urgent_latency_us);
9099
9059
dml2_printf("DML::%s: ROBSupport = %u\n", __func__, mode_lib->ms.support.ROBSupport);
9100
9060
#endif
9101
9061
9102
9062
/*Mode Support, Voltage State and SOC Configuration*/
9103
9063
{
9104
-
// s->dram_clock_change_support = 1;
9105
-
// s->f_clock_change_support = 1;
9106
-
9107
9064
if (mode_lib->ms.support.ScaleRatioAndTapsSupport
9108
9065
&& mode_lib->ms.support.SourceFormatPixelAndScanSupport
9109
9066
&& mode_lib->ms.support.ViewportSizeSupport
···
9111
9074
&& !mode_lib->ms.support.ExceededMultistreamSlots
9112
9075
&& !mode_lib->ms.support.MSOOrODMSplitWithNonDPLink
9113
9076
&& !mode_lib->ms.support.NotEnoughLanesForMSO
9114
-
//&& mode_lib->ms.support.LinkCapacitySupport == true // FIXME_STAGE2
9115
9077
&& !mode_lib->ms.support.P2IWith420
9116
-
&& !mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP
9117
9078
&& !mode_lib->ms.support.DSC422NativeNotSupported
9118
9079
&& mode_lib->ms.support.DSCSlicesODMModeSupported
9119
9080
&& !mode_lib->ms.support.NotEnoughDSCUnits
···
9179
9144
9180
9145
#if defined(__DML_VBA_DEBUG__)
9181
9146
if (!mode_lib->ms.support.ModeSupport)
9182
-
dml2_print_dml_mode_support_info(&mode_lib->ms.support, true);
9147
+
dml2_print_mode_support_info(&mode_lib->ms.support, true);
9183
9148
9184
9149
dml2_printf("DML::%s: --- DONE --- \n", __func__);
9185
9150
#endif
···
9198
9163
*in_out_params->out_evaluation_info = in_out_params->mode_lib->ms.support;
9199
9164
9200
9165
dml2_printf("DML::%s: is_mode_support = %u (min_clk_index=%d)\n", __func__, result, in_out_params->min_clk_index);
9166
+
9167
+
for (unsigned int k = 0; k < in_out_params->in_display_cfg->num_planes; k++)
9168
+
dml2_printf("DML::%s: plane_%d: reserved_vblank_time_ns = %u\n", __func__, k, in_out_params->in_display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns);
9169
+
9201
9170
dml2_printf("DML::%s: ------------- DONE ----------\n", __func__);
9202
9171
9203
9172
return result;
···
10736
10697
mode_lib->mp.TWait[k] = CalculateTWait(
10737
10698
display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns,
10738
10699
mode_lib->mp.UrgentLatency,
10739
-
mode_lib->mp.TripToMemory);
10700
+
mode_lib->mp.TripToMemory,
10701
+
!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ?
10702
+
get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0);
10740
10703
10741
10704
myPipe->Dppclk = mode_lib->mp.Dppclk[k];
10742
10705
myPipe->Dispclk = mode_lib->mp.Dispclk;
···
10784
10743
CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format;
10785
10744
CalculatePrefetchSchedule_params->MaxInterDCNTileRepeaters = mode_lib->ip.max_inter_dcn_tile_repeaters;
10786
10745
CalculatePrefetchSchedule_params->VStartup = s->MaxVStartupLines[k];
10787
-
CalculatePrefetchSchedule_params->MaxVStartup = s->MaxVStartupLines[k];
10788
10746
CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->soc.hostvm_min_page_size_kbytes;
10789
10747
CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable;
10790
10748
CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ip.dynamic_metadata_vm_enabled;
···
10869
10829
if (mode_lib->mp.dst_y_prefetch[k] < 2)
10870
10830
s->DestinationLineTimesForPrefetchLessThan2 = true;
10871
10831
10872
-
if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ ||
10873
-
mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__)
10832
+
if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ ||
10833
+
mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) {
10874
10834
s->VRatioPrefetchMoreThanMax = true;
10835
+
dml2_printf("DML::%s: k=%d, VRatioPrefetchY=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k], __DML2_CALCS_MAX_VRATIO_PRE__);
10836
+
dml2_printf("DML::%s: k=%d, VRatioPrefetchC=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchC[k], __DML2_CALCS_MAX_VRATIO_PRE__);
10837
+
dml2_printf("DML::%s: VRatioPrefetchMoreThanMax = %u\n", __func__, s->VRatioPrefetchMoreThanMax);
10838
+
}
10875
10839
10876
10840
if (mode_lib->mp.NotEnoughUrgentLatencyHiding[k]) {
10877
10841
dml2_printf("DML::%s: k=%u, NotEnoughUrgentLatencyHiding = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHiding[k]);
···
11209
11165
s->mmSOCParameters.USRRetrainingLatency = 0;
11210
11166
s->mmSOCParameters.SMNLatency = 0;
11211
11167
s->mmSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->mp.uclk_freq_mhz * 1000), in_out_params->min_clk_index);
11168
+
s->mmSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&mode_lib->soc.qos_parameters.qos_params.dcn4x, mode_lib->ms.uclk_freq_mhz, mode_lib->ms.FabricClock, in_out_params->min_clk_index);
11169
+
s->mmSOCParameters.df_response_time_us = mode_lib->soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib->ms.FabricClock;
11170
+
s->mmSOCParameters.qos_type = mode_lib->soc.qos_parameters.qos_type;
11212
11171
11213
11172
CalculateWatermarks_params->display_cfg = display_cfg;
11214
11173
CalculateWatermarks_params->USRRetrainingRequired = false;
···
11231
11184
CalculateWatermarks_params->DETBufferSizeC = mode_lib->mp.DETBufferSizeC;
11232
11185
CalculateWatermarks_params->SwathHeightY = mode_lib->mp.SwathHeightY;
11233
11186
CalculateWatermarks_params->SwathHeightC = mode_lib->mp.SwathHeightC;
11234
-
//CalculateWatermarks_params->LBBitPerPixel = 57; //FIXME_STAGE2
11235
11187
CalculateWatermarks_params->SwathWidthY = mode_lib->mp.SwathWidthY;
11236
11188
CalculateWatermarks_params->SwathWidthC = mode_lib->mp.SwathWidthC;
11237
11189
CalculateWatermarks_params->BytePerPixelDETY = mode_lib->mp.BytePerPixelInDETY;
···
11561
11515
11562
11516
bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params)
11563
11517
{
11518
+
dml2_printf("DML::%s: ------------- START ----------\n", __func__);
11564
11519
bool result = dml_core_mode_programming(in_out_params);
11565
11520
11566
-
dml2_printf("DML::%s: ------------- START ----------\n", __func__);
11567
11521
dml2_printf("DML::%s: result = %0d\n", __func__, result);
11568
11522
dml2_printf("DML::%s: ------------- DONE ----------\n", __func__);
11569
11523
return result;
···
12473
12427
phantom_processing_delay_pix = (double)((mode_lib->ip.subvp_fw_processing_delay_us + mode_lib->ip.subvp_pstate_allow_width_us) *
12474
12428
((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.pixel_clock_khz / 1000));
12475
12429
phantom_processing_delay_lines = (unsigned int)(phantom_processing_delay_pix / (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total);
12476
-
dml2_core_shared_div_rem(phantom_processing_delay_pix,
12430
+
dml2_core_div_rem(phantom_processing_delay_pix,
12477
12431
display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total,
12478
12432
&rem);
12479
12433
if (rem)
···
12516
12470
out->informative.mode_support_info.ScaleRatioAndTapsSupport = mode_lib->ms.support.ScaleRatioAndTapsSupport;
12517
12471
out->informative.mode_support_info.SourceFormatPixelAndScanSupport = mode_lib->ms.support.SourceFormatPixelAndScanSupport;
12518
12472
out->informative.mode_support_info.P2IWith420 = mode_lib->ms.support.P2IWith420;
12519
-
out->informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP;
12473
+
out->informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = false;
12520
12474
out->informative.mode_support_info.DSC422NativeNotSupported = mode_lib->ms.support.DSC422NativeNotSupported;
12521
12475
out->informative.mode_support_info.LinkRateDoesNotMatchDPVersion = mode_lib->ms.support.LinkRateDoesNotMatchDPVersion;
12522
12476
out->informative.mode_support_info.LinkRateForMultistreamNotIndicated = mode_lib->ms.support.LinkRateForMultistreamNotIndicated;
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c
+631
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
+631
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
//
3
+
// Copyright 2024 Advanced Micro Devices, Inc.
4
+
5
+
#include "dml2_core_utils.h"
6
+
7
+
double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)
8
+
{
9
+
*remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0);
10
+
return dividend / divisor;
11
+
12
+
}
13
+
14
+
const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)
15
+
{
16
+
switch (bw_type) {
17
+
case (dml2_core_internal_bw_sdp):
18
+
return("dml2_core_internal_bw_sdp");
19
+
case (dml2_core_internal_bw_dram):
20
+
return("dml2_core_internal_bw_dram");
21
+
case (dml2_core_internal_bw_max):
22
+
return("dml2_core_internal_bw_max");
23
+
default:
24
+
return("dml2_core_internal_bw_unknown");
25
+
}
26
+
}
27
+
28
+
bool dml2_core_utils_is_420(enum dml2_source_format_class source_format)
29
+
{
30
+
bool val = false;
31
+
32
+
switch (source_format) {
33
+
case dml2_444_8:
34
+
val = 0;
35
+
break;
36
+
case dml2_444_16:
37
+
val = 0;
38
+
break;
39
+
case dml2_444_32:
40
+
val = 0;
41
+
break;
42
+
case dml2_444_64:
43
+
val = 0;
44
+
break;
45
+
case dml2_420_8:
46
+
val = 1;
47
+
break;
48
+
case dml2_420_10:
49
+
val = 1;
50
+
break;
51
+
case dml2_420_12:
52
+
val = 1;
53
+
break;
54
+
case dml2_rgbe_alpha:
55
+
val = 0;
56
+
break;
57
+
case dml2_rgbe:
58
+
val = 0;
59
+
break;
60
+
case dml2_mono_8:
61
+
val = 0;
62
+
break;
63
+
case dml2_mono_16:
64
+
val = 0;
65
+
break;
66
+
default:
67
+
DML2_ASSERT(0);
68
+
break;
69
+
}
70
+
return val;
71
+
}
72
+
73
+
void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
74
+
{
75
+
dml2_printf("DML: ===================================== \n");
76
+
dml2_printf("DML: DML_MODE_SUPPORT_INFO_ST\n");
77
+
if (!fail_only || support->ScaleRatioAndTapsSupport == 0)
78
+
dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport);
79
+
if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)
80
+
dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport);
81
+
if (!fail_only || support->ViewportSizeSupport == 0)
82
+
dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);
83
+
if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)
84
+
dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion);
85
+
if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)
86
+
dml2_printf("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support->LinkRateForMultistreamNotIndicated);
87
+
if (!fail_only || support->BPPForMultistreamNotIndicated == 1)
88
+
dml2_printf("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated);
89
+
if (!fail_only || support->MultistreamWithHDMIOreDP == 1)
90
+
dml2_printf("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP);
91
+
if (!fail_only || support->ExceededMultistreamSlots == 1)
92
+
dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);
93
+
if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)
94
+
dml2_printf("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink);
95
+
if (!fail_only || support->NotEnoughLanesForMSO == 1)
96
+
dml2_printf("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO);
97
+
if (!fail_only || support->P2IWith420 == 1)
98
+
dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420);
99
+
if (!fail_only || support->DSC422NativeNotSupported == 1)
100
+
dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);
101
+
if (!fail_only || support->DSCSlicesODMModeSupported == 0)
102
+
dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);
103
+
if (!fail_only || support->NotEnoughDSCUnits == 1)
104
+
dml2_printf("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits);
105
+
if (!fail_only || support->NotEnoughDSCSlices == 1)
106
+
dml2_printf("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices);
107
+
if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)
108
+
dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);
109
+
if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)
110
+
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);
111
+
if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)
112
+
dml2_printf("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported);
113
+
if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)
114
+
dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);
115
+
if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)
116
+
dml2_printf("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported);
117
+
if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)
118
+
dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);
119
+
if (!fail_only || support->ROBSupport == 0)
120
+
dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport);
121
+
if (!fail_only || support->OutstandingRequestsSupport == 0)
122
+
dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);
123
+
if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)
124
+
dml2_printf("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance);
125
+
if (!fail_only || support->DISPCLK_DPPCLK_Support == 0)
126
+
dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support);
127
+
if (!fail_only || support->TotalAvailablePipesSupport == 0)
128
+
dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport);
129
+
if (!fail_only || support->NumberOfOTGSupport == 0)
130
+
dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);
131
+
if (!fail_only || support->NumberOfHDMIFRLSupport == 0)
132
+
dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);
133
+
if (!fail_only || support->NumberOfDP2p0Support == 0)
134
+
dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);
135
+
if (!fail_only || support->EnoughWritebackUnits == 0)
136
+
dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);
137
+
if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)
138
+
dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);
139
+
if (!fail_only || support->WritebackLatencySupport == 0)
140
+
dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);
141
+
if (!fail_only || support->CursorSupport == 0)
142
+
dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport);
143
+
if (!fail_only || support->PitchSupport == 0)
144
+
dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport);
145
+
if (!fail_only || support->ViewportExceedsSurface == 1)
146
+
dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);
147
+
if (!fail_only || support->PrefetchSupported == 0)
148
+
dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);
149
+
if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)
150
+
dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);
151
+
if (!fail_only || support->AvgBandwidthSupport == 0)
152
+
dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);
153
+
if (!fail_only || support->DynamicMetadataSupported == 0)
154
+
dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);
155
+
if (!fail_only || support->VRatioInPrefetchSupported == 0)
156
+
dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);
157
+
if (!fail_only || support->PTEBufferSizeNotExceeded == 1)
158
+
dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);
159
+
if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 1)
160
+
dml2_printf("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded);
161
+
if (!fail_only || support->ExceededMALLSize == 1)
162
+
dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);
163
+
if (!fail_only || support->g6_temp_read_support == 0)
164
+
dml2_printf("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);
165
+
if (!fail_only || support->ImmediateFlipSupport == 0)
166
+
dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);
167
+
if (!fail_only || support->LinkCapacitySupport == 0)
168
+
dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);
169
+
170
+
if (!fail_only || support->ModeSupport == 0)
171
+
dml2_printf("DML: support: ModeSupport = %d\n", support->ModeSupport);
172
+
dml2_printf("DML: ===================================== \n");
173
+
}
174
+
175
+
const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type)
176
+
{
177
+
switch (dml2_core_internal_soc_state_type) {
178
+
case (dml2_core_internal_soc_state_sys_idle):
179
+
return("dml2_core_internal_soc_state_sys_idle");
180
+
case (dml2_core_internal_soc_state_sys_active):
181
+
return("dml2_core_internal_soc_state_sys_active");
182
+
case (dml2_core_internal_soc_state_svp_prefetch):
183
+
return("dml2_core_internal_soc_state_svp_prefetch");
184
+
case dml2_core_internal_soc_state_max:
185
+
default:
186
+
return("dml2_core_internal_soc_state_unknown");
187
+
}
188
+
}
189
+
190
+
191
+
void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg)
192
+
{
193
+
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
194
+
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
195
+
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
196
+
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
197
+
case dml2_444:
198
+
out_bpp[k] = bpc * 3;
199
+
break;
200
+
case dml2_s422:
201
+
out_bpp[k] = bpc * 2;
202
+
break;
203
+
case dml2_n422:
204
+
out_bpp[k] = bpc * 2;
205
+
break;
206
+
case dml2_420:
207
+
default:
208
+
out_bpp[k] = bpc * 1.5;
209
+
break;
210
+
}
211
+
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
212
+
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
213
+
} else {
214
+
out_bpp[k] = 0;
215
+
}
216
+
#ifdef __DML_VBA_DEBUG__
217
+
dml2_printf("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
218
+
dml2_printf("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
219
+
dml2_printf("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
220
+
#endif
221
+
}
222
+
}
223
+
224
+
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up)
225
+
{
226
+
unsigned int remainder;
227
+
228
+
if (multiple == 0)
229
+
return num;
230
+
231
+
remainder = num % multiple;
232
+
if (remainder == 0)
233
+
return num;
234
+
235
+
if (up)
236
+
return (num + multiple - remainder);
237
+
else
238
+
return (num - remainder);
239
+
}
240
+
241
+
unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info)
242
+
{
243
+
unsigned int num_active_pipes = 0;
244
+
245
+
for (unsigned int k = 0; k < num_planes; k++) {
246
+
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
247
+
}
248
+
249
+
#ifdef __DML_VBA_DEBUG__
250
+
dml2_printf("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes);
251
+
#endif
252
+
return num_active_pipes;
253
+
}
254
+
255
+
void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane)
256
+
{
257
+
unsigned int pipe_idx = 0;
258
+
259
+
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
260
+
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
261
+
}
262
+
263
+
for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) {
264
+
for (int i = 0; i < cfg_support_info->plane_support_info[plane_idx].dpps_used; i++) {
265
+
pipe_plane[pipe_idx] = plane_idx;
266
+
pipe_idx++;
267
+
}
268
+
}
269
+
}
270
+
271
+
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)
272
+
{
273
+
bool is_phantom = false;
274
+
275
+
if (plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe ||
276
+
plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return) {
277
+
is_phantom = true;
278
+
}
279
+
280
+
return is_phantom;
281
+
}
282
+
283
+
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode)
284
+
{
285
+
switch (sw_mode) {
286
+
case (dml2_sw_linear):
287
+
return 256; break;
288
+
case (dml2_sw_256b_2d):
289
+
return 256; break;
290
+
case (dml2_sw_4kb_2d):
291
+
return 4096; break;
292
+
case (dml2_sw_64kb_2d):
293
+
return 65536; break;
294
+
case (dml2_sw_256kb_2d):
295
+
return 262144; break;
296
+
case (dml2_gfx11_sw_linear):
297
+
return 256; break;
298
+
case (dml2_gfx11_sw_64kb_d):
299
+
return 65536; break;
300
+
case (dml2_gfx11_sw_64kb_d_t):
301
+
return 65536; break;
302
+
case (dml2_gfx11_sw_64kb_d_x):
303
+
return 65536; break;
304
+
case (dml2_gfx11_sw_64kb_r_x):
305
+
return 65536; break;
306
+
case (dml2_gfx11_sw_256kb_d_x):
307
+
return 262144; break;
308
+
case (dml2_gfx11_sw_256kb_r_x):
309
+
return 262144; break;
310
+
default:
311
+
DML2_ASSERT(0);
312
+
return 256;
313
+
};
314
+
}
315
+
316
+
317
+
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan)
318
+
{
319
+
bool is_vert = false;
320
+
if (Scan == dml2_rotation_90 || Scan == dml2_rotation_270) {
321
+
is_vert = true;
322
+
} else {
323
+
is_vert = false;
324
+
}
325
+
return is_vert;
326
+
}
327
+
328
+
329
+
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode)
330
+
{
331
+
int unsigned version = 0;
332
+
333
+
if (sw_mode == dml2_sw_linear ||
334
+
sw_mode == dml2_sw_256b_2d ||
335
+
sw_mode == dml2_sw_4kb_2d ||
336
+
sw_mode == dml2_sw_64kb_2d ||
337
+
sw_mode == dml2_sw_256kb_2d) {
338
+
version = 12;
339
+
} else if (sw_mode == dml2_gfx11_sw_linear ||
340
+
sw_mode == dml2_gfx11_sw_64kb_d ||
341
+
sw_mode == dml2_gfx11_sw_64kb_d_t ||
342
+
sw_mode == dml2_gfx11_sw_64kb_d_x ||
343
+
sw_mode == dml2_gfx11_sw_64kb_r_x ||
344
+
sw_mode == dml2_gfx11_sw_256kb_d_x ||
345
+
sw_mode == dml2_gfx11_sw_256kb_r_x) {
346
+
version = 11;
347
+
} else {
348
+
dml2_printf("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode);
349
+
DML2_ASSERT(0);
350
+
}
351
+
352
+
return version;
353
+
}
354
+
355
+
unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params)
356
+
{
357
+
unsigned int i;
358
+
unsigned int index = 0;
359
+
360
+
for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
361
+
dml2_printf("DML::%s: per_uclk_dpm_params[%d].minimum_uclk_khz = %d\n", __func__, i, per_uclk_dpm_params[i].minimum_uclk_khz);
362
+
363
+
if (i == 0)
364
+
index = 0;
365
+
else
366
+
index = i - 1;
367
+
368
+
if (uclk_freq_khz < per_uclk_dpm_params[i].minimum_uclk_khz ||
369
+
per_uclk_dpm_params[i].minimum_uclk_khz == 0) {
370
+
break;
371
+
}
372
+
}
373
+
#if defined(__DML_VBA_DEBUG__)
374
+
dml2_printf("DML::%s: uclk_freq_khz = %d\n", __func__, uclk_freq_khz);
375
+
dml2_printf("DML::%s: index = %d\n", __func__, index);
376
+
#endif
377
+
return index;
378
+
}
379
+
380
+
unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table)
381
+
{
382
+
unsigned int i;
383
+
bool clk_entry_found = 0;
384
+
385
+
for (i = 0; i < clk_table->uclk.num_clk_values; i++) {
386
+
dml2_printf("DML::%s: clk_table.uclk.clk_values_khz[%d] = %d\n", __func__, i, clk_table->uclk.clk_values_khz[i]);
387
+
388
+
if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) {
389
+
clk_entry_found = 1;
390
+
break;
391
+
}
392
+
}
393
+
394
+
dml2_assert(clk_entry_found);
395
+
#if defined(__DML_VBA_DEBUG__)
396
+
dml2_printf("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);
397
+
dml2_printf("DML::%s: index = %d\n", __func__, i);
398
+
#endif
399
+
return i;
400
+
}
401
+
402
+
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format)
403
+
{
404
+
bool ret_val = 0;
405
+
406
+
if ((source_format == dml2_420_12) || (source_format == dml2_420_8) || (source_format == dml2_420_10) || (source_format == dml2_rgbe_alpha))
407
+
ret_val = 1;
408
+
409
+
return ret_val;
410
+
}
411
+
412
+
unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend)
413
+
{
414
+
if (a == 0)
415
+
return 0;
416
+
417
+
return (math_log2_approx(a) - subtrahend);
418
+
}
419
+
420
+
static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,
421
+
const struct dml2_implicit_svp_meta *meta)
422
+
{
423
+
memcpy(phantom, main, sizeof(struct dml2_stream_parameters));
424
+
425
+
phantom->timing.v_total = meta->v_total;
426
+
phantom->timing.v_active = meta->v_active;
427
+
phantom->timing.v_front_porch = meta->v_front_porch;
428
+
phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
429
+
phantom->timing.drr_config.enabled = false;
430
+
}
431
+
432
+
static void create_phantom_plane_from_main_plane(struct dml2_plane_parameters *phantom, const struct dml2_plane_parameters *main,
433
+
const struct dml2_stream_parameters *phantom_stream, int phantom_stream_index, const struct dml2_stream_parameters *main_stream)
434
+
{
435
+
memcpy(phantom, main, sizeof(struct dml2_plane_parameters));
436
+
437
+
phantom->stream_index = phantom_stream_index;
438
+
phantom->overrides.refresh_from_mall = dml2_refresh_from_mall_mode_override_force_disable;
439
+
phantom->overrides.legacy_svp_config = dml2_svp_mode_override_phantom_pipe_no_data_return;
440
+
phantom->composition.viewport.plane0.height = (long int unsigned) math_min2(math_ceil2(
441
+
(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
442
+
(double)main->composition.viewport.plane0.height);
443
+
phantom->composition.viewport.plane1.height = (long int unsigned) math_min2(math_ceil2(
444
+
(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
445
+
(double)main->composition.viewport.plane1.height);
446
+
phantom->immediate_flip = false;
447
+
phantom->dynamic_meta_data.enable = false;
448
+
phantom->cursor.num_cursors = 0;
449
+
phantom->cursor.cursor_width = 0;
450
+
phantom->tdlut.setup_for_tdlut = false;
451
+
}
452
+
453
+
void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,
454
+
struct dml2_core_scratch *scratch)
455
+
{
456
+
unsigned int stream_index, plane_index;
457
+
const struct dml2_plane_parameters *main_plane;
458
+
const struct dml2_stream_parameters *main_stream;
459
+
const struct dml2_stream_parameters *phantom_stream;
460
+
461
+
memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg));
462
+
memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
463
+
memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
464
+
memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);
465
+
466
+
if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo)
467
+
return;
468
+
469
+
/* disable unbounded requesting for all planes until stage 3 has been performed */
470
+
if (!display_cfg->stage3.performed) {
471
+
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;
472
+
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.value = false;
473
+
}
474
+
// Create the phantom streams
475
+
for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) {
476
+
main_stream = &display_cfg->display_config.stream_descriptors[stream_index];
477
+
scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;
478
+
scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;
479
+
480
+
if (display_cfg->stage3.stream_svp_meta[stream_index].valid) {
481
+
// Create the phantom stream
482
+
create_phantom_stream_from_main_stream(&svp_expanded_display_cfg->stream_descriptors[svp_expanded_display_cfg->num_streams],
483
+
main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]);
484
+
485
+
// Associate this phantom stream to the main stream
486
+
scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;
487
+
scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;
488
+
489
+
// Increment num streams
490
+
svp_expanded_display_cfg->num_streams++;
491
+
}
492
+
}
493
+
494
+
// Create the phantom planes
495
+
for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) {
496
+
main_plane = &display_cfg->display_config.plane_descriptors[plane_index];
497
+
498
+
if (display_cfg->stage3.stream_svp_meta[main_plane->stream_index].valid) {
499
+
main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index];
500
+
phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];
501
+
create_phantom_plane_from_main_plane(&svp_expanded_display_cfg->plane_descriptors[svp_expanded_display_cfg->num_planes],
502
+
main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);
503
+
504
+
// Associate this phantom plane to the main plane
505
+
scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;
506
+
scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;
507
+
508
+
// Increment num planes
509
+
svp_expanded_display_cfg->num_planes++;
510
+
511
+
// Adjust the main plane settings
512
+
svp_expanded_display_cfg->plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mode_override_main_pipe;
513
+
}
514
+
}
515
+
}
516
+
517
+
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor)
518
+
{
519
+
switch (stream_descriptor->output.output_encoder) {
520
+
case dml2_dp:
521
+
case dml2_dp2p0:
522
+
case dml2_edp:
523
+
case dml2_hdmi:
524
+
case dml2_hdmifrl:
525
+
return true;
526
+
case dml2_none:
527
+
default:
528
+
return false;
529
+
}
530
+
}
531
+
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor)
532
+
{
533
+
switch (stream_descriptor->output.output_encoder) {
534
+
case dml2_dp:
535
+
case dml2_dp2p0:
536
+
case dml2_edp:
537
+
case dml2_hdmifrl:
538
+
return true;
539
+
case dml2_hdmi:
540
+
case dml2_none:
541
+
default:
542
+
return false;
543
+
}
544
+
}
545
+
546
+
547
+
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
548
+
{
549
+
switch (stream_descriptor->output.output_encoder) {
550
+
case dml2_dp:
551
+
case dml2_edp:
552
+
return true;
553
+
case dml2_dp2p0:
554
+
case dml2_hdmi:
555
+
case dml2_hdmifrl:
556
+
case dml2_none:
557
+
default:
558
+
return false;
559
+
}
560
+
}
561
+
562
+
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
563
+
{
564
+
switch (stream_descriptor->output.output_encoder) {
565
+
case dml2_dp2p0:
566
+
return true;
567
+
case dml2_dp:
568
+
case dml2_edp:
569
+
case dml2_hdmi:
570
+
case dml2_hdmifrl:
571
+
case dml2_none:
572
+
default:
573
+
return false;
574
+
}
575
+
}
576
+
577
+
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
578
+
{
579
+
return dml2_core_utils_is_dio_dp_encoder(stream_descriptor)
580
+
|| dml2_core_utils_is_hpo_dp_encoder(stream_descriptor);
581
+
}
582
+
583
+
584
+
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate)
585
+
{
586
+
switch (rate) {
587
+
case dml2_dp_rate_hbr:
588
+
case dml2_dp_rate_hbr2:
589
+
case dml2_dp_rate_hbr3:
590
+
return true;
591
+
case dml2_dp_rate_na:
592
+
case dml2_dp_rate_uhbr10:
593
+
case dml2_dp_rate_uhbr13p5:
594
+
case dml2_dp_rate_uhbr20:
595
+
default:
596
+
return false;
597
+
}
598
+
}
599
+
600
+
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate)
601
+
{
602
+
switch (rate) {
603
+
case dml2_dp_rate_uhbr10:
604
+
case dml2_dp_rate_uhbr13p5:
605
+
case dml2_dp_rate_uhbr20:
606
+
return true;
607
+
case dml2_dp_rate_hbr:
608
+
case dml2_dp_rate_hbr2:
609
+
case dml2_dp_rate_hbr3:
610
+
case dml2_dp_rate_na:
611
+
default:
612
+
return false;
613
+
}
614
+
}
615
+
616
+
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)
617
+
{
618
+
switch (odm_mode) {
619
+
case dml2_odm_mode_split_1to2:
620
+
case dml2_odm_mode_mso_1to2:
621
+
case dml2_odm_mode_mso_1to4:
622
+
return true;
623
+
case dml2_odm_mode_auto:
624
+
case dml2_odm_mode_bypass:
625
+
case dml2_odm_mode_combine_2to1:
626
+
case dml2_odm_mode_combine_3to1:
627
+
case dml2_odm_mode_combine_4to1:
628
+
default:
629
+
return false;
630
+
}
631
+
}
+39
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
+39
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h
···
1
+
// SPDX-License-Identifier: MIT
2
+
//
3
+
// Copyright 2024 Advanced Micro Devices, Inc.
4
+
5
+
#ifndef __DML2_CORE_UTILS_H__
6
+
#define __DML2_CORE_UTILS_H__
7
+
#include "dml2_internal_shared_types.h"
8
+
#include "dml2_debug.h"
9
+
#include "lib_float_math.h"
10
+
11
+
double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder);
12
+
const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type);
13
+
bool dml2_core_utils_is_420(enum dml2_source_format_class source_format);
14
+
void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only);
15
+
const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type);
16
+
void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
17
+
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up);
18
+
unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info);
19
+
void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
20
+
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg);
21
+
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode);
22
+
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan);
23
+
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode);
24
+
unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params);
25
+
unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table);
26
+
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format);
27
+
unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend);
28
+
void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,
29
+
struct dml2_core_scratch *scratch);
30
+
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor);
31
+
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor);
32
+
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
33
+
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
34
+
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
35
+
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate);
36
+
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate);
37
+
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);
38
+
39
+
#endif /* __DML2_CORE_UTILS_H__ */
+41
-13
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
+41
-13
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
···
203
203
return true;
204
204
}
205
205
206
+
static bool round_to_non_dfs_granularity(unsigned long dispclk_khz, unsigned long dpprefclk_khz, unsigned long dtbrefclk_khz,
207
+
unsigned long *rounded_dispclk_khz, unsigned long *rounded_dpprefclk_khz, unsigned long *rounded_dtbrefclk_khz)
208
+
{
209
+
unsigned long pll_frequency_khz;
210
+
211
+
pll_frequency_khz = (unsigned long) math_max2(600000, math_ceil2(math_max3(dispclk_khz, dpprefclk_khz, dtbrefclk_khz), 1000));
212
+
213
+
*rounded_dispclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dispclk_khz, 32);
214
+
215
+
*rounded_dpprefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dpprefclk_khz, 32);
216
+
217
+
if (dtbrefclk_khz > 0) {
218
+
*rounded_dtbrefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dtbrefclk_khz, 32);
219
+
} else {
220
+
*rounded_dtbrefclk_khz = 0;
221
+
}
222
+
223
+
return true;
224
+
}
225
+
206
226
static bool round_up_and_copy_to_next_dpm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table)
207
227
{
208
228
bool result = false;
···
575
555
// but still the required dispclk can be more than the maximum dispclk speed:
576
556
dispclk_khz = math_max2(dispclk_khz, mode_support_result->global.dispclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
577
557
578
-
add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0,
579
-
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did);
580
-
581
558
// DPP Ref is always set to max of all DPP clocks
582
559
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
583
560
if (in_out->programming->min_clocks.dcn4x.dpprefclk_khz < mode_support_result->per_plane[i].dppclk_khz)
584
561
in_out->programming->min_clocks.dcn4x.dpprefclk_khz = mode_support_result->per_plane[i].dppclk_khz;
585
562
}
586
-
587
-
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0,
588
-
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did);
589
-
590
-
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
591
-
in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0
592
-
* math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0));
593
-
}
563
+
in_out->programming->min_clocks.dcn4x.dpprefclk_khz = (unsigned long) (in_out->programming->min_clocks.dcn4x.dpprefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
594
564
595
565
// DTB Ref is always set to max of all DTB clocks
596
566
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
597
567
if (in_out->programming->min_clocks.dcn4x.dtbrefclk_khz < mode_support_result->per_stream[i].dtbclk_khz)
598
568
in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = mode_support_result->per_stream[i].dtbclk_khz;
599
569
}
570
+
in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
600
571
601
-
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0,
602
-
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did);
572
+
if (in_out->soc_bb->no_dfs) {
573
+
round_to_non_dfs_granularity((unsigned long)dispclk_khz, in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->programming->min_clocks.dcn4x.dtbrefclk_khz,
574
+
&in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz);
575
+
} else {
576
+
add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0,
577
+
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did);
578
+
579
+
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 0.0,
580
+
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did);
581
+
582
+
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, 0.0,
583
+
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did);
584
+
}
585
+
586
+
587
+
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
588
+
in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0
589
+
* math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0));
590
+
}
603
591
604
592
in_out->programming->min_clocks.dcn4x.deepsleep_dcfclk_khz = mode_support_result->global.dcfclk_deepsleep_khz;
605
593
in_out->programming->min_clocks.dcn4x.socclk_khz = mode_support_result->global.socclk_khz;
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
+1
-1
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
+12
-8
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+12
-8
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
···
718
718
const struct dml2_core_mode_support_result *mode_support_result =
719
719
&in_out->base_display_config->mode_support_result;
720
720
struct dml2_optimization_stage4_state *state =
721
-
&in_out->base_display_config->stage4;
721
+
&in_out->base_display_config->stage4;
722
722
723
723
if (in_out->instance->options->disable_dyn_odm ||
724
724
(in_out->instance->options->disable_dyn_odm_for_multi_stream && display_config->num_streams > 1))
···
1444
1444
/* DRR variable strategies are disallowed due to settings or policy */
1445
1445
strategy_matches_drr_requirements = false;
1446
1446
} else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_method) &&
1447
-
(pmo->options->disable_drr_clamped ||
1447
+
(pmo->options->disable_drr_clamped ||
1448
1448
(!stream_descriptor->timing.drr_config.enabled ||
1449
1449
(!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) ||
1450
1450
(pmo->options->disable_drr_clamped_when_var_active &&
···
1910
1910
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
1911
1911
plane = &display_config->display_config.plane_descriptors[plane_index];
1912
1912
1913
-
plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000);
1913
+
plane->overrides.reserved_vblank_time_ns = (long)math_max2(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000.0,
1914
+
plane->overrides.reserved_vblank_time_ns);
1914
1915
1915
1916
display_config->stage3.pstate_switch_modes[plane_index] = dml2_uclk_pstate_support_method_vblank;
1916
1917
···
2197
2196
2198
2197
unsigned int i;
2199
2198
2200
-
for (i = 0; i < in_out->base_display_config->display_config.num_streams; i++) {
2199
+
for (i = 0; i < in_out->base_display_config->display_config.num_planes; i++) {
2201
2200
if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 &&
2202
2201
pmo->scratch.pmo_dcn4.z8_vblank_optimizable &&
2203
-
in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) {
2202
+
in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * 1000) {
2204
2203
success = false;
2205
2204
break;
2206
2205
}
2207
2206
if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0 &&
2208
-
in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us) {
2207
+
in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * 1000) {
2209
2208
success = false;
2210
2209
break;
2211
2210
}
···
2224
2223
2225
2224
if (!in_out->last_candidate_failed) {
2226
2225
if (pmo->scratch.pmo_dcn4.cur_stutter_candidate < pmo->scratch.pmo_dcn4.num_stutter_candidates) {
2227
-
for (i = 0; i < in_out->optimized_display_config->display_config.num_streams; i++) {
2228
-
in_out->optimized_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us = pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate];
2226
+
for (i = 0; i < in_out->optimized_display_config->display_config.num_planes; i++) {
2227
+
/* take the max of the current and the optimal reserved time */
2228
+
in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns =
2229
+
(long)math_max2(pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate] * 1000,
2230
+
in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns);
2229
2231
}
2230
2232
2231
2233
success = true;