tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu/mes: add multi-xcc support

a. extend mes pipe instances to num_xcc * max_mes_pipe
b. initialize mes schq/kiq pipes per xcc
c. submit mes packet to mes ring according to xcc_id

v2: rebase (Alex)

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jack Xiao and committed by
Alex Deucher d09c7e26 2718942f

+158 -108
+8 -6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 511 511 j = i + xcc_id * adev->gfx.num_compute_rings; 512 512 amdgpu_mes_unmap_legacy_queue(adev, 513 513 &adev->gfx.compute_ring[j], 514 - RESET_QUEUES, 0, 0); 514 + RESET_QUEUES, 0, 0, xcc_id); 515 515 } 516 516 return 0; 517 517 } ··· 562 562 j = i + xcc_id * adev->gfx.num_gfx_rings; 563 563 amdgpu_mes_unmap_legacy_queue(adev, 564 564 &adev->gfx.gfx_ring[j], 565 - PREEMPT_QUEUES, 0, 0); 565 + PREEMPT_QUEUES, 0, 0, xcc_id); 566 566 } 567 567 } 568 568 return 0; ··· 644 644 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 645 645 j = i + xcc_id * adev->gfx.num_compute_rings; 646 646 r = amdgpu_mes_map_legacy_queue(adev, 647 - &adev->gfx.compute_ring[j]); 647 + &adev->gfx.compute_ring[j], 648 + xcc_id); 648 649 if (r) { 649 650 dev_err(adev->dev, "failed to map compute queue\n"); 650 651 return r; ··· 734 733 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 735 734 j = i + xcc_id * adev->gfx.num_gfx_rings; 736 735 r = amdgpu_mes_map_legacy_queue(adev, 737 - &adev->gfx.gfx_ring[j]); 736 + &adev->gfx.gfx_ring[j], 737 + xcc_id); 738 738 if (r) { 739 739 dev_err(adev->dev, "failed to map gfx queue\n"); 740 740 return r; ··· 1069 1067 return 0; 1070 1068 1071 1069 if (adev->mes.ring[0].sched.ready) 1072 - return amdgpu_mes_rreg(adev, reg); 1070 + return amdgpu_mes_rreg(adev, reg, xcc_id); 1073 1071 1074 1072 BUG_ON(!ring->funcs->emit_rreg); 1075 1073 ··· 1145 1143 return; 1146 1144 1147 1145 if (adev->mes.ring[0].sched.ready) { 1148 - amdgpu_mes_wreg(adev, reg, v); 1146 + amdgpu_mes_wreg(adev, reg, v, xcc_id); 1149 1147 return; 1150 1148 } 1151 1149
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
··· 813 813 814 814 if (adev->mes.ring[0].sched.ready) { 815 815 amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, 816 - ref, mask); 816 + ref, mask, xcc_inst); 817 817 return; 818 818 } 819 819
+53 -33
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
··· 91 91 int amdgpu_mes_init(struct amdgpu_device *adev) 92 92 { 93 93 int i, r, num_pipes; 94 + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 94 95 95 96 adev->mes.adev = adev; 96 97 ··· 102 101 spin_lock_init(&adev->mes.queue_id_lock); 103 102 mutex_init(&adev->mes.mutex_hidden); 104 103 105 - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) 104 + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) 106 105 spin_lock_init(&adev->mes.ring_lock[i]); 107 106 108 107 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; ··· 157 156 adev->mes.sdma_hqd_mask[i] = 0xfc; 158 157 } 159 158 160 - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { 159 + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 161 160 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]); 162 161 if (r) { 163 162 dev_err(adev->dev, ··· 193 192 goto error_doorbell; 194 193 195 194 if (adev->mes.hung_queue_db_array_size) { 196 - r = amdgpu_bo_create_kernel(adev, 197 - adev->mes.hung_queue_db_array_size * sizeof(u32), 198 - PAGE_SIZE, 199 - AMDGPU_GEM_DOMAIN_GTT, 200 - &adev->mes.hung_queue_db_array_gpu_obj, 201 - &adev->mes.hung_queue_db_array_gpu_addr, 202 - &adev->mes.hung_queue_db_array_cpu_addr); 203 - if (r) { 204 - dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); 205 - goto error_doorbell; 195 + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 196 + r = amdgpu_bo_create_kernel(adev, 197 + adev->mes.hung_queue_db_array_size * sizeof(u32), 198 + PAGE_SIZE, 199 + AMDGPU_GEM_DOMAIN_GTT, 200 + &adev->mes.hung_queue_db_array_gpu_obj[i], 201 + &adev->mes.hung_queue_db_array_gpu_addr[i], 202 + &adev->mes.hung_queue_db_array_cpu_addr[i]); 203 + if (r) { 204 + dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); 205 + goto error_doorbell; 206 + } 206 207 } 207 208 } 208 209 ··· 213 210 error_doorbell: 214 211 amdgpu_mes_doorbell_free(adev); 215 212 error: 216 - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { 213 + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 217 214 if (adev->mes.sch_ctx_ptr[i]) 218 215 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); 219 216 if (adev->mes.query_status_fence_ptr[i]) 220 217 amdgpu_device_wb_free(adev, 221 218 adev->mes.query_status_fence_offs[i]); 219 + if (adev->mes.hung_queue_db_array_gpu_obj[i]) 220 + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], 221 + &adev->mes.hung_queue_db_array_gpu_addr[i], 222 + &adev->mes.hung_queue_db_array_cpu_addr[i]); 222 223 } 223 224 224 225 idr_destroy(&adev->mes.pasid_idr); ··· 235 228 236 229 void amdgpu_mes_fini(struct amdgpu_device *adev) 237 230 { 238 - int i; 239 - 240 - amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj, 241 - &adev->mes.hung_queue_db_array_gpu_addr, 242 - &adev->mes.hung_queue_db_array_cpu_addr); 231 + int i, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 243 232 244 233 amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, 245 234 &adev->mes.event_log_gpu_addr, 246 235 &adev->mes.event_log_cpu_addr); 247 236 248 - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { 237 + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { 238 + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], 239 + &adev->mes.hung_queue_db_array_gpu_addr[i], 240 + &adev->mes.hung_queue_db_array_cpu_addr[i]); 241 + 249 242 if (adev->mes.sch_ctx_ptr[i]) 250 243 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); 251 244 if (adev->mes.query_status_fence_ptr[i]) ··· 311 304 } 312 305 313 306 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 314 - struct amdgpu_ring *ring) 307 + struct amdgpu_ring *ring, uint32_t xcc_id) 315 308 { 316 309 struct mes_map_legacy_queue_input queue_input; 317 310 int r; 318 311 319 312 memset(&queue_input, 0, sizeof(queue_input)); 320 313 314 + queue_input.xcc_id = xcc_id; 321 315 queue_input.queue_type = ring->funcs->type; 322 316 queue_input.doorbell_offset = ring->doorbell_index; 323 317 queue_input.pipe_id = ring->pipe; ··· 338 330 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 339 331 struct amdgpu_ring *ring, 340 332 enum amdgpu_unmap_queues_action action, 341 - u64 gpu_addr, u64 seq) 333 + u64 gpu_addr, u64 seq, uint32_t xcc_id) 342 334 { 343 335 struct mes_unmap_legacy_queue_input queue_input; 344 336 int r; 345 337 338 + queue_input.xcc_id = xcc_id; 346 339 queue_input.action = action; 347 340 queue_input.queue_type = ring->funcs->type; 348 341 queue_input.doorbell_offset = ring->doorbell_index; ··· 364 355 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 365 356 struct amdgpu_ring *ring, 366 357 unsigned int vmid, 367 - bool use_mmio) 358 + bool use_mmio, 359 + uint32_t xcc_id) 368 360 { 369 361 struct mes_reset_queue_input queue_input; 370 362 int r; 371 363 372 364 memset(&queue_input, 0, sizeof(queue_input)); 373 365 366 + queue_input.xcc_id = xcc_id; 374 367 queue_input.queue_type = ring->funcs->type; 375 368 queue_input.doorbell_offset = ring->doorbell_index; 376 369 queue_input.me_id = ring->me; ··· 404 393 int queue_type, 405 394 bool detect_only, 406 395 unsigned int *hung_db_num, 407 - u32 *hung_db_array) 408 - 396 + u32 *hung_db_array, 397 + uint32_t xcc_id) 409 398 { 410 399 struct mes_detect_and_reset_queue_input input; 411 - u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr; 400 + u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; 412 401 int r, i; 413 402 414 403 if (!hung_db_num || !hung_db_array) ··· 420 409 return -EINVAL; 421 410 422 411 /* Clear the doorbell array before detection */ 423 - memset(adev->mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET, 412 + memset(adev->mes.hung_queue_db_array_cpu_addr[xcc_id], AMDGPU_MES_INVALID_DB_OFFSET, 424 413 adev->mes.hung_queue_db_array_size * sizeof(u32)); 425 414 input.queue_type = queue_type; 426 415 input.detect_only = detect_only; ··· 447 436 return r; 448 437 } 449 438 450 - uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) 439 + uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 440 + uint32_t xcc_id) 451 441 { 452 442 struct mes_misc_op_input op_input; 453 443 int r, val = 0; ··· 462 450 } 463 451 read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4); 464 452 read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset]; 453 + op_input.xcc_id = xcc_id; 465 454 op_input.op = MES_MISC_OP_READ_REG; 466 455 op_input.read_reg.reg_offset = reg; 467 456 op_input.read_reg.buffer_addr = read_val_gpu_addr; ··· 486 473 return val; 487 474 } 488 475 489 - int amdgpu_mes_wreg(struct amdgpu_device *adev, 490 - uint32_t reg, uint32_t val) 476 + int amdgpu_mes_wreg(struct amdgpu_device *adev, uint32_t reg, 477 + uint32_t val, uint32_t xcc_id) 491 478 { 492 479 struct mes_misc_op_input op_input; 493 480 int r; 494 481 482 + op_input.xcc_id = xcc_id; 495 483 op_input.op = MES_MISC_OP_WRITE_REG; 496 484 op_input.write_reg.reg_offset = reg; 497 485 op_input.write_reg.reg_value = val; ··· 515 501 516 502 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 517 503 uint32_t reg0, uint32_t reg1, 518 - uint32_t ref, uint32_t mask) 504 + uint32_t ref, uint32_t mask, 505 + uint32_t xcc_id) 519 506 { 520 507 struct mes_misc_op_input op_input; 521 508 int r; 522 509 510 + op_input.xcc_id = xcc_id; 523 511 op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; 524 512 op_input.wrm_reg.reg0 = reg0; 525 513 op_input.wrm_reg.reg1 = reg1; ··· 553 537 ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; 554 538 555 539 return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset, 556 - ref_and_mask, ref_and_mask); 540 + ref_and_mask, ref_and_mask, 0); 557 541 } 558 542 559 543 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, ··· 561 545 uint32_t spi_gdbg_per_vmid_cntl, 562 546 const uint32_t *tcp_watch_cntl, 563 547 uint32_t flags, 564 - bool trap_en) 548 + bool trap_en, 549 + uint32_t xcc_id) 565 550 { 566 551 struct mes_misc_op_input op_input = {0}; 567 552 int r; ··· 573 556 return -EINVAL; 574 557 } 575 558 559 + op_input.xcc_id = xcc_id; 576 560 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; 577 561 op_input.set_shader_debugger.process_context_addr = process_context_addr; 578 562 op_input.set_shader_debugger.flags.u32all = flags; ··· 602 584 } 603 585 604 586 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 605 - uint64_t process_context_addr) 587 + uint64_t process_context_addr, 588 + uint32_t xcc_id) 606 589 { 607 590 struct mes_misc_op_input op_input = {0}; 608 591 int r; ··· 614 595 return -EINVAL; 615 596 } 616 597 598 + op_input.xcc_id = xcc_id; 617 599 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; 618 600 op_input.set_shader_debugger.process_context_addr = process_context_addr; 619 601 op_input.set_shader_debugger.flags.process_ctx_flush = true;
+63 -37
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
··· 58 58 struct amdgpu_mes_funcs; 59 59 60 60 enum amdgpu_mes_pipe { 61 - AMDGPU_MES_SCHED_PIPE = 0, 62 - AMDGPU_MES_KIQ_PIPE, 61 + AMDGPU_MES_PIPE_0 = 0, 62 + AMDGPU_MES_PIPE_1, 63 63 AMDGPU_MAX_MES_PIPES = 2, 64 64 }; 65 + 66 + #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 + #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 + 69 + #define AMDGPU_MAX_MES_INST_PIPES \ 70 + (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 + 72 + #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 + (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 65 74 66 75 struct amdgpu_mes { 67 76 struct amdgpu_device *adev; ··· 95 86 uint64_t default_process_quantum; 96 87 uint64_t default_gang_quantum; 97 88 98 - struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 99 - spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 89 + struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 90 + spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 100 91 101 92 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 102 93 103 94 /* mes ucode */ 104 - struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 105 - uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 106 - uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 95 + struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 96 + uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 97 + uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 107 98 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 108 99 109 100 /* mes ucode data */ 110 - struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 111 - uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 112 - uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 101 + struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 102 + uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 103 + uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 113 104 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 114 105 115 106 /* eop gpu obj */ 116 - struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 117 - uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 107 + struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 108 + uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 118 109 119 - void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 120 - struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 110 + void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 111 + struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 121 112 122 113 uint32_t vmid_mask_gfxhub; 123 114 uint32_t vmid_mask_mmhub; ··· 125 116 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 126 117 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 127 118 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 128 - uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 129 - uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 130 - uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 131 - uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 132 - uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 133 - uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 119 + 120 + uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 121 + uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 122 + uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 123 + uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 124 + uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 125 + uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 134 126 135 127 uint32_t saved_flags; 136 128 137 129 /* initialize kiq pipe */ 138 - int (*kiq_hw_init)(struct amdgpu_device *adev); 139 - int (*kiq_hw_fini)(struct amdgpu_device *adev); 130 + int (*kiq_hw_init)(struct amdgpu_device *adev, 131 + uint32_t xcc_id); 132 + int (*kiq_hw_fini)(struct amdgpu_device *adev, 133 + uint32_t xcc_id); 140 134 141 135 /* MES doorbells */ 142 136 uint32_t db_start_dw_offset; ··· 162 150 163 151 int hung_queue_db_array_size; 164 152 int hung_queue_hqd_info_offset; 165 - struct amdgpu_bo *hung_queue_db_array_gpu_obj; 166 - uint64_t hung_queue_db_array_gpu_addr; 167 - void *hung_queue_db_array_cpu_addr; 153 + struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES]; 154 + uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES]; 155 + void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES]; 168 156 }; 169 157 170 158 struct amdgpu_mes_gang { ··· 220 208 }; 221 209 222 210 struct mes_add_queue_input { 211 + uint32_t xcc_id; 223 212 uint32_t process_id; 224 213 uint64_t page_table_base_addr; 225 214 uint64_t process_va_start; ··· 250 237 }; 251 238 252 239 struct mes_remove_queue_input { 240 + uint32_t xcc_id; 253 241 uint32_t doorbell_offset; 254 242 uint64_t gang_context_addr; 255 243 bool remove_queue_after_reset; 256 244 }; 257 245 258 246 struct mes_map_legacy_queue_input { 247 + uint32_t xcc_id; 259 248 uint32_t queue_type; 260 249 uint32_t doorbell_offset; 261 250 uint32_t pipe_id; ··· 267 252 }; 268 253 269 254 struct mes_unmap_legacy_queue_input { 255 + uint32_t xcc_id; 270 256 enum amdgpu_unmap_queues_action action; 271 257 uint32_t queue_type; 272 258 uint32_t doorbell_offset; ··· 278 262 }; 279 263 280 264 struct mes_suspend_gang_input { 265 + uint32_t xcc_id; 281 266 bool suspend_all_gangs; 282 267 uint64_t gang_context_addr; 283 268 uint64_t suspend_fence_addr; ··· 286 269 }; 287 270 288 271 struct mes_resume_gang_input { 272 + uint32_t xcc_id; 289 273 bool resume_all_gangs; 290 274 uint64_t gang_context_addr; 291 275 }; 292 276 293 277 struct mes_reset_queue_input { 278 + uint32_t xcc_id; 294 279 uint32_t queue_type; 295 280 uint32_t doorbell_offset; 296 281 bool use_mmio; ··· 328 309 }; 329 310 330 311 struct mes_misc_op_input { 331 - enum mes_misc_opcode op; 312 + uint32_t xcc_id; 313 + enum mes_misc_opcode op; 332 314 333 315 union { 334 316 struct { ··· 415 395 struct mes_inv_tlbs_pasid_input *input); 416 396 }; 417 397 418 - #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 419 - #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 398 + #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 399 + (adev)->mes.kiq_hw_init((adev), (xcc_id)) 400 + #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 401 + (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 420 402 421 403 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 422 404 int amdgpu_mes_init(struct amdgpu_device *adev); ··· 428 406 int amdgpu_mes_resume(struct amdgpu_device *adev); 429 407 430 408 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 431 - struct amdgpu_ring *ring); 409 + struct amdgpu_ring *ring, uint32_t xcc_id); 432 410 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 433 411 struct amdgpu_ring *ring, 434 412 enum amdgpu_unmap_queues_action action, 435 - u64 gpu_addr, u64 seq); 413 + u64 gpu_addr, u64 seq, uint32_t xcc_id); 436 414 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 437 415 struct amdgpu_ring *ring, 438 416 unsigned int vmid, 439 - bool use_mmio); 417 + bool use_mmio, 418 + uint32_t xcc_id); 440 419 441 420 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 442 421 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 443 422 int queue_type, 444 423 bool detect_only, 445 424 unsigned int *hung_db_num, 446 - u32 *hung_db_array); 425 + u32 *hung_db_array, 426 + uint32_t xcc_id); 447 427 448 - uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 428 + uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 429 + uint32_t xcc_id); 449 430 int amdgpu_mes_wreg(struct amdgpu_device *adev, 450 - uint32_t reg, uint32_t val); 431 + uint32_t reg, uint32_t val, uint32_t xcc_id); 451 432 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 452 433 uint32_t reg0, uint32_t reg1, 453 - uint32_t ref, uint32_t mask); 434 + uint32_t ref, uint32_t mask, uint32_t xcc_id); 454 435 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 455 436 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 456 437 uint64_t process_context_addr, 457 438 uint32_t spi_gdbg_per_vmid_cntl, 458 439 const uint32_t *tcp_watch_cntl, 459 440 uint32_t flags, 460 - bool trap_en); 441 + bool trap_en, 442 + uint32_t xcc_id); 461 443 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 462 - uint64_t process_context_addr); 444 + uint64_t process_context_addr, uint32_t xcc_id); 463 445 464 446 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 465 447 enum amdgpu_mes_priority_level prio);
+8 -7
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 416 416 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 417 417 418 418 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 419 - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 419 + amdgpu_mes_unmap_legacy_queue(adev, ring, action, 420 + gpu_addr, seq, 0); 420 421 return; 421 422 } 422 423 ··· 4594 4593 } 4595 4594 4596 4595 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 4597 - r = amdgpu_mes_kiq_hw_init(adev); 4596 + r = amdgpu_mes_kiq_hw_init(adev, 0); 4598 4597 else 4599 4598 r = gfx_v11_0_kiq_resume(adev); 4600 4599 if (r) ··· 4902 4901 if (amdgpu_gfx_disable_kcq(adev, 0)) 4903 4902 DRM_ERROR("KCQ disable failed\n"); 4904 4903 4905 - amdgpu_mes_kiq_hw_fini(adev); 4904 + amdgpu_mes_kiq_hw_fini(adev, 0); 4906 4905 } 4907 4906 4908 4907 if (amdgpu_sriov_vf(adev)) ··· 6828 6827 6829 6828 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6830 6829 6831 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 6830 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); 6832 6831 if (r) { 6833 6832 6834 6833 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); ··· 6843 6842 return r; 6844 6843 } 6845 6844 6846 - r = amdgpu_mes_map_legacy_queue(adev, ring); 6845 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 6847 6846 if (r) { 6848 6847 dev_err(adev->dev, "failed to remap kgq\n"); 6849 6848 return r; ··· 6991 6990 6992 6991 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 6993 6992 6994 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 6993 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); 6995 6994 if (r) { 6996 6995 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 6997 6996 r = gfx_v11_0_reset_compute_pipe(ring); ··· 7004 7003 dev_err(adev->dev, "fail to init kcq\n"); 7005 7004 return r; 7006 7005 } 7007 - r = amdgpu_mes_map_legacy_queue(adev, ring); 7006 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 7008 7007 if (r) { 7009 7008 dev_err(adev->dev, "failed to remap kcq\n"); 7010 7009 return r;
+8 -7
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 356 356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 357 357 358 358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { 359 - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 359 + amdgpu_mes_unmap_legacy_queue(adev, ring, action, 360 + gpu_addr, seq, 0); 360 361 return; 361 362 } 362 363 ··· 3471 3470 } 3472 3471 3473 3472 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 3474 - r = amdgpu_mes_kiq_hw_init(adev); 3473 + r = amdgpu_mes_kiq_hw_init(adev, 0); 3475 3474 else 3476 3475 r = gfx_v12_0_kiq_resume(adev); 3477 3476 if (r) ··· 3760 3759 if (amdgpu_gfx_disable_kcq(adev, 0)) 3761 3760 DRM_ERROR("KCQ disable failed\n"); 3762 3761 3763 - amdgpu_mes_kiq_hw_fini(adev); 3762 + amdgpu_mes_kiq_hw_fini(adev, 0); 3764 3763 } 3765 3764 3766 3765 if (amdgpu_sriov_vf(adev)) { ··· 5313 5312 5314 5313 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5315 5314 5316 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); 5315 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false, 0); 5317 5316 if (r) { 5318 5317 dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); 5319 5318 r = gfx_v12_reset_gfx_pipe(ring); ··· 5327 5326 return r; 5328 5327 } 5329 5328 5330 - r = amdgpu_mes_map_legacy_queue(adev, ring); 5329 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5331 5330 if (r) { 5332 5331 dev_err(adev->dev, "failed to remap kgq\n"); 5333 5332 return r; ··· 5428 5427 5429 5428 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 5430 5429 5431 - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); 5430 + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); 5432 5431 if (r) { 5433 5432 dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); 5434 5433 r = gfx_v12_0_reset_compute_pipe(ring); ··· 5441 5440 dev_err(adev->dev, "failed to init kcq\n"); 5442 5441 return r; 5443 5442 } 5444 - r = amdgpu_mes_map_legacy_queue(adev, ring); 5443 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 5445 5444 if (r) { 5446 5445 dev_err(adev->dev, "failed to remap kcq\n"); 5447 5446 return r;
+1 -1
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
··· 223 223 224 224 amdgpu_mes_lock(&adev->mes); 225 225 r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, 226 - &hung_db_num, db_array); 226 + &hung_db_num, db_array, 0); 227 227 amdgpu_mes_unlock(&adev->mes); 228 228 if (r) { 229 229 dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r);
+5 -5
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
··· 59 59 60 60 static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); 61 61 static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); 62 - static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 63 - static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 62 + static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 63 + static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 64 64 65 65 #define MES_EOP_SIZE 2048 66 66 #define GFX_MES_DRAM_SIZE 0x80000 ··· 811 811 mes_reset_queue_pkt.queue_type = 812 812 convert_to_mes_queue_type(input->queue_type); 813 813 mes_reset_queue_pkt.doorbell_offset_addr = 814 - mes->hung_queue_db_array_gpu_addr; 814 + mes->hung_queue_db_array_gpu_addr[0]; 815 815 816 816 if (input->detect_only) 817 817 mes_reset_queue_pkt.hang_detect_only = 1; ··· 1570 1570 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1571 1571 } 1572 1572 1573 - static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1573 + static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1574 1574 { 1575 1575 int r = 0; 1576 1576 struct amdgpu_ip_block *ip_block; ··· 1625 1625 return r; 1626 1626 } 1627 1627 1628 - static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1628 + static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1629 1629 { 1630 1630 if (adev->mes.ring[0].sched.ready) { 1631 1631 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]);
+7 -7
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
··· 42 42 43 43 static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); 44 44 static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); 45 - static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); 46 - static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); 45 + static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); 46 + static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); 47 47 48 48 #define MES_EOP_SIZE 2048 49 49 ··· 939 939 mes_reset_queue_pkt.queue_type = 940 940 convert_to_mes_queue_type(input->queue_type); 941 941 mes_reset_queue_pkt.doorbell_offset_addr = 942 - mes->hung_queue_db_array_gpu_addr; 942 + mes->hung_queue_db_array_gpu_addr[0]; 943 943 944 944 if (input->detect_only) 945 945 mes_reset_queue_pkt.hang_detect_only = 1; ··· 1489 1489 1490 1490 if (pipe == AMDGPU_MES_SCHED_PIPE) { 1491 1491 if (adev->enable_uni_mes) 1492 - r = amdgpu_mes_map_legacy_queue(adev, ring); 1492 + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); 1493 1493 else 1494 1494 r = mes_v12_0_kiq_enable_queue(adev); 1495 1495 if (r) ··· 1739 1739 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); 1740 1740 } 1741 1741 1742 - static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) 1742 + static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) 1743 1743 { 1744 1744 int r = 0; 1745 1745 struct amdgpu_ip_block *ip_block; ··· 1801 1801 return r; 1802 1802 } 1803 1803 1804 - static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) 1804 + static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) 1805 1805 { 1806 1806 if (adev->mes.ring[0].sched.ready) { 1807 1807 if (adev->enable_uni_mes) 1808 1808 amdgpu_mes_unmap_legacy_queue(adev, 1809 1809 &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], 1810 - RESET_QUEUES, 0, 0); 1810 + RESET_QUEUES, 0, 0, 0); 1811 1811 else 1812 1812 mes_v12_0_kiq_dequeue_sched(adev); 1813 1813
+1 -1
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
··· 1586 1586 1587 1587 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1588 1588 1589 - r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 1589 + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); 1590 1590 if (r) 1591 1591 return r; 1592 1592
+1 -1
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
··· 816 816 817 817 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 818 818 819 - r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); 819 + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); 820 820 if (r) 821 821 return r; 822 822
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_debug.c
··· 372 372 } 373 373 374 374 return amdgpu_mes_set_shader_debugger(pdd->dev->adev, pdd->proc_ctx_gpu_addr, spi_dbg_cntl, 375 - pdd->watch_points, flags, sq_trap_en); 375 + pdd->watch_points, flags, sq_trap_en, 0); 376 376 } 377 377 378 378 #define KFD_DEBUGGER_INVALID_WATCH_POINT_ID -1
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
··· 94 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 - pdd->proc_ctx_gpu_addr); 97 + pdd->proc_ctx_gpu_addr, 0); 98 98 up_read(&dev->adev->reset_domain->sem); 99 99 } 100 100 pdd->already_dequeued = true;