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Merge branch 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm

* 'fixes' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm:
ARM: 7088/1: entry: fix wrong parameter name used in do_thumb_abort
ARM: 7080/1: l2x0: make sure I&D are not locked down on init
ARM: 7081/1: mach-integrator: fix the clocksource
NET: am79c961: fix race in link status code
ARM: 7067/1: mm: keep significant bits in pfn_valid

+36 -7
+7 -2
arch/arm/include/asm/hardware/cache-l2x0.h
··· 45 45 #define L2X0_CLEAN_INV_LINE_PA 0x7F0 46 46 #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 47 47 #define L2X0_CLEAN_INV_WAY 0x7FC 48 - #define L2X0_LOCKDOWN_WAY_D 0x900 49 - #define L2X0_LOCKDOWN_WAY_I 0x904 48 + /* 49 + * The lockdown registers repeat 8 times for L310, the L210 has only one 50 + * D and one I lockdown register at 0x0900 and 0x0904. 51 + */ 52 + #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 53 + #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 54 + #define L2X0_LOCKDOWN_STRIDE 0x08 50 55 #define L2X0_TEST_OPERATION 0xF00 51 56 #define L2X0_LINE_DATA 0xF10 52 57 #define L2X0_LINE_TAG 0xF30
+3 -3
arch/arm/mach-integrator/integrator_ap.c
··· 337 337 static void integrator_clocksource_init(u32 khz) 338 338 { 339 339 void __iomem *base = (void __iomem *)TIMER2_VA_BASE; 340 - u32 ctrl = TIMER_CTRL_ENABLE; 340 + u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; 341 341 342 342 if (khz >= 1500) { 343 343 khz /= 16; 344 - ctrl = TIMER_CTRL_DIV16; 344 + ctrl |= TIMER_CTRL_DIV16; 345 345 } 346 346 347 - writel(ctrl, base + TIMER_CTRL); 348 347 writel(0xffff, base + TIMER_LOAD); 348 + writel(ctrl, base + TIMER_CTRL); 349 349 350 350 clocksource_mmio_init(base + TIMER_VALUE, "timer2", 351 351 khz * 1000, 200, 16, clocksource_mmio_readl_down);
+1 -1
arch/arm/mm/abort-macro.S
··· 17 17 cmp \tmp, # 0x5600 @ Is it ldrsb? 18 18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes 19 19 tst \tmp, #1 << 11 @ L = 0 -> write 20 - orreq \psr, \psr, #1 << 11 @ yes. 20 + orreq \fsr, \fsr, #1 << 11 @ yes. 21 21 b do_DataAbort 22 22 not_thumb: 23 23 .endm
+21
arch/arm/mm/cache-l2x0.c
··· 277 277 spin_unlock_irqrestore(&l2x0_lock, flags); 278 278 } 279 279 280 + static void __init l2x0_unlock(__u32 cache_id) 281 + { 282 + int lockregs; 283 + int i; 284 + 285 + if (cache_id == L2X0_CACHE_ID_PART_L310) 286 + lockregs = 8; 287 + else 288 + /* L210 and unknown types */ 289 + lockregs = 1; 290 + 291 + for (i = 0; i < lockregs; i++) { 292 + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + 293 + i * L2X0_LOCKDOWN_STRIDE); 294 + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + 295 + i * L2X0_LOCKDOWN_STRIDE); 296 + } 297 + } 298 + 280 299 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) 281 300 { 282 301 __u32 aux; ··· 347 328 * accessing the below registers will fault. 348 329 */ 349 330 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { 331 + /* Make sure that I&D is not locked down when starting */ 332 + l2x0_unlock(cache_id); 350 333 351 334 /* l2x0 controller is disabled */ 352 335 writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
+1 -1
arch/arm/mm/init.c
··· 298 298 #ifdef CONFIG_HAVE_ARCH_PFN_VALID 299 299 int pfn_valid(unsigned long pfn) 300 300 { 301 - return memblock_is_memory(pfn << PAGE_SHIFT); 301 + return memblock_is_memory(__pfn_to_phys(pfn)); 302 302 } 303 303 EXPORT_SYMBOL(pfn_valid); 304 304 #endif
+3
drivers/net/arm/am79c961a.c
··· 308 308 struct net_device *dev = (struct net_device *)data; 309 309 struct dev_priv *priv = netdev_priv(dev); 310 310 unsigned int lnkstat, carrier; 311 + unsigned long flags; 311 312 313 + spin_lock_irqsave(&priv->chip_lock, flags); 312 314 lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST; 315 + spin_unlock_irqrestore(&priv->chip_lock, flags); 313 316 carrier = netif_carrier_ok(dev); 314 317 315 318 if (lnkstat && !carrier) {