Merge branch 'add-embedded-sync-feature-for-a-dpll-s-pin'

+21

Documentation/driver-api/dpll.rst

··· 214 214 divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and 215 215 modulo divided to get fractional part. 216 216 217 + Embedded SYNC 218 + ============= 219 + 220 + Device may provide ability to use Embedded SYNC feature. It allows 221 + to embed additional SYNC signal into the base frequency of a pin - a one 222 + special pulse of base frequency signal every time SYNC signal pulse 223 + happens. The user can configure the frequency of Embedded SYNC. 224 + The Embedded SYNC capability is always related to a given base frequency 225 + and HW capabilities. The user is provided a range of Embedded SYNC 226 + frequencies supported, depending on current base frequency configured for 227 + the pin. 228 + 229 + ========================================= ================================= 230 + ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency 231 + ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC 232 + frequency ranges 233 + ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency 234 + ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency 235 + ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC 236 + ========================================= ================================= 237 + 217 238 Configuration commands group 218 239 ============================ 219 240

+24

Documentation/netlink/specs/dpll.yaml

··· 345 345 Value is in PPM (parts per million). 346 346 This may be implemented for example for pin of type 347 347 PIN_TYPE_SYNCE_ETH_PORT. 348 + - 349 + name: esync-frequency 350 + type: u64 351 + doc: | 352 + Frequency of Embedded SYNC signal. If provided, the pin is configured 353 + with a SYNC signal embedded into its base clock frequency. 354 + - 355 + name: esync-frequency-supported 356 + type: nest 357 + multi-attr: true 358 + nested-attributes: frequency-range 359 + doc: | 360 + If provided a pin is capable of embedding a SYNC signal (within given 361 + range) into its base frequency signal. 362 + - 363 + name: esync-pulse 364 + type: u32 365 + doc: | 366 + A ratio of high to low state of a SYNC signal pulse embedded 367 + into base clock frequency. Value is in percents. 348 368 - 349 369 name: pin-parent-device 350 370 subset-of: pin ··· 530 510 - phase-adjust-max 531 511 - phase-adjust 532 512 - fractional-frequency-offset 513 + - esync-frequency 514 + - esync-frequency-supported 515 + - esync-pulse 533 516 534 517 dump: 535 518 request: ··· 559 536 - parent-device 560 537 - parent-pin 561 538 - phase-adjust 539 + - esync-frequency 562 540 - 563 541 name: pin-create-ntf 564 542 doc: Notification about pin appearing

+130

drivers/dpll/dpll_netlink.c

··· 342 342 return 0; 343 343 } 344 344 345 + static int 346 + dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 347 + struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 348 + { 349 + const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 350 + struct dpll_device *dpll = ref->dpll; 351 + struct dpll_pin_esync esync; 352 + struct nlattr *nest; 353 + int ret, i; 354 + 355 + if (!ops->esync_get) 356 + return 0; 357 + ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 358 + dpll_priv(dpll), &esync, extack); 359 + if (ret == -EOPNOTSUPP) 360 + return 0; 361 + else if (ret) 362 + return ret; 363 + if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 364 + &esync.freq, DPLL_A_PIN_PAD)) 365 + return -EMSGSIZE; 366 + if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 367 + return -EMSGSIZE; 368 + for (i = 0; i < esync.range_num; i++) { 369 + nest = nla_nest_start(msg, 370 + DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 371 + if (!nest) 372 + return -EMSGSIZE; 373 + if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 374 + sizeof(esync.range[i].min), 375 + &esync.range[i].min, DPLL_A_PIN_PAD)) 376 + goto nest_cancel; 377 + if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 378 + sizeof(esync.range[i].max), 379 + &esync.range[i].max, DPLL_A_PIN_PAD)) 380 + goto nest_cancel; 381 + nla_nest_end(msg, nest); 382 + } 383 + return 0; 384 + 385 + nest_cancel: 386 + nla_nest_cancel(msg, nest); 387 + return -EMSGSIZE; 388 + } 389 + 345 390 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 346 391 { 347 392 int fs; ··· 526 481 if (ret) 527 482 return ret; 528 483 ret = dpll_msg_add_ffo(msg, pin, ref, extack); 484 + if (ret) 485 + return ret; 486 + ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 529 487 if (ret) 530 488 return ret; 531 489 if (xa_empty(&pin->parent_refs)) ··· 782 734 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 783 735 dpll, dpll_priv(dpll), old_freq, extack)) 784 736 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 737 + } 738 + return ret; 739 + } 740 + 741 + static int 742 + dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 743 + struct netlink_ext_ack *extack) 744 + { 745 + struct dpll_pin_ref *ref, *failed; 746 + const struct dpll_pin_ops *ops; 747 + struct dpll_pin_esync esync; 748 + u64 freq = nla_get_u64(a); 749 + struct dpll_device *dpll; 750 + bool supported = false; 751 + unsigned long i; 752 + int ret; 753 + 754 + xa_for_each(&pin->dpll_refs, i, ref) { 755 + ops = dpll_pin_ops(ref); 756 + if (!ops->esync_set || !ops->esync_get) { 757 + NL_SET_ERR_MSG(extack, 758 + "embedded sync feature is not supported by this device"); 759 + return -EOPNOTSUPP; 760 + } 761 + } 762 + ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 763 + ops = dpll_pin_ops(ref); 764 + dpll = ref->dpll; 765 + ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 766 + dpll_priv(dpll), &esync, extack); 767 + if (ret) { 768 + NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 769 + return ret; 770 + } 771 + if (freq == esync.freq) 772 + return 0; 773 + for (i = 0; i < esync.range_num; i++) 774 + if (freq <= esync.range[i].max && freq >= esync.range[i].min) 775 + supported = true; 776 + if (!supported) { 777 + NL_SET_ERR_MSG_ATTR(extack, a, 778 + "requested embedded sync frequency value is not supported by this device"); 779 + return -EINVAL; 780 + } 781 + 782 + xa_for_each(&pin->dpll_refs, i, ref) { 783 + void *pin_dpll_priv; 784 + 785 + ops = dpll_pin_ops(ref); 786 + dpll = ref->dpll; 787 + pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 788 + ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 789 + freq, extack); 790 + if (ret) { 791 + failed = ref; 792 + NL_SET_ERR_MSG_FMT(extack, 793 + "embedded sync frequency set failed for dpll_id: %u", 794 + dpll->id); 795 + goto rollback; 796 + } 797 + } 798 + __dpll_pin_change_ntf(pin); 799 + 800 + return 0; 801 + 802 + rollback: 803 + xa_for_each(&pin->dpll_refs, i, ref) { 804 + void *pin_dpll_priv; 805 + 806 + if (ref == failed) 807 + break; 808 + ops = dpll_pin_ops(ref); 809 + dpll = ref->dpll; 810 + pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 811 + if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 812 + esync.freq, extack)) 813 + NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 785 814 } 786 815 return ret; 787 816 } ··· 1161 1036 break; 1162 1037 case DPLL_A_PIN_PARENT_PIN: 1163 1038 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1039 + if (ret) 1040 + return ret; 1041 + break; 1042 + case DPLL_A_PIN_ESYNC_FREQUENCY: 1043 + ret = dpll_pin_esync_set(pin, a, info->extack); 1164 1044 if (ret) 1165 1045 return ret; 1166 1046 break;

+3 -2

drivers/dpll/dpll_nl.c

··· 62 62 }; 63 63 64 64 /* DPLL_CMD_PIN_SET - do */ 65 - static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = { 65 + static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY + 1] = { 66 66 [DPLL_A_PIN_ID] = { .type = NLA_U32, }, 67 67 [DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, }, 68 68 [DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2), ··· 71 71 [DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy), 72 72 [DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy), 73 73 [DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, }, 74 + [DPLL_A_PIN_ESYNC_FREQUENCY] = { .type = NLA_U64, }, 74 75 }; 75 76 76 77 /* Ops table for dpll */ ··· 139 138 .doit = dpll_nl_pin_set_doit, 140 139 .post_doit = dpll_pin_post_doit, 141 140 .policy = dpll_pin_set_nl_policy, 142 - .maxattr = DPLL_A_PIN_PHASE_ADJUST, 141 + .maxattr = DPLL_A_PIN_ESYNC_FREQUENCY, 143 142 .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, 144 143 }, 145 144 };

+220 -3

drivers/net/ethernet/intel/ice/ice_dpll.c

··· 9 9 #define ICE_CGU_STATE_ACQ_ERR_THRESHOLD 50 10 10 #define ICE_DPLL_PIN_IDX_INVALID 0xff 11 11 #define ICE_DPLL_RCLK_NUM_PER_PF 1 12 + #define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25 12 13 13 14 /** 14 15 * enum ice_dpll_pin_type - enumerate ice pin types: ··· 29 28 [ICE_DPLL_PIN_TYPE_INPUT] = "input", 30 29 [ICE_DPLL_PIN_TYPE_OUTPUT] = "output", 31 30 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input", 31 + }; 32 + 33 + static const struct dpll_pin_frequency ice_esync_range[] = { 34 + DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ), 32 35 }; 33 36 34 37 /** ··· 399 394 400 395 switch (pin_type) { 401 396 case ICE_DPLL_PIN_TYPE_INPUT: 402 - ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL, 403 - NULL, &pin->flags[0], 397 + ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, &pin->status, 398 + NULL, NULL, &pin->flags[0], 404 399 &pin->freq, &pin->phase_adjust); 405 400 if (ret) 406 401 goto err; ··· 435 430 goto err; 436 431 437 432 parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL; 438 - if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { 433 + if (ICE_AQC_GET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) { 439 434 pin->state[pf->dplls.eec.dpll_idx] = 440 435 parent == pf->dplls.eec.dpll_idx ? 441 436 DPLL_PIN_STATE_CONNECTED : ··· 1104 1099 } 1105 1100 1106 1101 /** 1102 + * ice_dpll_output_esync_set - callback for setting embedded sync 1103 + * @pin: pointer to a pin 1104 + * @pin_priv: private data pointer passed on pin registration 1105 + * @dpll: registered dpll pointer 1106 + * @dpll_priv: private data pointer passed on dpll registration 1107 + * @freq: requested embedded sync frequency 1108 + * @extack: error reporting 1109 + * 1110 + * Dpll subsystem callback. Handler for setting embedded sync frequency value 1111 + * on output pin. 1112 + * 1113 + * Context: Acquires pf->dplls.lock 1114 + * Return: 1115 + * * 0 - success 1116 + * * negative - error 1117 + */ 1118 + static int 1119 + ice_dpll_output_esync_set(const struct dpll_pin *pin, void *pin_priv, 1120 + const struct dpll_device *dpll, void *dpll_priv, 1121 + u64 freq, struct netlink_ext_ack *extack) 1122 + { 1123 + struct ice_dpll_pin *p = pin_priv; 1124 + struct ice_dpll *d = dpll_priv; 1125 + struct ice_pf *pf = d->pf; 1126 + u8 flags = 0; 1127 + int ret; 1128 + 1129 + if (ice_dpll_is_reset(pf, extack)) 1130 + return -EBUSY; 1131 + mutex_lock(&pf->dplls.lock); 1132 + if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN) 1133 + flags = ICE_AQC_SET_CGU_OUT_CFG_OUT_EN; 1134 + if (freq == DPLL_PIN_FREQUENCY_1_HZ) { 1135 + if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { 1136 + ret = 0; 1137 + } else { 1138 + flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 1139 + ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, 1140 + 0, 0, 0); 1141 + } 1142 + } else { 1143 + if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)) { 1144 + ret = 0; 1145 + } else { 1146 + flags &= ~ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN; 1147 + ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flags, 1148 + 0, 0, 0); 1149 + } 1150 + } 1151 + mutex_unlock(&pf->dplls.lock); 1152 + 1153 + return ret; 1154 + } 1155 + 1156 + /** 1157 + * ice_dpll_output_esync_get - callback for getting embedded sync config 1158 + * @pin: pointer to a pin 1159 + * @pin_priv: private data pointer passed on pin registration 1160 + * @dpll: registered dpll pointer 1161 + * @dpll_priv: private data pointer passed on dpll registration 1162 + * @esync: on success holds embedded sync pin properties 1163 + * @extack: error reporting 1164 + * 1165 + * Dpll subsystem callback. Handler for getting embedded sync frequency value 1166 + * and capabilities on output pin. 1167 + * 1168 + * Context: Acquires pf->dplls.lock 1169 + * Return: 1170 + * * 0 - success 1171 + * * negative - error 1172 + */ 1173 + static int 1174 + ice_dpll_output_esync_get(const struct dpll_pin *pin, void *pin_priv, 1175 + const struct dpll_device *dpll, void *dpll_priv, 1176 + struct dpll_pin_esync *esync, 1177 + struct netlink_ext_ack *extack) 1178 + { 1179 + struct ice_dpll_pin *p = pin_priv; 1180 + struct ice_dpll *d = dpll_priv; 1181 + struct ice_pf *pf = d->pf; 1182 + 1183 + if (ice_dpll_is_reset(pf, extack)) 1184 + return -EBUSY; 1185 + mutex_lock(&pf->dplls.lock); 1186 + if (!(p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_ABILITY) || 1187 + p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { 1188 + mutex_unlock(&pf->dplls.lock); 1189 + return -EOPNOTSUPP; 1190 + } 1191 + esync->range = ice_esync_range; 1192 + esync->range_num = ARRAY_SIZE(ice_esync_range); 1193 + if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN) { 1194 + esync->freq = DPLL_PIN_FREQUENCY_1_HZ; 1195 + esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; 1196 + } else { 1197 + esync->freq = 0; 1198 + esync->pulse = 0; 1199 + } 1200 + mutex_unlock(&pf->dplls.lock); 1201 + 1202 + return 0; 1203 + } 1204 + 1205 + /** 1206 + * ice_dpll_input_esync_set - callback for setting embedded sync 1207 + * @pin: pointer to a pin 1208 + * @pin_priv: private data pointer passed on pin registration 1209 + * @dpll: registered dpll pointer 1210 + * @dpll_priv: private data pointer passed on dpll registration 1211 + * @freq: requested embedded sync frequency 1212 + * @extack: error reporting 1213 + * 1214 + * Dpll subsystem callback. Handler for setting embedded sync frequency value 1215 + * on input pin. 1216 + * 1217 + * Context: Acquires pf->dplls.lock 1218 + * Return: 1219 + * * 0 - success 1220 + * * negative - error 1221 + */ 1222 + static int 1223 + ice_dpll_input_esync_set(const struct dpll_pin *pin, void *pin_priv, 1224 + const struct dpll_device *dpll, void *dpll_priv, 1225 + u64 freq, struct netlink_ext_ack *extack) 1226 + { 1227 + struct ice_dpll_pin *p = pin_priv; 1228 + struct ice_dpll *d = dpll_priv; 1229 + struct ice_pf *pf = d->pf; 1230 + u8 flags_en = 0; 1231 + int ret; 1232 + 1233 + if (ice_dpll_is_reset(pf, extack)) 1234 + return -EBUSY; 1235 + mutex_lock(&pf->dplls.lock); 1236 + if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN) 1237 + flags_en = ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN; 1238 + if (freq == DPLL_PIN_FREQUENCY_1_HZ) { 1239 + if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { 1240 + ret = 0; 1241 + } else { 1242 + flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 1243 + ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, 1244 + flags_en, 0, 0); 1245 + } 1246 + } else { 1247 + if (!(p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)) { 1248 + ret = 0; 1249 + } else { 1250 + flags_en &= ~ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN; 1251 + ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, 0, 1252 + flags_en, 0, 0); 1253 + } 1254 + } 1255 + mutex_unlock(&pf->dplls.lock); 1256 + 1257 + return ret; 1258 + } 1259 + 1260 + /** 1261 + * ice_dpll_input_esync_get - callback for getting embedded sync config 1262 + * @pin: pointer to a pin 1263 + * @pin_priv: private data pointer passed on pin registration 1264 + * @dpll: registered dpll pointer 1265 + * @dpll_priv: private data pointer passed on dpll registration 1266 + * @esync: on success holds embedded sync pin properties 1267 + * @extack: error reporting 1268 + * 1269 + * Dpll subsystem callback. Handler for getting embedded sync frequency value 1270 + * and capabilities on input pin. 1271 + * 1272 + * Context: Acquires pf->dplls.lock 1273 + * Return: 1274 + * * 0 - success 1275 + * * negative - error 1276 + */ 1277 + static int 1278 + ice_dpll_input_esync_get(const struct dpll_pin *pin, void *pin_priv, 1279 + const struct dpll_device *dpll, void *dpll_priv, 1280 + struct dpll_pin_esync *esync, 1281 + struct netlink_ext_ack *extack) 1282 + { 1283 + struct ice_dpll_pin *p = pin_priv; 1284 + struct ice_dpll *d = dpll_priv; 1285 + struct ice_pf *pf = d->pf; 1286 + 1287 + if (ice_dpll_is_reset(pf, extack)) 1288 + return -EBUSY; 1289 + mutex_lock(&pf->dplls.lock); 1290 + if (!(p->status & ICE_AQC_GET_CGU_IN_CFG_STATUS_ESYNC_CAP) || 1291 + p->freq != DPLL_PIN_FREQUENCY_10_MHZ) { 1292 + mutex_unlock(&pf->dplls.lock); 1293 + return -EOPNOTSUPP; 1294 + } 1295 + esync->range = ice_esync_range; 1296 + esync->range_num = ARRAY_SIZE(ice_esync_range); 1297 + if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN) { 1298 + esync->freq = DPLL_PIN_FREQUENCY_1_HZ; 1299 + esync->pulse = ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT; 1300 + } else { 1301 + esync->freq = 0; 1302 + esync->pulse = 0; 1303 + } 1304 + mutex_unlock(&pf->dplls.lock); 1305 + 1306 + return 0; 1307 + } 1308 + 1309 + /** 1107 1310 * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin 1108 1311 * @pin: pointer to a pin 1109 1312 * @pin_priv: private data pointer passed on pin registration ··· 1435 1222 .phase_adjust_get = ice_dpll_pin_phase_adjust_get, 1436 1223 .phase_adjust_set = ice_dpll_input_phase_adjust_set, 1437 1224 .phase_offset_get = ice_dpll_phase_offset_get, 1225 + .esync_set = ice_dpll_input_esync_set, 1226 + .esync_get = ice_dpll_input_esync_get, 1438 1227 }; 1439 1228 1440 1229 static const struct dpll_pin_ops ice_dpll_output_ops = { ··· 1447 1232 .direction_get = ice_dpll_output_direction, 1448 1233 .phase_adjust_get = ice_dpll_pin_phase_adjust_get, 1449 1234 .phase_adjust_set = ice_dpll_output_phase_adjust_set, 1235 + .esync_set = ice_dpll_output_esync_set, 1236 + .esync_get = ice_dpll_output_esync_get, 1450 1237 }; 1451 1238 1452 1239 static const struct dpll_device_ops ice_dpll_ops = {

+1

drivers/net/ethernet/intel/ice/ice_dpll.h

··· 31 31 struct dpll_pin_properties prop; 32 32 u32 freq; 33 33 s32 phase_adjust; 34 + u8 status; 34 35 }; 35 36 36 37 /** ice_dpll - store info required for DPLL control

+15

include/linux/dpll.h

··· 15 15 16 16 struct dpll_device; 17 17 struct dpll_pin; 18 + struct dpll_pin_esync; 18 19 19 20 struct dpll_device_ops { 20 21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv, ··· 84 83 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv, 85 84 const struct dpll_device *dpll, void *dpll_priv, 86 85 s64 *ffo, struct netlink_ext_ack *extack); 86 + int (*esync_set)(const struct dpll_pin *pin, void *pin_priv, 87 + const struct dpll_device *dpll, void *dpll_priv, 88 + u64 freq, struct netlink_ext_ack *extack); 89 + int (*esync_get)(const struct dpll_pin *pin, void *pin_priv, 90 + const struct dpll_device *dpll, void *dpll_priv, 91 + struct dpll_pin_esync *esync, 92 + struct netlink_ext_ack *extack); 87 93 }; 88 94 89 95 struct dpll_pin_frequency { ··· 117 109 struct dpll_pin_phase_adjust_range { 118 110 s32 min; 119 111 s32 max; 112 + }; 113 + 114 + struct dpll_pin_esync { 115 + u64 freq; 116 + const struct dpll_pin_frequency *range; 117 + u8 range_num; 118 + u8 pulse; 120 119 }; 121 120 122 121 struct dpll_pin_properties {

+3

include/uapi/linux/dpll.h

··· 210 210 DPLL_A_PIN_PHASE_ADJUST, 211 211 DPLL_A_PIN_PHASE_OFFSET, 212 212 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 213 + DPLL_A_PIN_ESYNC_FREQUENCY, 214 + DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED, 215 + DPLL_A_PIN_ESYNC_PULSE, 213 216 214 217 __DPLL_A_PIN_MAX, 215 218 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)

Configure Feed

Configure Feed