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ASoC: SOF: amd: Add sof support for vangogh platform

Add pci driver and platform driver to enable SOF support
on ACP5x architecture based Vangogh platform.

Signed-off-by: Venkata Prasad Potturu <venkataprasad.potturu@amd.com>
Link: https://lore.kernel.org/r/20230809123534.287707-1-venkataprasad.potturu@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Venkata Prasad Potturu and committed by
Mark Brown
d0dab6b7 919a4a94

+290 -4
+11 -1
sound/soc/sof/amd/Kconfig
··· 2 2 # This file is provided under a dual BSD/GPLv2 license. When using or 3 3 # redistributing this file, you may do so under either license. 4 4 # 5 - # Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 5 + # Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 6 6 7 7 config SND_SOC_SOF_AMD_TOPLEVEL 8 8 tristate "SOF support for AMD audio DSPs" ··· 33 33 select SND_SOC_SOF_AMD_COMMON 34 34 help 35 35 Select this option for SOF support on AMD Renoir platform 36 + 37 + config SND_SOC_SOF_AMD_VANGOGH 38 + tristate "SOF support for VANGOGH" 39 + depends on SND_SOC_SOF_PCI 40 + select SND_SOC_SOF_AMD_COMMON 41 + help 42 + Select this option for SOF support 43 + on AMD Vangogh platform. 44 + Say Y if you want to enable SOF on Vangogh. 45 + If unsure select "N". 36 46 37 47 config SND_SOC_SOF_AMD_REMBRANDT 38 48 tristate "SOF support for REMBRANDT"
+3 -1
sound/soc/sof/amd/Makefile
··· 2 2 # This file is provided under a dual BSD/GPLv2 license. When using or 3 3 # redistributing this file, you may do so under either license. 4 4 # 5 - # Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 5 + # Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 6 6 7 7 snd-sof-amd-acp-objs := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o acp-common.o 8 8 snd-sof-amd-acp-$(CONFIG_SND_SOC_SOF_ACP_PROBES) = acp-probes.o 9 9 snd-sof-amd-renoir-objs := pci-rn.o renoir.o 10 10 snd-sof-amd-rembrandt-objs := pci-rmb.o rembrandt.o 11 + snd-sof-amd-vangogh-objs := pci-vangogh.o vangogh.o 11 12 12 13 obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o 13 14 obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) +=snd-sof-amd-renoir.o 14 15 obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) +=snd-sof-amd-rembrandt.o 16 + obj-$(CONFIG_SND_SOC_SOF_AMD_VANGOGH) +=snd-sof-amd-vangogh.o
+7 -1
sound/soc/sof/amd/acp-dsp-offset.h
··· 3 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 4 * redistributing this file, you may do so under either license. 5 5 * 6 - * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 6 + * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 7 * 8 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 9 */ ··· 49 49 #define ACP_CONTROL 0x1004 50 50 51 51 #define ACP3X_I2S_PIN_CONFIG 0x1400 52 + #define ACP5X_I2S_PIN_CONFIG 0x1400 52 53 #define ACP6X_I2S_PIN_CONFIG 0x1440 53 54 54 55 /* Registers offsets from ACP_PGFSM block */ 55 56 #define ACP3X_PGFSM_BASE 0x141C 57 + #define ACP5X_PGFSM_BASE 0x1424 56 58 #define ACP6X_PGFSM_BASE 0x1024 57 59 #define PGFSM_CONTROL_OFFSET 0x0 58 60 #define PGFSM_STATUS_OFFSET 0x4 59 61 #define ACP3X_CLKMUX_SEL 0x1424 62 + #define ACP5X_CLKMUX_SEL 0x142C 60 63 #define ACP6X_CLKMUX_SEL 0x102C 61 64 62 65 /* Registers from ACP_INTR block */ 63 66 #define ACP3X_EXT_INTR_STAT 0x1808 67 + #define ACP5X_EXT_INTR_STAT 0x1808 64 68 #define ACP6X_EXT_INTR_STAT 0x1A0C 65 69 66 70 #define ACP3X_DSP_SW_INTR_BASE 0x1814 71 + #define ACP5X_DSP_SW_INTR_BASE 0x1814 67 72 #define ACP6X_DSP_SW_INTR_BASE 0x1808 68 73 #define DSP_SW_INTR_CNTL_OFFSET 0x0 69 74 #define DSP_SW_INTR_STAT_OFFSET 0x4 70 75 #define DSP_SW_INTR_TRIG_OFFSET 0x8 71 76 #define ACP_ERROR_STATUS 0x18C4 72 77 #define ACP3X_AXI2DAGB_SEM_0 0x1880 78 + #define ACP5X_AXI2DAGB_SEM_0 0x1884 73 79 #define ACP6X_AXI2DAGB_SEM_0 0x1874 74 80 75 81 /* Registers from ACP_SHA block */
+8 -1
sound/soc/sof/amd/acp.h
··· 3 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 4 * redistributing this file, you may do so under either license. 5 5 * 6 - * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 6 + * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 7 * 8 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 9 */ ··· 32 32 33 33 #define ACP_DSP_INTR_EN_MASK 0x00000001 34 34 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 35 + #define ACP5X_SRAM_PTE_OFFSET 0x02050000 35 36 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 36 37 #define PAGE_SIZE_4K_ENABLE 0x2 37 38 #define ACP_PAGE_SIZE 0x1000 ··· 57 56 #define ACP_DSP_TO_HOST_IRQ 0x04 58 57 59 58 #define ACP_RN_PCI_ID 0x01 59 + #define ACP_VANGOGH_PCI_ID 0x50 60 60 #define ACP_RMB_PCI_ID 0x6F 61 61 62 62 #define HOST_BRIDGE_CZN 0x1630 63 + #define HOST_BRIDGE_VGH 0x1645 63 64 #define HOST_BRIDGE_RMB 0x14B5 64 65 #define ACP_SHA_STAT 0x8000 65 66 #define ACP_PSP_TIMEOUT_US 1000000 ··· 166 163 167 164 struct sof_amd_acp_desc { 168 165 unsigned int rev; 166 + const char *name; 169 167 unsigned int host_bridge_id; 170 168 u32 pgfsm_base; 171 169 u32 ext_intr_stat; ··· 257 253 258 254 extern struct snd_sof_dsp_ops sof_renoir_ops; 259 255 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 256 + extern struct snd_sof_dsp_ops sof_vangogh_ops; 257 + int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 260 258 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 261 259 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 262 260 ··· 288 282 int acp_probes_register(struct snd_sof_dev *sdev); 289 283 void acp_probes_unregister(struct snd_sof_dev *sdev); 290 284 285 + extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 291 286 #endif
+105
sound/soc/sof/amd/pci-vangogh.c
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 + // 3 + // This file is provided under a dual BSD/GPLv2 license. When using or 4 + // redistributing this file, you may do so under either license. 5 + // 6 + // Copyright(c) 2023 Advanced Micro Devices, Inc. All rights reserved. 7 + // 8 + // Authors: Venkata Prasad Potturu <venkataprasad.potturu@amd.com> 9 + 10 + /*. 11 + * PCI interface for Vangogh ACP device 12 + */ 13 + 14 + #include <linux/module.h> 15 + #include <linux/pci.h> 16 + #include <linux/platform_device.h> 17 + #include <sound/sof.h> 18 + #include <sound/soc-acpi.h> 19 + 20 + #include "../ops.h" 21 + #include "../sof-pci-dev.h" 22 + #include "../../amd/mach-config.h" 23 + #include "acp.h" 24 + #include "acp-dsp-offset.h" 25 + 26 + #define ACP5X_FUTURE_REG_ACLK_0 0x1864 27 + 28 + static const struct sof_amd_acp_desc vangogh_chip_info = { 29 + .rev = 5, 30 + .name = "vangogh", 31 + .host_bridge_id = HOST_BRIDGE_VGH, 32 + .pgfsm_base = ACP5X_PGFSM_BASE, 33 + .ext_intr_stat = ACP5X_EXT_INTR_STAT, 34 + .dsp_intr_base = ACP5X_DSP_SW_INTR_BASE, 35 + .sram_pte_offset = ACP5X_SRAM_PTE_OFFSET, 36 + .hw_semaphore_offset = ACP5X_AXI2DAGB_SEM_0, 37 + .acp_clkmux_sel = ACP5X_CLKMUX_SEL, 38 + .probe_reg_offset = ACP5X_FUTURE_REG_ACLK_0, 39 + }; 40 + 41 + static const struct sof_dev_desc vangogh_desc = { 42 + .machines = snd_soc_acpi_amd_vangogh_sof_machines, 43 + .resindex_lpe_base = 0, 44 + .resindex_pcicfg_base = -1, 45 + .resindex_imr_base = -1, 46 + .irqindex_host_ipc = -1, 47 + .chip_info = &vangogh_chip_info, 48 + .ipc_supported_mask = BIT(SOF_IPC), 49 + .ipc_default = SOF_IPC, 50 + .default_fw_path = { 51 + [SOF_IPC] = "amd/sof", 52 + }, 53 + .default_tplg_path = { 54 + [SOF_IPC] = "amd/sof-tplg", 55 + }, 56 + .default_fw_filename = { 57 + [SOF_IPC] = "sof-vangogh.ri", 58 + }, 59 + .nocodec_tplg_filename = "sof-acp.tplg", 60 + .ops = &sof_vangogh_ops, 61 + .ops_init = sof_vangogh_ops_init, 62 + }; 63 + 64 + static int acp_pci_vgh_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 65 + { 66 + unsigned int flag; 67 + 68 + if (pci->revision != ACP_VANGOGH_PCI_ID) 69 + return -ENODEV; 70 + 71 + flag = snd_amd_acp_find_config(pci); 72 + if (flag != FLAG_AMD_SOF && flag != FLAG_AMD_SOF_ONLY_DMIC) 73 + return -ENODEV; 74 + 75 + return sof_pci_probe(pci, pci_id); 76 + }; 77 + 78 + static void acp_pci_vgh_remove(struct pci_dev *pci) 79 + { 80 + sof_pci_remove(pci); 81 + } 82 + 83 + /* PCI IDs */ 84 + static const struct pci_device_id vgh_pci_ids[] = { 85 + { PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_PCI_DEV_ID), 86 + .driver_data = (unsigned long)&vangogh_desc}, 87 + { 0, } 88 + }; 89 + MODULE_DEVICE_TABLE(pci, vgh_pci_ids); 90 + 91 + /* pci_driver definition */ 92 + static struct pci_driver snd_sof_pci_amd_vgh_driver = { 93 + .name = KBUILD_MODNAME, 94 + .id_table = vgh_pci_ids, 95 + .probe = acp_pci_vgh_probe, 96 + .remove = acp_pci_vgh_remove, 97 + .driver = { 98 + .pm = &sof_pci_pm, 99 + }, 100 + }; 101 + module_pci_driver(snd_sof_pci_amd_vgh_driver); 102 + 103 + MODULE_LICENSE("Dual BSD/GPL"); 104 + MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON); 105 + MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV);
+156
sound/soc/sof/amd/vangogh.c
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 + // 3 + // This file is provided under a dual BSD/GPLv2 license. When using or 4 + // redistributing this file, you may do so under either license. 5 + // 6 + // Copyright(c) 2023 Advanced Micro Devices, Inc. 7 + // 8 + // Authors: Venkata Prasad Potturu <venkataprasad.potturu@amd.com> 9 + 10 + /* 11 + * Hardware interface for Audio DSP on Vangogh platform 12 + */ 13 + 14 + #include <linux/platform_device.h> 15 + #include <linux/module.h> 16 + 17 + #include "../ops.h" 18 + #include "../sof-audio.h" 19 + #include "acp.h" 20 + #include "acp-dsp-offset.h" 21 + 22 + #define I2S_HS_INSTANCE 0 23 + #define I2S_BT_INSTANCE 1 24 + #define I2S_SP_INSTANCE 2 25 + #define PDM_DMIC_INSTANCE 3 26 + #define I2S_HS_VIRTUAL_INSTANCE 4 27 + 28 + static struct snd_soc_dai_driver vangogh_sof_dai[] = { 29 + [I2S_HS_INSTANCE] = { 30 + .id = I2S_HS_INSTANCE, 31 + .name = "acp-sof-hs", 32 + .playback = { 33 + .rates = SNDRV_PCM_RATE_8000_96000, 34 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 35 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 36 + .channels_min = 2, 37 + .channels_max = 8, 38 + .rate_min = 8000, 39 + .rate_max = 96000, 40 + }, 41 + .capture = { 42 + .rates = SNDRV_PCM_RATE_8000_48000, 43 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 44 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 45 + /* Supporting only stereo for I2S HS controller capture */ 46 + .channels_min = 2, 47 + .channels_max = 2, 48 + .rate_min = 8000, 49 + .rate_max = 48000, 50 + }, 51 + }, 52 + 53 + [I2S_BT_INSTANCE] = { 54 + .id = I2S_BT_INSTANCE, 55 + .name = "acp-sof-bt", 56 + .playback = { 57 + .rates = SNDRV_PCM_RATE_8000_96000, 58 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 59 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 60 + .channels_min = 2, 61 + .channels_max = 8, 62 + .rate_min = 8000, 63 + .rate_max = 96000, 64 + }, 65 + .capture = { 66 + .rates = SNDRV_PCM_RATE_8000_48000, 67 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 68 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 69 + /* Supporting only stereo for I2S BT controller capture */ 70 + .channels_min = 2, 71 + .channels_max = 2, 72 + .rate_min = 8000, 73 + .rate_max = 48000, 74 + }, 75 + }, 76 + 77 + [I2S_SP_INSTANCE] = { 78 + .id = I2S_SP_INSTANCE, 79 + .name = "acp-sof-sp", 80 + .playback = { 81 + .rates = SNDRV_PCM_RATE_8000_96000, 82 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 83 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 84 + .channels_min = 2, 85 + .channels_max = 8, 86 + .rate_min = 8000, 87 + .rate_max = 96000, 88 + }, 89 + .capture = { 90 + .rates = SNDRV_PCM_RATE_8000_48000, 91 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 92 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 93 + /* Supporting only stereo for I2S SP controller capture */ 94 + .channels_min = 2, 95 + .channels_max = 2, 96 + .rate_min = 8000, 97 + .rate_max = 48000, 98 + }, 99 + }, 100 + 101 + [PDM_DMIC_INSTANCE] = { 102 + .id = PDM_DMIC_INSTANCE, 103 + .name = "acp-sof-dmic", 104 + .capture = { 105 + .rates = SNDRV_PCM_RATE_8000_48000, 106 + .formats = SNDRV_PCM_FMTBIT_S32_LE, 107 + .channels_min = 2, 108 + .channels_max = 4, 109 + .rate_min = 8000, 110 + .rate_max = 48000, 111 + }, 112 + }, 113 + 114 + [I2S_HS_VIRTUAL_INSTANCE] = { 115 + .id = I2S_HS_VIRTUAL_INSTANCE, 116 + .name = "acp-sof-hs-virtual", 117 + .playback = { 118 + .rates = SNDRV_PCM_RATE_8000_96000, 119 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 120 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 121 + .channels_min = 2, 122 + .channels_max = 8, 123 + .rate_min = 8000, 124 + .rate_max = 96000, 125 + }, 126 + .capture = { 127 + .rates = SNDRV_PCM_RATE_8000_48000, 128 + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 129 + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, 130 + /* Supporting only stereo for I2S HS-Virtual controller capture */ 131 + .channels_min = 2, 132 + .channels_max = 2, 133 + .rate_min = 8000, 134 + .rate_max = 48000, 135 + }, 136 + }, 137 + }; 138 + 139 + /* Vangogh ops */ 140 + struct snd_sof_dsp_ops sof_vangogh_ops; 141 + EXPORT_SYMBOL_NS(sof_vangogh_ops, SND_SOC_SOF_AMD_COMMON); 142 + 143 + int sof_vangogh_ops_init(struct snd_sof_dev *sdev) 144 + { 145 + /* common defaults */ 146 + memcpy(&sof_vangogh_ops, &sof_acp_common_ops, sizeof(struct snd_sof_dsp_ops)); 147 + 148 + sof_vangogh_ops.drv = vangogh_sof_dai; 149 + sof_vangogh_ops.num_drv = ARRAY_SIZE(vangogh_sof_dai); 150 + 151 + return 0; 152 + } 153 + 154 + MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON); 155 + MODULE_DESCRIPTION("VANGOGH SOF Driver"); 156 + MODULE_LICENSE("Dual BSD/GPL");