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OMAPDSS: fix rounding when calculating fclk rate

"clk: divider: fix rate calculation for fractional rates" patch (and
similar for TI specific divider) fixes the clk-divider's rounding. This
patch updates the DSS driver to round the rates accordingly.

This fixes the DSS's warnings about clock rate mismatch, and also fixes
the wrong fclk rate being set.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Christoph Fritz <chf.fritz@googlemail.com>
Tested-by: Marek Belisko <marek@goldelico.com>

+2 -2
+2 -2
drivers/video/omap2/dss/dss.c
··· 457 457 fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); 458 458 459 459 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { 460 - fck = prate / fckd * m; 460 + fck = DIV_ROUND_UP(prate, fckd) * m; 461 461 462 462 if (func(fck, data)) 463 463 return true; ··· 506 506 507 507 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, 508 508 max_dss_fck); 509 - fck = prate / fck_div * dss.feat->dss_fck_multiplier; 509 + fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; 510 510 } 511 511 512 512 r = dss_set_fck_rate(fck);