Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spi-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"A busy enough release, but not for the core which has only seen very
small updates. The biggest addition is the readdition of support for
detailed configuration of the timings around chip selects. That had
been removed for lack of use but there's been applications found for
it on Atmel systems. Otherwise the updates are mostly feature
additions and cleanups to existing drivers.
Summary:
- Provide a helper for getting device match data in a way that
abstracts away which firmware interface is being used.
- Re-add the spi_set_cs_timing() API for detailed configuration of
the timing around chip select and support it on Atmel.
- Support for MediaTek MT7986, Microchip PCI1xxxx, Nuvoton WPCM450
FIU and Socionext F_OSPI"
* tag 'spi-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits)
spi: dt-bindings: Convert Synquacer SPI to DT schema
spi: spi-gpio: Don't set MOSI as an input if not 3WIRE mode
spi: spi-mtk-nor: Add recovery mechanism for dma read timeout
spi: spi-fsl-lpspi: add num-cs binding for lpspi
spi: spi-fsl-lpspi: support multiple cs for lpspi
spi: mtk-snfi: Add snfi support for MT7986 IC
spi: spidev: mask SPI_CS_HIGH in SPI_IOC_RD_MODE
spi: cadence-quadspi: Add minimum operable clock rate warning to baudrate divisor calculation
spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver
spi: dt-bindings: nuvoton,wpcm450-fiu: Fix warning in example (missing reg property)
spi: dt-bindings: nuvoton,wpcm450-fiu: Fix error in example (bogus include)
spi: mediatek: Enable irq when pdata is ready
spi: spi-mtk-nor: Unify write buffer on/off
spi: intel: Add support for SFDP opcode
spi: intel: Take possible chip address into account in intel_spi_read/write_reg()
spi: intel: Implement adjust_op_size()
spi: intel: Use ->replacement_op in intel_spi_hw_cycle()
spi: cadence: Drop obsolete dependency on COMPILE_TEST
spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings
spi: wpcm-fiu: Add direct map support
...
+2612
-386
+43
-24
Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
+43
-24
Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
···
10
10
maintainers:
11
11
- Neil Armstrong <neil.armstrong@linaro.org>
12
12
13
-
allOf:
14
-
- $ref: "spi-controller.yaml#"
15
-
16
13
description: |
17
14
The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
18
15
communications with dedicated 16 words RX/TX PIO FIFOs.
···
40
43
minItems: 1
41
44
maxItems: 2
42
45
43
-
if:
44
-
properties:
45
-
compatible:
46
-
contains:
47
-
enum:
48
-
- amlogic,meson-g12a-spicc
46
+
allOf:
47
+
- $ref: "spi-controller.yaml#"
48
+
- if:
49
+
properties:
50
+
compatible:
51
+
contains:
52
+
enum:
53
+
- amlogic,meson-g12a-spicc
49
54
50
-
then:
51
-
properties:
52
-
clocks:
53
-
minItems: 2
55
+
then:
56
+
properties:
57
+
clocks:
58
+
minItems: 2
54
59
55
-
clock-names:
56
-
items:
57
-
- const: core
58
-
- const: pclk
60
+
clock-names:
61
+
items:
62
+
- const: core
63
+
- const: pclk
59
64
60
-
else:
61
-
properties:
62
-
clocks:
63
-
maxItems: 1
65
+
else:
66
+
properties:
67
+
clocks:
68
+
maxItems: 1
64
69
65
-
clock-names:
66
-
items:
67
-
- const: core
70
+
clock-names:
71
+
items:
72
+
- const: core
73
+
74
+
- if:
75
+
properties:
76
+
compatible:
77
+
contains:
78
+
enum:
79
+
- amlogic,meson-gx-spicc
80
+
81
+
then:
82
+
properties:
83
+
pinctrl-0: true
84
+
pinctrl-1: true
85
+
pinctrl-2: true
86
+
87
+
pinctrl-names:
88
+
minItems: 1
89
+
items:
90
+
- const: default
91
+
- const: idle-high
92
+
- const: idle-low
68
93
69
94
required:
70
95
- compatible
+1
-1
Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
+1
-1
Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
+66
Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml
+66
Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Nuvoton WPCM450 Flash Interface Unit (FIU)
8
+
9
+
maintainers:
10
+
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11
+
12
+
allOf:
13
+
- $ref: /schemas/spi/spi-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
const: nuvoton,wpcm450-fiu
18
+
19
+
reg:
20
+
items:
21
+
- description: FIU registers
22
+
- description: Memory-mapped flash contents
23
+
24
+
reg-names:
25
+
items:
26
+
- const: control
27
+
- const: memory
28
+
29
+
interrupts:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
maxItems: 1
34
+
35
+
nuvoton,shm:
36
+
$ref: /schemas/types.yaml#/definitions/phandle
37
+
description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml)
38
+
39
+
required:
40
+
- compatible
41
+
- reg
42
+
- clocks
43
+
44
+
unevaluatedProperties: false
45
+
46
+
examples:
47
+
- |
48
+
spi@c8000000 {
49
+
compatible = "nuvoton,wpcm450-fiu";
50
+
reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
51
+
#address-cells = <1>;
52
+
#size-cells = <0>;
53
+
reg-names = "control", "memory";
54
+
clocks = <&clk 0>;
55
+
nuvoton,shm = <&shm>;
56
+
57
+
flash@0 {
58
+
compatible = "jedec,spi-nor";
59
+
reg = <0>;
60
+
};
61
+
};
62
+
63
+
shm: syscon@c8001000 {
64
+
compatible = "nuvoton,wpcm450-shm", "syscon";
65
+
reg = <0xc8001000 0x1000>;
66
+
};
+57
Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml
+57
Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext F_OSPI controller
8
+
9
+
description: |
10
+
The Socionext F_OSPI is a controller used to interface with flash
11
+
memories using the SPI communication interface.
12
+
13
+
maintainers:
14
+
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15
+
16
+
allOf:
17
+
- $ref: spi-controller.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: socionext,f-ospi
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 1
28
+
29
+
num-cs:
30
+
minimum: 1
31
+
maximum: 4
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- clocks
37
+
- "#address-cells"
38
+
- "#size-cells"
39
+
40
+
unevaluatedProperties: false
41
+
42
+
examples:
43
+
- |
44
+
ospi0: spi@80000000 {
45
+
compatible = "socionext,f-ospi";
46
+
reg = <0x80000000 0x1000>;
47
+
clocks = <&clks 0>;
48
+
num-cs = <1>;
49
+
#address-cells = <1>;
50
+
#size-cells = <0>;
51
+
52
+
flash@0 {
53
+
compatible = "spansion,s25fl128s", "jedec,spi-nor";
54
+
reg = <0>;
55
+
spi-max-frequency = <50000000>;
56
+
};
57
+
};
+73
Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml
+73
Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Socionext SynQuacer HS-SPI Controller
8
+
9
+
maintainers:
10
+
- Masahisa Kojima <masahisa.kojima@linaro.org>
11
+
- Jassi Brar <jaswinder.singh@linaro.org>
12
+
13
+
allOf:
14
+
- $ref: spi-controller.yaml#
15
+
16
+
properties:
17
+
compatible:
18
+
const: socionext,synquacer-spi
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
clocks:
24
+
minItems: 1
25
+
items:
26
+
- description: core clock
27
+
- description: rate clock
28
+
29
+
clock-names:
30
+
minItems: 1
31
+
items:
32
+
- const: iHCLK
33
+
- const: iPCLK
34
+
35
+
interrupts:
36
+
items:
37
+
- description: Receive Interrupt
38
+
- description: Transmit Interrupt
39
+
- description: Fault Interrupt
40
+
41
+
socionext,use-rtm:
42
+
type: boolean
43
+
description: Enable using "retimed clock" for RX
44
+
45
+
socionext,set-aces:
46
+
type: boolean
47
+
description: Enable same active clock edges field to be set
48
+
49
+
required:
50
+
- compatible
51
+
- reg
52
+
- interrupts
53
+
- clocks
54
+
- clock-names
55
+
56
+
unevaluatedProperties: false
57
+
58
+
examples:
59
+
- |
60
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
61
+
62
+
spi@ff110000 {
63
+
compatible = "socionext,synquacer-spi";
64
+
reg = <0xff110000 0x1000>;
65
+
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
66
+
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
67
+
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
68
+
clocks = <&clk_hsspi>;
69
+
clock-names = "iHCLK";
70
+
socionext,use-rtm;
71
+
socionext,set-aces;
72
+
};
73
+
...
+8
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
+8
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
···
56
56
this property to re-config the chipselect value in the LPSPI driver.
57
57
type: boolean
58
58
59
+
num-cs:
60
+
description:
61
+
number of chip selects.
62
+
minimum: 1
63
+
maximum: 2
64
+
default: 1
65
+
59
66
required:
60
67
- compatible
61
68
- reg
···
87
80
clock-names = "per", "ipg";
88
81
spi-slave;
89
82
fsl,spi-only-use-cs1-sel;
83
+
num-cs = <2>;
90
84
};
+5
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+5
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
···
44
44
description:
45
45
Maximum SPI clocking speed of the device in Hz.
46
46
47
+
spi-cs-setup-ns:
48
+
description:
49
+
Delay in nanosecods to be introduced by the controller after CS is
50
+
asserted.
51
+
47
52
spi-rx-bus-width:
48
53
description:
49
54
Bus width to the SPI bus used for read transfers.
-27
Documentation/devicetree/bindings/spi/spi-synquacer.txt
-27
Documentation/devicetree/bindings/spi/spi-synquacer.txt
···
1
-
* Socionext Synquacer HS-SPI bindings
2
-
3
-
Required Properties:
4
-
- compatible: should be "socionext,synquacer-spi"
5
-
- reg: physical base address of the controller and length of memory mapped
6
-
region.
7
-
- interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts.
8
-
- clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK)
9
-
- clock-names: Shall be "iHCLK" and "iPCLK" respectively
10
-
11
-
Optional Properties:
12
-
- socionext,use-rtm: boolean, if required to use "retimed clock" for RX
13
-
- socionext,set-aces: boolean, if same active clock edges field to be set.
14
-
15
-
Example:
16
-
17
-
spi0: spi@ff110000 {
18
-
compatible = "socionext,synquacer-spi";
19
-
reg = <0xff110000 0x1000>;
20
-
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
21
-
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
22
-
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
23
-
clocks = <&clk_hsspi>;
24
-
clock-names = "iHCLK";
25
-
socionext,use-rtm;
26
-
socionext,set-aces;
27
-
};
+3
-1
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
+3
-1
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
+2
-2
Documentation/driver-api/spi.rst
+2
-2
Documentation/driver-api/spi.rst
···
25
25
a pair of FIFOs connected to dual DMA engines on the other side of the
26
26
SPI shift register (maximizing throughput). Such drivers bridge between
27
27
whatever bus they sit on (often the platform bus) and SPI, and expose
28
-
the SPI side of their device as a :c:type:`struct spi_master
29
-
<spi_master>`. SPI devices are children of that master,
28
+
the SPI side of their device as a :c:type:`struct spi_controller
29
+
<spi_controller>`. SPI devices are children of that master,
30
30
represented as a :c:type:`struct spi_device <spi_device>` and
31
31
manufactured from :c:type:`struct spi_board_info
32
32
<spi_board_info>` descriptors which are usually provided by
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
19159
19159
M: Jassi Brar <jaswinder.singh@linaro.org>
19160
19160
L: linux-spi@vger.kernel.org
19161
19161
S: Maintained
19162
-
F: Documentation/devicetree/bindings/spi/spi-synquacer.txt
19162
+
F: Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml
19163
19163
F: drivers/spi/spi-synquacer.c
19164
19164
19165
19165
SOCIONEXT SYNQUACER I2C DRIVER
+7
drivers/firmware/xilinx/zynqmp.c
+7
drivers/firmware/xilinx/zynqmp.c
···
843
843
}
844
844
EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
845
845
846
+
int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
847
+
{
848
+
return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_SET_TAPDELAY_BYPASS,
849
+
index, value, NULL);
850
+
}
851
+
EXPORT_SYMBOL_GPL(zynqmp_pm_set_tapdelay_bypass);
852
+
846
853
/**
847
854
* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
848
855
* @value: Status value to be written
+30
-1
drivers/spi/Kconfig
+30
-1
drivers/spi/Kconfig
···
241
241
242
242
config SPI_CADENCE_XSPI
243
243
tristate "Cadence XSPI controller"
244
-
depends on (OF || COMPILE_TEST) && HAS_IOMEM
244
+
depends on OF && HAS_IOMEM
245
245
depends on SPI_MEM
246
246
help
247
247
Enable support for the Cadence XSPI Flash controller.
···
635
635
is implemented as a SPI-MEM controller with pipelined ECC
636
636
capcability.
637
637
638
+
config SPI_WPCM_FIU
639
+
tristate "Nuvoton WPCM450 Flash Interface Unit"
640
+
depends on ARCH_NPCM || COMPILE_TEST
641
+
select REGMAP
642
+
help
643
+
This enables support got the Flash Interface Unit SPI controller
644
+
present in the Nuvoton WPCM450 SoC.
645
+
646
+
This driver does not support generic SPI. The implementation only
647
+
supports the spi-mem interface.
648
+
638
649
config SPI_NPCM_FIU
639
650
tristate "Nuvoton NPCM FLASH Interface Unit"
640
651
depends on ARCH_NPCM || COMPILE_TEST
···
720
709
help
721
710
This enables using the SPI master controller on the Orion
722
711
and MVEBU chips.
712
+
713
+
config SPI_PCI1XXXX
714
+
tristate "PCI1XXXX SPI Bus support"
715
+
depends on PCI
716
+
help
717
+
Say "yes" to Enable the SPI Bus support for the PCI1xxxx card
718
+
This is a PCI to SPI Bus driver
719
+
This driver can be built as module. If so, the module will be
720
+
called as spi-pci1xxxx.
723
721
724
722
config SPI_PIC32
725
723
tristate "Microchip PIC32 series SPI"
···
916
896
If you want to use MediaTek(R) SPI slave interface,
917
897
say Y or M here.If you are not sure, say N.
918
898
SPI slave drivers for Mediatek MT27XX series ARM SoCs.
899
+
900
+
config SPI_SN_F_OSPI
901
+
tristate "Socionext F_OSPI SPI flash controller"
902
+
depends on OF && HAS_IOMEM
903
+
depends on SPI_MEM
904
+
help
905
+
This enables support for the Socionext F_OSPI controller
906
+
for connecting an SPI Flash memory over up to 8-bit wide bus.
907
+
It supports indirect access mode only.
919
908
920
909
config SPI_SPRD
921
910
tristate "Spreadtrum SPI controller"
+3
drivers/spi/Makefile
+3
drivers/spi/Makefile
···
83
83
obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o
84
84
obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
85
85
obj-$(CONFIG_SPI_MXS) += spi-mxs.o
86
+
obj-$(CONFIG_SPI_WPCM_FIU) += spi-wpcm-fiu.o
86
87
obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o
87
88
obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o
88
89
obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o
···
95
94
obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
96
95
obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
97
96
obj-$(CONFIG_SPI_ORION) += spi-orion.o
97
+
obj-$(CONFIG_SPI_PCI1XXXX) += spi-pci1xxxx.o
98
98
obj-$(CONFIG_SPI_PIC32) += spi-pic32.o
99
99
obj-$(CONFIG_SPI_PIC32_SQI) += spi-pic32-sqi.o
100
100
obj-$(CONFIG_SPI_PL022) += spi-pl022.o
···
122
120
obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
123
121
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
124
122
obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
123
+
obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
125
124
obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
126
125
obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
127
126
obj-$(CONFIG_SPI_STM32) += spi-stm32.o
+34
drivers/spi/atmel-quadspi.c
+34
drivers/spi/atmel-quadspi.c
···
510
510
return 0;
511
511
}
512
512
513
+
static int atmel_qspi_set_cs_timing(struct spi_device *spi)
514
+
{
515
+
struct spi_controller *ctrl = spi->master;
516
+
struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
517
+
unsigned long clk_rate;
518
+
u32 cs_setup;
519
+
int delay;
520
+
int ret;
521
+
522
+
delay = spi_delay_to_ns(&spi->cs_setup, NULL);
523
+
if (delay <= 0)
524
+
return delay;
525
+
526
+
clk_rate = clk_get_rate(aq->pclk);
527
+
if (!clk_rate)
528
+
return -EINVAL;
529
+
530
+
cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)),
531
+
1000);
532
+
533
+
ret = pm_runtime_resume_and_get(ctrl->dev.parent);
534
+
if (ret < 0)
535
+
return ret;
536
+
537
+
aq->scr |= QSPI_SCR_DLYBS(cs_setup);
538
+
atmel_qspi_write(aq->scr, aq, QSPI_SCR);
539
+
540
+
pm_runtime_mark_last_busy(ctrl->dev.parent);
541
+
pm_runtime_put_autosuspend(ctrl->dev.parent);
542
+
543
+
return 0;
544
+
}
545
+
513
546
static void atmel_qspi_init(struct atmel_qspi *aq)
514
547
{
515
548
/* Reset the QSPI controller */
···
588
555
589
556
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
590
557
ctrl->setup = atmel_qspi_setup;
558
+
ctrl->set_cs_timing = atmel_qspi_set_cs_timing;
591
559
ctrl->bus_num = -1;
592
560
ctrl->mem_ops = &atmel_qspi_mem_ops;
593
561
ctrl->num_chipselect = 1;
+2
-4
drivers/spi/spi-aspeed-smc.c
+2
-4
drivers/spi/spi-aspeed-smc.c
···
734
734
aspi->data = data;
735
735
aspi->dev = dev;
736
736
737
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738
-
aspi->regs = devm_ioremap_resource(dev, res);
737
+
aspi->regs = devm_platform_ioremap_resource(pdev, 0);
739
738
if (IS_ERR(aspi->regs))
740
739
return PTR_ERR(aspi->regs);
741
740
742
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
743
-
aspi->ahb_base = devm_ioremap_resource(dev, res);
741
+
aspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
744
742
if (IS_ERR(aspi->ahb_base)) {
745
743
dev_err(dev, "missing AHB mapping window\n");
746
744
return PTR_ERR(aspi->ahb_base);
+2
-3
drivers/spi/spi-bcm-qspi.c
+2
-3
drivers/spi/spi-bcm-qspi.c
···
1682
1682
/* probe function to be called by SoC specific platform driver probe */
1683
1683
EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1684
1684
1685
-
int bcm_qspi_remove(struct platform_device *pdev)
1685
+
void bcm_qspi_remove(struct platform_device *pdev)
1686
1686
{
1687
1687
struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1688
1688
···
1690
1690
bcm_qspi_hw_uninit(qspi);
1691
1691
clk_disable_unprepare(qspi->clk);
1692
1692
kfree(qspi->dev_ids);
1693
-
1694
-
return 0;
1695
1693
}
1694
+
1696
1695
/* function to be called by SoC specific platform driver remove() */
1697
1696
EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1698
1697
+1
-1
drivers/spi/spi-bcm-qspi.h
+1
-1
drivers/spi/spi-bcm-qspi.h
···
96
96
/* The common driver functions to be called by the SoC platform driver */
97
97
int bcm_qspi_probe(struct platform_device *pdev,
98
98
struct bcm_qspi_soc_intc *soc_intc);
99
-
int bcm_qspi_remove(struct platform_device *pdev);
99
+
void bcm_qspi_remove(struct platform_device *pdev);
100
100
101
101
/* pm_ops used by the SoC platform driver called on PM suspend/resume */
102
102
extern const struct dev_pm_ops bcm_qspi_pm_ops;
+1
-2
drivers/spi/spi-bcm63xx.c
+1
-2
drivers/spi/spi-bcm63xx.c
···
547
547
platform_set_drvdata(pdev, master);
548
548
bs->pdev = pdev;
549
549
550
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
551
-
bs->regs = devm_ioremap_resource(&pdev->dev, r);
550
+
bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
552
551
if (IS_ERR(bs->regs)) {
553
552
ret = PTR_ERR(bs->regs);
554
553
goto out_err;
+3
-1
drivers/spi/spi-brcmstb-qspi.c
+3
-1
drivers/spi/spi-brcmstb-qspi.c
+10
-5
drivers/spi/spi-cadence-quadspi.c
+10
-5
drivers/spi/spi-cadence-quadspi.c
···
1119
1119
/* Recalculate the baudrate divisor based on QSPI specification. */
1120
1120
div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1121
1121
1122
+
/* Maximum baud divisor */
1123
+
if (div > CQSPI_REG_CONFIG_BAUD_MASK) {
1124
+
div = CQSPI_REG_CONFIG_BAUD_MASK;
1125
+
dev_warn(&cqspi->pdev->dev,
1126
+
"Unable to adjust clock <= %d hz. Reduced to %d hz\n",
1127
+
cqspi->sclk, ref_clk_hz/((div+1)*2));
1128
+
}
1129
+
1122
1130
reg = readl(reg_base + CQSPI_REG_CONFIG);
1123
1131
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
1124
1132
reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
···
1588
1580
struct spi_master *master;
1589
1581
struct resource *res_ahb;
1590
1582
struct cqspi_st *cqspi;
1591
-
struct resource *res;
1592
1583
int ret;
1593
1584
int irq;
1594
1585
···
1623
1616
}
1624
1617
1625
1618
/* Obtain and remap controller address. */
1626
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1627
-
cqspi->iobase = devm_ioremap_resource(dev, res);
1619
+
cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1628
1620
if (IS_ERR(cqspi->iobase)) {
1629
1621
dev_err(dev, "Cannot remap controller address.\n");
1630
1622
ret = PTR_ERR(cqspi->iobase);
···
1631
1625
}
1632
1626
1633
1627
/* Obtain and remap AHB address. */
1634
-
res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1635
-
cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1628
+
cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1636
1629
if (IS_ERR(cqspi->ahb_base)) {
1637
1630
dev_err(dev, "Cannot remap AHB address.\n");
1638
1631
ret = PTR_ERR(cqspi->ahb_base);
-4
drivers/spi/spi-cadence-xspi.c
-4
drivers/spi/spi-cadence-xspi.c
···
607
607
return 0;
608
608
}
609
609
610
-
#ifdef CONFIG_OF
611
610
static const struct of_device_id cdns_xspi_of_match[] = {
612
611
{
613
612
.compatible = "cdns,xspi-nor",
···
614
615
{ /* end of table */}
615
616
};
616
617
MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
617
-
#else
618
-
#define cdns_xspi_of_match NULL
619
-
#endif /* CONFIG_OF */
620
618
621
619
static struct platform_driver cdns_xspi_platform_driver = {
622
620
.probe = cdns_xspi_probe,
+1
-1
drivers/spi/spi-fsl-cpm.c
+1
-1
drivers/spi/spi-fsl-cpm.c
···
333
333
goto err_bds;
334
334
}
335
335
336
-
mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
336
+
mspi->dma_dummy_tx = dma_map_single(dev, ZERO_PAGE(0), PAGE_SIZE,
337
337
DMA_TO_DEVICE);
338
338
if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
339
339
dev_err(dev, "unable to map dummy tx buffer\n");
+34
-2
drivers/spi/spi-fsl-dspi.c
+34
-2
drivers/spi/spi-fsl-dspi.c
···
900
900
return IRQ_HANDLED;
901
901
}
902
902
903
+
static void dspi_assert_cs(struct spi_device *spi, bool *cs)
904
+
{
905
+
if (!spi->cs_gpiod || *cs)
906
+
return;
907
+
908
+
gpiod_set_value_cansleep(spi->cs_gpiod, true);
909
+
*cs = true;
910
+
}
911
+
912
+
static void dspi_deassert_cs(struct spi_device *spi, bool *cs)
913
+
{
914
+
if (!spi->cs_gpiod || !*cs)
915
+
return;
916
+
917
+
gpiod_set_value_cansleep(spi->cs_gpiod, false);
918
+
*cs = false;
919
+
}
920
+
903
921
static int dspi_transfer_one_message(struct spi_controller *ctlr,
904
922
struct spi_message *message)
905
923
{
906
924
struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
907
925
struct spi_device *spi = message->spi;
908
926
struct spi_transfer *transfer;
927
+
bool cs = false;
909
928
int status = 0;
910
929
911
930
message->actual_length = 0;
···
933
914
dspi->cur_transfer = transfer;
934
915
dspi->cur_msg = message;
935
916
dspi->cur_chip = spi_get_ctldata(spi);
917
+
918
+
dspi_assert_cs(spi, &cs);
919
+
936
920
/* Prepare command word for CMD FIFO */
937
-
dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
938
-
SPI_PUSHR_CMD_PCS(spi->chip_select);
921
+
dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0);
922
+
if (!spi->cs_gpiod)
923
+
dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi->chip_select);
924
+
939
925
if (list_is_last(&dspi->cur_transfer->transfer_list,
940
926
&dspi->cur_msg->transfers)) {
941
927
/* Leave PCS activated after last transfer when
···
988
964
break;
989
965
990
966
spi_transfer_delay_exec(transfer);
967
+
968
+
if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT))
969
+
dspi_deassert_cs(spi, &cs);
991
970
}
992
971
993
972
message->status = status;
···
1008
981
unsigned char pasc = 0, asc = 0;
1009
982
struct chip_data *chip;
1010
983
unsigned long clkrate;
984
+
bool cs = true;
1011
985
1012
986
/* Only alloc on first setup */
1013
987
chip = spi_get_ctldata(spi);
···
1057
1029
if (spi->mode & SPI_LSB_FIRST)
1058
1030
chip->ctar_val |= SPI_CTAR_LSBFE;
1059
1031
}
1032
+
1033
+
gpiod_direction_output(spi->cs_gpiod, false);
1034
+
dspi_deassert_cs(spi, &cs);
1060
1035
1061
1036
spi_set_ctldata(spi, chip);
1062
1037
···
1279
1248
ctlr->cleanup = dspi_cleanup;
1280
1249
ctlr->slave_abort = dspi_slave_abort;
1281
1250
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1251
+
ctlr->use_gpio_descriptors = true;
1282
1252
1283
1253
pdata = dev_get_platdata(&pdev->dev);
1284
1254
if (pdata) {
+5
drivers/spi/spi-fsl-lpspi.c
+5
drivers/spi/spi-fsl-lpspi.c
···
98
98
struct clk *clk_ipg;
99
99
struct clk *clk_per;
100
100
bool is_slave;
101
+
u32 num_cs;
101
102
bool is_only_cs1;
102
103
bool is_first_byte;
103
104
···
841
840
fsl_lpspi->is_slave = is_slave;
842
841
fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
843
842
"fsl,spi-only-use-cs1-sel");
843
+
if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
844
+
&fsl_lpspi->num_cs))
845
+
fsl_lpspi->num_cs = 1;
844
846
845
847
controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
846
848
controller->transfer_one = fsl_lpspi_transfer_one;
···
853
849
controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
854
850
controller->dev.of_node = pdev->dev.of_node;
855
851
controller->bus_num = pdev->id;
852
+
controller->num_chipselect = fsl_lpspi->num_cs;
856
853
controller->slave_abort = fsl_lpspi_slave_abort;
857
854
if (!fsl_lpspi->is_slave)
858
855
controller->use_gpio_descriptors = true;
+13
-3
drivers/spi/spi-gpio.c
+13
-3
drivers/spi/spi-gpio.c
···
268
268
if (output)
269
269
return gpiod_direction_output(spi_gpio->mosi, 1);
270
270
271
-
ret = gpiod_direction_input(spi_gpio->mosi);
272
-
if (ret)
273
-
return ret;
271
+
/*
272
+
* Only change MOSI to an input if using 3WIRE mode.
273
+
* Otherwise, MOSI could be left floating if there is
274
+
* no pull resistor connected to the I/O pin, or could
275
+
* be left logic high if there is a pull-up. Transmitting
276
+
* logic high when only clocking MISO data in can put some
277
+
* SPI devices in to a bad state.
278
+
*/
279
+
if (spi->mode & SPI_3WIRE) {
280
+
ret = gpiod_direction_input(spi_gpio->mosi);
281
+
if (ret)
282
+
return ret;
283
+
}
274
284
/*
275
285
* Send a turnaround high impedance cycle when switching
276
286
* from output to input. Theoretically there should be
+1
-1
drivers/spi/spi-hisi-sfc-v3xx.c
+1
-1
drivers/spi/spi-hisi-sfc-v3xx.c
···
165
165
}
166
166
167
167
/*
168
-
* The controller only supports Standard SPI mode, Duall mode and
168
+
* The controller only supports Standard SPI mode, Dual mode and
169
169
* Quad mode. Double sanitize the ops here to avoid OOB access.
170
170
*/
171
171
static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
+1
-2
drivers/spi/spi-img-spfi.c
+1
-2
drivers/spi/spi-img-spfi.c
···
540
540
spfi->master = master;
541
541
spin_lock_init(&spfi->lock);
542
542
543
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
544
-
spfi->regs = devm_ioremap_resource(spfi->dev, res);
543
+
spfi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
545
544
if (IS_ERR(spfi->regs)) {
546
545
ret = PTR_ERR(spfi->regs);
547
546
goto put_spi;
-8
drivers/spi/spi-imx.c
-8
drivers/spi/spi-imx.c
···
77
77
void (*reset)(struct spi_imx_data *spi_imx);
78
78
void (*setup_wml)(struct spi_imx_data *spi_imx);
79
79
void (*disable)(struct spi_imx_data *spi_imx);
80
-
void (*disable_dma)(struct spi_imx_data *spi_imx);
81
80
bool has_dmamode;
82
81
bool has_slavemode;
83
82
unsigned int fifo_size;
···
493
494
reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
494
495
reg |= MX51_ECSPI_CTRL_XCH;
495
496
writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
496
-
}
497
-
498
-
static void mx51_disable_dma(struct spi_imx_data *spi_imx)
499
-
{
500
-
writel(0, spi_imx->base + MX51_ECSPI_DMA);
501
497
}
502
498
503
499
static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
···
1036
1042
.rx_available = mx51_ecspi_rx_available,
1037
1043
.reset = mx51_ecspi_reset,
1038
1044
.setup_wml = mx51_setup_wml,
1039
-
.disable_dma = mx51_disable_dma,
1040
1045
.fifo_size = 64,
1041
1046
.has_dmamode = true,
1042
1047
.dynamic_burst = true,
···
1050
1057
.prepare_transfer = mx51_ecspi_prepare_transfer,
1051
1058
.trigger = mx51_ecspi_trigger,
1052
1059
.rx_available = mx51_ecspi_rx_available,
1053
-
.disable_dma = mx51_disable_dma,
1054
1060
.reset = mx51_ecspi_reset,
1055
1061
.fifo_size = 64,
1056
1062
.has_dmamode = true,
+40
-38
drivers/spi/spi-intel.c
+40
-38
drivers/spi/spi-intel.c
···
33
33
#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
34
34
#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
35
35
#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
36
+
#define HSFSTS_CTL_FCYCLE_RDSFDP (0x05 << HSFSTS_CTL_FCYCLE_SHIFT)
36
37
#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
37
38
#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
38
39
#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
···
353
352
return 0;
354
353
}
355
354
356
-
static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)
355
+
static int intel_spi_hw_cycle(struct intel_spi *ispi,
356
+
const struct intel_spi_mem_op *iop, size_t len)
357
357
{
358
358
u32 val, status;
359
359
int ret;
360
360
361
+
if (!iop->replacement_op)
362
+
return -EINVAL;
363
+
361
364
val = readl(ispi->base + HSFSTS_CTL);
362
365
val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
363
-
364
-
switch (opcode) {
365
-
case SPINOR_OP_RDID:
366
-
val |= HSFSTS_CTL_FCYCLE_RDID;
367
-
break;
368
-
case SPINOR_OP_WRSR:
369
-
val |= HSFSTS_CTL_FCYCLE_WRSR;
370
-
break;
371
-
case SPINOR_OP_RDSR:
372
-
val |= HSFSTS_CTL_FCYCLE_RDSR;
373
-
break;
374
-
default:
375
-
return -EINVAL;
376
-
}
377
-
378
-
if (len > INTEL_SPI_FIFO_SZ)
379
-
return -EINVAL;
380
-
381
366
val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
382
367
val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
383
368
val |= HSFSTS_CTL_FGO;
369
+
val |= iop->replacement_op;
384
370
writel(val, ispi->base + HSFSTS_CTL);
385
371
386
372
ret = intel_spi_wait_hw_busy(ispi);
···
393
405
ret = intel_spi_opcode_index(ispi, opcode, optype);
394
406
if (ret < 0)
395
407
return ret;
396
-
397
-
if (len > INTEL_SPI_FIFO_SZ)
398
-
return -EINVAL;
399
408
400
409
/*
401
410
* Always clear it after each SW sequencer operation regardless
···
458
473
const struct intel_spi_mem_op *iop,
459
474
const struct spi_mem_op *op)
460
475
{
476
+
u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
461
477
size_t nbytes = op->data.nbytes;
462
478
u8 opcode = op->cmd.opcode;
463
479
int ret;
464
480
465
-
writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);
481
+
writel(addr, ispi->base + FADDR);
466
482
467
483
if (ispi->swseq_reg)
468
484
ret = intel_spi_sw_cycle(ispi, opcode, nbytes,
469
485
OPTYPE_READ_NO_ADDR);
470
486
else
471
-
ret = intel_spi_hw_cycle(ispi, opcode, nbytes);
487
+
ret = intel_spi_hw_cycle(ispi, iop, nbytes);
472
488
473
489
if (ret)
474
490
return ret;
···
481
495
const struct intel_spi_mem_op *iop,
482
496
const struct spi_mem_op *op)
483
497
{
498
+
u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
484
499
size_t nbytes = op->data.nbytes;
485
500
u8 opcode = op->cmd.opcode;
486
501
int ret;
···
525
538
if (opcode == SPINOR_OP_WRDI)
526
539
return 0;
527
540
528
-
writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);
541
+
writel(addr, ispi->base + FADDR);
529
542
530
543
/* Write the value beforehand */
531
544
ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);
···
535
548
if (ispi->swseq_reg)
536
549
return intel_spi_sw_cycle(ispi, opcode, nbytes,
537
550
OPTYPE_WRITE_NO_ADDR);
538
-
return intel_spi_hw_cycle(ispi, opcode, nbytes);
551
+
return intel_spi_hw_cycle(ispi, iop, nbytes);
539
552
}
540
553
541
554
static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,
···
700
713
return 0;
701
714
}
702
715
716
+
static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
717
+
{
718
+
op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ);
719
+
return 0;
720
+
}
721
+
703
722
static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop,
704
723
const struct spi_mem_op *op)
705
724
{
···
846
853
}
847
854
848
855
static const struct spi_controller_mem_ops intel_spi_mem_ops = {
856
+
.adjust_op_size = intel_spi_adjust_op_size,
849
857
.supports_op = intel_spi_supports_mem_op,
850
858
.exec_op = intel_spi_exec_mem_op,
851
859
.get_name = intel_spi_get_name,
···
906
912
*/
907
913
#define INTEL_SPI_GENERIC_OPS \
908
914
/* Status register operations */ \
909
-
INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \
910
-
SPI_MEM_OP_NO_ADDR, \
911
-
INTEL_SPI_OP_DATA_IN(1), \
912
-
intel_spi_read_reg), \
913
-
INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \
914
-
SPI_MEM_OP_NO_ADDR, \
915
-
INTEL_SPI_OP_DATA_IN(1), \
916
-
intel_spi_read_reg), \
917
-
INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \
918
-
SPI_MEM_OP_NO_ADDR, \
919
-
INTEL_SPI_OP_DATA_OUT(1), \
920
-
intel_spi_write_reg), \
915
+
INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \
916
+
SPI_MEM_OP_NO_ADDR, \
917
+
INTEL_SPI_OP_DATA_IN(1), \
918
+
intel_spi_read_reg, \
919
+
HSFSTS_CTL_FCYCLE_RDID), \
920
+
INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \
921
+
SPI_MEM_OP_NO_ADDR, \
922
+
INTEL_SPI_OP_DATA_IN(1), \
923
+
intel_spi_read_reg, \
924
+
HSFSTS_CTL_FCYCLE_RDSR), \
925
+
INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \
926
+
SPI_MEM_OP_NO_ADDR, \
927
+
INTEL_SPI_OP_DATA_OUT(1), \
928
+
intel_spi_write_reg, \
929
+
HSFSTS_CTL_FCYCLE_WRSR), \
930
+
INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSFDP, 1), \
931
+
INTEL_SPI_OP_ADDR(3), \
932
+
INTEL_SPI_OP_DATA_IN(1), \
933
+
intel_spi_read_reg, \
934
+
HSFSTS_CTL_FCYCLE_RDSFDP), \
921
935
/* Normal read */ \
922
936
INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \
923
937
INTEL_SPI_OP_ADDR(3), \
+3
-1
drivers/spi/spi-iproc-qspi.c
+3
-1
drivers/spi/spi-iproc-qspi.c
+38
-1
drivers/spi/spi-meson-spicc.c
+38
-1
drivers/spi/spi-meson-spicc.c
···
21
21
#include <linux/types.h>
22
22
#include <linux/interrupt.h>
23
23
#include <linux/reset.h>
24
+
#include <linux/pinctrl/consumer.h>
24
25
25
26
/*
26
27
* The Meson SPICC controller could support DMA based transfers, but is not
···
169
168
unsigned long tx_remain;
170
169
unsigned long rx_remain;
171
170
unsigned long xfer_remain;
171
+
struct pinctrl *pinctrl;
172
+
struct pinctrl_state *pins_idle_high;
173
+
struct pinctrl_state *pins_idle_low;
172
174
};
173
175
174
176
#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
···
180
176
{
181
177
u32 conf;
182
178
183
-
if (!spicc->data->has_oen)
179
+
if (!spicc->data->has_oen) {
180
+
/* Try to get pinctrl states for idle high/low */
181
+
spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,
182
+
"idle-high");
183
+
if (IS_ERR(spicc->pins_idle_high)) {
184
+
dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");
185
+
spicc->pins_idle_high = NULL;
186
+
}
187
+
spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,
188
+
"idle-low");
189
+
if (IS_ERR(spicc->pins_idle_low)) {
190
+
dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");
191
+
spicc->pins_idle_low = NULL;
192
+
}
184
193
return;
194
+
}
185
195
186
196
conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
187
197
SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
···
477
459
else
478
460
conf &= ~SPICC_POL;
479
461
462
+
if (!spicc->data->has_oen) {
463
+
if (spi->mode & SPI_CPOL) {
464
+
if (spicc->pins_idle_high)
465
+
pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);
466
+
} else {
467
+
if (spicc->pins_idle_low)
468
+
pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);
469
+
}
470
+
}
471
+
480
472
if (spi->mode & SPI_CPHA)
481
473
conf |= SPICC_PHA;
482
474
else
···
532
504
533
505
/* Set default configuration, keeping datarate field */
534
506
writel_relaxed(conf, spicc->base + SPICC_CONREG);
507
+
508
+
if (!spicc->data->has_oen)
509
+
pinctrl_select_default_state(&spicc->pdev->dev);
535
510
536
511
return 0;
537
512
}
···
847
816
if (ret) {
848
817
dev_err(&pdev->dev, "pclk clock enable failed\n");
849
818
goto out_core_clk;
819
+
}
820
+
821
+
spicc->pinctrl = devm_pinctrl_get(&pdev->dev);
822
+
if (IS_ERR(spicc->pinctrl)) {
823
+
ret = PTR_ERR(spicc->pinctrl);
824
+
goto out_clk;
850
825
}
851
826
852
827
device_reset_optional(&pdev->dev);
-9
drivers/spi/spi-microchip-core.c
-9
drivers/spi/spi-microchip-core.c
···
119
119
writel(val, spi->regs + reg);
120
120
}
121
121
122
-
static inline void mchp_corespi_enable(struct mchp_corespi *spi)
123
-
{
124
-
u32 control = mchp_corespi_read(spi, REG_CONTROL);
125
-
126
-
control |= CONTROL_ENABLE;
127
-
128
-
mchp_corespi_write(spi, REG_CONTROL, control);
129
-
}
130
-
131
122
static inline void mchp_corespi_disable(struct mchp_corespi *spi)
132
123
{
133
124
u32 control = mchp_corespi_read(spi, REG_CONTROL);
+7
-5
drivers/spi/spi-mt65xx.c
+7
-5
drivers/spi/spi-mt65xx.c
···
1192
1192
else
1193
1193
dma_set_max_seg_size(dev, SZ_256K);
1194
1194
1195
-
ret = devm_request_irq(dev, irq, mtk_spi_interrupt,
1196
-
IRQF_TRIGGER_NONE, dev_name(dev), master);
1197
-
if (ret)
1198
-
return dev_err_probe(dev, ret, "failed to register irq\n");
1199
-
1200
1195
mdata->parent_clk = devm_clk_get(dev, "parent-clk");
1201
1196
if (IS_ERR(mdata->parent_clk))
1202
1197
return dev_err_probe(dev, PTR_ERR(mdata->parent_clk),
···
1259
1264
if (ret) {
1260
1265
pm_runtime_disable(dev);
1261
1266
return dev_err_probe(dev, ret, "failed to register master\n");
1267
+
}
1268
+
1269
+
ret = devm_request_irq(dev, irq, mtk_spi_interrupt,
1270
+
IRQF_TRIGGER_NONE, dev_name(dev), master);
1271
+
if (ret) {
1272
+
pm_runtime_disable(dev);
1273
+
return dev_err_probe(dev, ret, "failed to register irq\n");
1262
1274
}
1263
1275
1264
1276
return 0;
+41
-28
drivers/spi/spi-mtk-nor.c
+41
-28
drivers/spi/spi-mtk-nor.c
···
80
80
#define MTK_NOR_REG_DMA_FADR 0x71c
81
81
#define MTK_NOR_REG_DMA_DADR 0x720
82
82
#define MTK_NOR_REG_DMA_END_DADR 0x724
83
+
#define MTK_NOR_REG_CG_DIS 0x728
84
+
#define MTK_NOR_SFC_SW_RST BIT(2)
85
+
83
86
#define MTK_NOR_REG_DMA_DADR_HB 0x738
84
87
#define MTK_NOR_REG_DMA_END_DADR_HB 0x73c
85
88
···
148
145
if (ret < 0)
149
146
dev_err(sp->dev, "command %u timeout.\n", cmd);
150
147
return ret;
148
+
}
149
+
150
+
static void mtk_nor_reset(struct mtk_nor *sp)
151
+
{
152
+
mtk_nor_rmw(sp, MTK_NOR_REG_CG_DIS, 0, MTK_NOR_SFC_SW_RST);
153
+
mb(); /* flush previous writes */
154
+
mtk_nor_rmw(sp, MTK_NOR_REG_CG_DIS, MTK_NOR_SFC_SW_RST, 0);
155
+
mb(); /* flush previous writes */
156
+
writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP);
151
157
}
152
158
153
159
static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op)
···
366
354
dma_addr_t dma_addr)
367
355
{
368
356
int ret = 0;
369
-
ulong delay;
357
+
u32 delay, timeout;
370
358
u32 reg;
371
359
372
360
writel(from, sp->base + MTK_NOR_REG_DMA_FADR);
···
388
376
mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
389
377
390
378
delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE);
379
+
timeout = (delay + 1) * 100;
391
380
392
381
if (sp->has_irq) {
393
382
if (!wait_for_completion_timeout(&sp->op_done,
394
-
(delay + 1) * 100))
383
+
usecs_to_jiffies(max(timeout, 10000U))))
395
384
ret = -ETIMEDOUT;
396
385
} else {
397
386
ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg,
398
387
!(reg & MTK_NOR_DMA_START), delay / 3,
399
-
(delay + 1) * 100);
388
+
timeout);
400
389
}
401
390
402
391
if (ret < 0)
···
456
443
return ret;
457
444
}
458
445
459
-
static int mtk_nor_write_buffer_enable(struct mtk_nor *sp)
446
+
static int mtk_nor_setup_write_buffer(struct mtk_nor *sp, bool on)
460
447
{
461
448
int ret;
462
449
u32 val;
463
450
464
-
if (sp->wbuf_en)
451
+
if (!(sp->wbuf_en ^ on))
465
452
return 0;
466
453
467
454
val = readl(sp->base + MTK_NOR_REG_CFG2);
468
-
writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
469
-
ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
470
-
val & MTK_NOR_WR_BUF_EN, 0, 10000);
471
-
if (!ret)
472
-
sp->wbuf_en = true;
473
-
return ret;
474
-
}
455
+
if (on) {
456
+
writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
457
+
ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
458
+
val & MTK_NOR_WR_BUF_EN, 0, 10000);
459
+
} else {
460
+
writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
461
+
ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
462
+
!(val & MTK_NOR_WR_BUF_EN), 0, 10000);
463
+
}
475
464
476
-
static int mtk_nor_write_buffer_disable(struct mtk_nor *sp)
477
-
{
478
-
int ret;
479
-
u32 val;
480
-
481
-
if (!sp->wbuf_en)
482
-
return 0;
483
-
val = readl(sp->base + MTK_NOR_REG_CFG2);
484
-
writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2);
485
-
ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val,
486
-
!(val & MTK_NOR_WR_BUF_EN), 0, 10000);
487
465
if (!ret)
488
-
sp->wbuf_en = false;
466
+
sp->wbuf_en = on;
467
+
489
468
return ret;
490
469
}
491
470
···
487
482
u32 val;
488
483
int ret, i;
489
484
490
-
ret = mtk_nor_write_buffer_enable(sp);
485
+
ret = mtk_nor_setup_write_buffer(sp, true);
491
486
if (ret < 0)
492
487
return ret;
493
488
···
506
501
const u8 *buf = op->data.buf.out;
507
502
int ret;
508
503
509
-
ret = mtk_nor_write_buffer_disable(sp);
504
+
ret = mtk_nor_setup_write_buffer(sp, false);
510
505
if (ret < 0)
511
506
return ret;
512
507
writeb(buf[0], sp->base + MTK_NOR_REG_WDATA);
···
613
608
}
614
609
615
610
if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) {
616
-
ret = mtk_nor_write_buffer_disable(sp);
611
+
ret = mtk_nor_setup_write_buffer(sp, false);
617
612
if (ret < 0)
618
613
return ret;
619
614
mtk_nor_setup_bus(sp, op);
···
621
616
mtk_nor_set_addr(sp, op);
622
617
return mtk_nor_read_pio(sp, op);
623
618
} else {
624
-
return mtk_nor_read_dma(sp, op);
619
+
ret = mtk_nor_read_dma(sp, op);
620
+
if (unlikely(ret)) {
621
+
/* Handle rare bus glitch */
622
+
mtk_nor_reset(sp);
623
+
mtk_nor_setup_bus(sp, op);
624
+
return mtk_nor_read_dma(sp, op);
625
+
}
626
+
627
+
return ret;
625
628
}
626
629
}
627
630
+27
-2
drivers/spi/spi-mtk-snfi.c
+27
-2
drivers/spi/spi-mtk-snfi.c
···
126
126
#define STR_DATA BIT(0)
127
127
128
128
#define NFI_STA 0x060
129
-
#define NFI_NAND_FSM GENMASK(28, 24)
129
+
#define NFI_NAND_FSM_7622 GENMASK(28, 24)
130
+
#define NFI_NAND_FSM_7986 GENMASK(29, 23)
130
131
#define NFI_FSM GENMASK(19, 16)
131
132
#define READ_EMPTY BIT(12)
132
133
···
159
158
#define MAS_WR GENMASK(5, 3)
160
159
#define MAS_RDDLY GENMASK(2, 0)
161
160
#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)
161
+
#define NFI_MASTERSTA_MASK_7986 3
162
162
163
163
// SNFI registers
164
164
#define SNF_MAC_CTL 0x500
···
222
220
223
221
static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };
224
222
223
+
static const u8 mt7986_spare_sizes[] = {
224
+
16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, 67,
225
+
74
226
+
};
227
+
225
228
struct mtk_snand_caps {
226
229
u16 sector_size;
227
230
u16 max_sectors;
···
237
230
bool bbm_swap;
238
231
bool empty_page_check;
239
232
u32 mastersta_mask;
233
+
u32 nandfsm_mask;
240
234
241
235
const u8 *spare_sizes;
242
236
u32 num_spare_size;
···
252
244
.bbm_swap = false,
253
245
.empty_page_check = false,
254
246
.mastersta_mask = NFI_MASTERSTA_MASK_7622,
247
+
.nandfsm_mask = NFI_NAND_FSM_7622,
255
248
.spare_sizes = mt7622_spare_sizes,
256
249
.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
257
250
};
···
266
257
.bbm_swap = true,
267
258
.empty_page_check = false,
268
259
.mastersta_mask = NFI_MASTERSTA_MASK_7622,
260
+
.nandfsm_mask = NFI_NAND_FSM_7622,
269
261
.spare_sizes = mt7622_spare_sizes,
270
262
.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)
263
+
};
264
+
265
+
static const struct mtk_snand_caps mt7986_snand_caps = {
266
+
.sector_size = 1024,
267
+
.max_sectors = 8,
268
+
.fdm_size = 8,
269
+
.fdm_ecc_size = 1,
270
+
.fifo_size = 64,
271
+
.bbm_swap = true,
272
+
.empty_page_check = true,
273
+
.mastersta_mask = NFI_MASTERSTA_MASK_7986,
274
+
.nandfsm_mask = NFI_NAND_FSM_7986,
275
+
.spare_sizes = mt7986_spare_sizes,
276
+
.num_spare_size = ARRAY_SIZE(mt7986_spare_sizes)
271
277
};
272
278
273
279
struct mtk_snand_conf {
···
384
360
}
385
361
386
362
ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,
387
-
!(val & (NFI_FSM | NFI_NAND_FSM)), 0,
363
+
!(val & (NFI_FSM | snf->caps->nandfsm_mask)), 0,
388
364
SNFI_POLL_INTERVAL);
389
365
if (ret) {
390
366
dev_err(snf->dev, "Failed to reset NFI\n");
···
1319
1295
static const struct of_device_id mtk_snand_ids[] = {
1320
1296
{ .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps },
1321
1297
{ .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps },
1298
+
{ .compatible = "mediatek,mt7986-snand", .data = &mt7986_snand_caps },
1322
1299
{},
1323
1300
};
1324
1301
+1
-2
drivers/spi/spi-mxic.c
+1
-2
drivers/spi/spi-mxic.c
···
772
772
if (IS_ERR(mxic->send_dly_clk))
773
773
return PTR_ERR(mxic->send_dly_clk);
774
774
775
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
776
-
mxic->regs = devm_ioremap_resource(&pdev->dev, res);
775
+
mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs");
777
776
if (IS_ERR(mxic->regs))
778
777
return PTR_ERR(mxic->regs);
779
778
+1
-3
drivers/spi/spi-npcm-fiu.c
+1
-3
drivers/spi/spi-npcm-fiu.c
···
699
699
struct spi_controller *ctrl;
700
700
struct npcm_fiu_spi *fiu;
701
701
void __iomem *regbase;
702
-
struct resource *res;
703
702
int id, ret;
704
703
705
704
ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
···
724
725
platform_set_drvdata(pdev, fiu);
725
726
fiu->dev = dev;
726
727
727
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
728
-
regbase = devm_ioremap_resource(dev, res);
728
+
regbase = devm_platform_ioremap_resource_byname(pdev, "control");
729
729
if (IS_ERR(regbase))
730
730
return PTR_ERR(regbase);
731
731
+1
-1
drivers/spi/spi-nxp-fspi.c
+1
-1
drivers/spi/spi-nxp-fspi.c
+475
drivers/spi/spi-pci1xxxx.c
+475
drivers/spi/spi-pci1xxxx.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
// PCI1xxxx SPI driver
3
+
// Copyright (C) 2022 Microchip Technology Inc.
4
+
// Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>
5
+
// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>
6
+
7
+
8
+
#include <linux/module.h>
9
+
#include <linux/pci.h>
10
+
#include <linux/spi/spi.h>
11
+
#include <linux/delay.h>
12
+
13
+
#define DRV_NAME "spi-pci1xxxx"
14
+
15
+
#define SYS_FREQ_DEFAULT (62500000)
16
+
17
+
#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000)
18
+
#define PCI1XXXX_SPI_CLK_20MHZ (20000000)
19
+
#define PCI1XXXX_SPI_CLK_15MHZ (15000000)
20
+
#define PCI1XXXX_SPI_CLK_12MHZ (12000000)
21
+
#define PCI1XXXX_SPI_CLK_10MHZ (10000000)
22
+
#define PCI1XXXX_SPI_MIN_CLOCK_HZ (2000000)
23
+
24
+
#define PCI1XXXX_SPI_BUFFER_SIZE (320)
25
+
26
+
#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25))
27
+
#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8))
28
+
#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5))
29
+
#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4))
30
+
31
+
#define SPI_MST_CTL_FORCE_CE (BIT(4))
32
+
#define SPI_MST_CTL_MODE_SEL (BIT(2))
33
+
#define SPI_MST_CTL_GO (BIT(0))
34
+
35
+
#define SPI_MST1_ADDR_BASE (0x800)
36
+
37
+
/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
38
+
39
+
#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00)
40
+
#define SPI_MST_RSP_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x200)
41
+
#define SPI_MST_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x400)
42
+
#define SPI_MST_EVENT_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x420)
43
+
#define SPI_MST_EVENT_MASK_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x424)
44
+
#define SPI_MST_PAD_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x460)
45
+
#define SPIALERT_MST_DB_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x464)
46
+
#define SPIALERT_MST_VAL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x468)
47
+
#define SPI_PCI_CTRL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x480)
48
+
49
+
#define PCI1XXXX_IRQ_FLAGS (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE)
50
+
#define SPI_MAX_DATA_LEN 320
51
+
52
+
#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100))
53
+
54
+
#define SPI_INTR BIT(8)
55
+
#define SPI_FORCE_CE BIT(4)
56
+
57
+
#define SPI_CHIP_SEL_COUNT 7
58
+
#define VENDOR_ID_MCHP 0x1055
59
+
60
+
#define SPI_SUSPEND_CONFIG 0x101
61
+
#define SPI_RESUME_CONFIG 0x303
62
+
63
+
struct pci1xxxx_spi_internal {
64
+
u8 hw_inst;
65
+
bool spi_xfer_in_progress;
66
+
int irq;
67
+
struct completion spi_xfer_done;
68
+
struct spi_master *spi_host;
69
+
struct pci1xxxx_spi *parent;
70
+
struct {
71
+
unsigned int dev_sel : 3;
72
+
unsigned int msi_vector_sel : 1;
73
+
} prev_val;
74
+
};
75
+
76
+
struct pci1xxxx_spi {
77
+
struct pci_dev *dev;
78
+
u8 total_hw_instances;
79
+
void __iomem *reg_base;
80
+
struct pci1xxxx_spi_internal *spi_int[];
81
+
};
82
+
83
+
static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = {
84
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
85
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
86
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
87
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
88
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
89
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
90
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
91
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
92
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
93
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
94
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
95
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
96
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
97
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
98
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
99
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
100
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02},
101
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01},
102
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11},
103
+
{ PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},
104
+
{ 0, }
105
+
};
106
+
107
+
MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table);
108
+
109
+
static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
110
+
{
111
+
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller);
112
+
struct pci1xxxx_spi *par = p->parent;
113
+
u32 regval;
114
+
115
+
/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
116
+
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
117
+
if (enable) {
118
+
regval &= ~SPI_MST_CTL_DEVSEL_MASK;
119
+
regval |= (spi->chip_select << 25);
120
+
writel(regval,
121
+
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
122
+
} else {
123
+
regval &= ~(spi->chip_select << 25);
124
+
writel(regval,
125
+
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
126
+
127
+
}
128
+
}
129
+
130
+
static u8 pci1xxxx_get_clock_div(u32 hz)
131
+
{
132
+
u8 val = 0;
133
+
134
+
if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ)
135
+
val = 2;
136
+
else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ))
137
+
val = 3;
138
+
else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ))
139
+
val = 4;
140
+
else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >= PCI1XXXX_SPI_CLK_12MHZ))
141
+
val = 5;
142
+
else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >= PCI1XXXX_SPI_CLK_10MHZ))
143
+
val = 6;
144
+
else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >= PCI1XXXX_SPI_MIN_CLOCK_HZ))
145
+
val = 7;
146
+
else
147
+
val = 2;
148
+
149
+
return val;
150
+
}
151
+
152
+
static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
153
+
struct spi_device *spi, struct spi_transfer *xfer)
154
+
{
155
+
struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);
156
+
int mode, len, loop_iter, transfer_len;
157
+
struct pci1xxxx_spi *par = p->parent;
158
+
unsigned long bytes_transfered;
159
+
unsigned long bytes_recvd;
160
+
unsigned long loop_count;
161
+
u8 *rx_buf, result;
162
+
const u8 *tx_buf;
163
+
u32 regval;
164
+
u8 clkdiv;
165
+
166
+
p->spi_xfer_in_progress = true;
167
+
mode = spi->mode;
168
+
clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);
169
+
tx_buf = xfer->tx_buf;
170
+
rx_buf = xfer->rx_buf;
171
+
transfer_len = xfer->len;
172
+
regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
173
+
writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
174
+
175
+
if (tx_buf) {
176
+
bytes_transfered = 0;
177
+
bytes_recvd = 0;
178
+
loop_count = transfer_len / SPI_MAX_DATA_LEN;
179
+
if (transfer_len % SPI_MAX_DATA_LEN != 0)
180
+
loop_count += 1;
181
+
182
+
for (loop_iter = 0; loop_iter < loop_count; loop_iter++) {
183
+
len = SPI_MAX_DATA_LEN;
184
+
if ((transfer_len % SPI_MAX_DATA_LEN != 0) &&
185
+
(loop_iter == loop_count - 1))
186
+
len = transfer_len % SPI_MAX_DATA_LEN;
187
+
188
+
reinit_completion(&p->spi_xfer_done);
189
+
memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),
190
+
&tx_buf[bytes_transfered], len);
191
+
bytes_transfered += len;
192
+
regval = readl(par->reg_base +
193
+
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
194
+
regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |
195
+
SPI_MST_CTL_SPEED_MASK);
196
+
197
+
if (mode == SPI_MODE_3)
198
+
regval |= SPI_MST_CTL_MODE_SEL;
199
+
else
200
+
regval &= ~SPI_MST_CTL_MODE_SEL;
201
+
202
+
regval |= ((clkdiv << 5) | SPI_FORCE_CE | (len << 8));
203
+
regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
204
+
writel(regval, par->reg_base +
205
+
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
206
+
regval = readl(par->reg_base +
207
+
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
208
+
regval |= SPI_MST_CTL_GO;
209
+
writel(regval, par->reg_base +
210
+
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
211
+
212
+
/* Wait for DMA_TERM interrupt */
213
+
result = wait_for_completion_timeout(&p->spi_xfer_done,
214
+
PCI1XXXX_SPI_TIMEOUT);
215
+
if (!result)
216
+
return -ETIMEDOUT;
217
+
218
+
if (rx_buf) {
219
+
memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base +
220
+
SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len);
221
+
bytes_recvd += len;
222
+
}
223
+
}
224
+
}
225
+
226
+
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
227
+
regval &= ~SPI_FORCE_CE;
228
+
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
229
+
p->spi_xfer_in_progress = false;
230
+
231
+
return 0;
232
+
}
233
+
234
+
static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)
235
+
{
236
+
struct pci1xxxx_spi_internal *p = dev;
237
+
irqreturn_t spi_int_fired = IRQ_NONE;
238
+
u32 regval;
239
+
240
+
/* Clear the SPI GO_BIT Interrupt */
241
+
regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
242
+
if (regval & SPI_INTR) {
243
+
/* Clear xfer_done */
244
+
complete(&p->spi_xfer_done);
245
+
spi_int_fired = IRQ_HANDLED;
246
+
}
247
+
248
+
writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));
249
+
250
+
return spi_int_fired;
251
+
}
252
+
253
+
static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
254
+
{
255
+
u8 hw_inst_cnt, iter, start, only_sec_inst;
256
+
struct pci1xxxx_spi_internal *spi_sub_ptr;
257
+
struct device *dev = &pdev->dev;
258
+
struct pci1xxxx_spi *spi_bus;
259
+
struct spi_master *spi_host;
260
+
u32 regval;
261
+
int ret;
262
+
263
+
hw_inst_cnt = ent->driver_data & 0x0f;
264
+
start = (ent->driver_data & 0xf0) >> 4;
265
+
if (start == 1)
266
+
only_sec_inst = 1;
267
+
else
268
+
only_sec_inst = 0;
269
+
270
+
spi_bus = devm_kzalloc(&pdev->dev,
271
+
struct_size(spi_bus, spi_int, hw_inst_cnt),
272
+
GFP_KERNEL);
273
+
if (!spi_bus)
274
+
return -ENOMEM;
275
+
276
+
spi_bus->dev = pdev;
277
+
spi_bus->total_hw_instances = hw_inst_cnt;
278
+
pci_set_master(pdev);
279
+
280
+
for (iter = 0; iter < hw_inst_cnt; iter++) {
281
+
spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev,
282
+
sizeof(struct pci1xxxx_spi_internal),
283
+
GFP_KERNEL);
284
+
spi_sub_ptr = spi_bus->spi_int[iter];
285
+
spi_sub_ptr->spi_host = devm_spi_alloc_master(dev, sizeof(struct spi_master));
286
+
if (!spi_sub_ptr->spi_host)
287
+
return -ENOMEM;
288
+
289
+
spi_sub_ptr->parent = spi_bus;
290
+
spi_sub_ptr->spi_xfer_in_progress = false;
291
+
292
+
if (!iter) {
293
+
ret = pcim_enable_device(pdev);
294
+
if (ret)
295
+
return -ENOMEM;
296
+
297
+
ret = pci_request_regions(pdev, DRV_NAME);
298
+
if (ret)
299
+
return -ENOMEM;
300
+
301
+
spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
302
+
if (!spi_bus->reg_base) {
303
+
ret = -EINVAL;
304
+
goto error;
305
+
}
306
+
307
+
ret = pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt,
308
+
PCI_IRQ_ALL_TYPES);
309
+
if (ret < 0) {
310
+
dev_err(&pdev->dev, "Error allocating MSI vectors\n");
311
+
goto error;
312
+
}
313
+
314
+
init_completion(&spi_sub_ptr->spi_xfer_done);
315
+
/* Initialize Interrupts - SPI_INT */
316
+
regval = readl(spi_bus->reg_base +
317
+
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
318
+
regval &= ~SPI_INTR;
319
+
writel(regval, spi_bus->reg_base +
320
+
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
321
+
spi_sub_ptr->irq = pci_irq_vector(pdev, 0);
322
+
323
+
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
324
+
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
325
+
pci_name(pdev), spi_sub_ptr);
326
+
if (ret < 0) {
327
+
dev_err(&pdev->dev, "Unable to request irq : %d",
328
+
spi_sub_ptr->irq);
329
+
ret = -ENODEV;
330
+
goto error;
331
+
}
332
+
333
+
/* This register is only applicable for 1st instance */
334
+
regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
335
+
if (!only_sec_inst)
336
+
regval |= (BIT(4));
337
+
else
338
+
regval &= ~(BIT(4));
339
+
340
+
writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));
341
+
}
342
+
343
+
spi_sub_ptr->hw_inst = start++;
344
+
345
+
if (iter == 1) {
346
+
init_completion(&spi_sub_ptr->spi_xfer_done);
347
+
/* Initialize Interrupts - SPI_INT */
348
+
regval = readl(spi_bus->reg_base +
349
+
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
350
+
regval &= ~SPI_INTR;
351
+
writel(regval, spi_bus->reg_base +
352
+
SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));
353
+
spi_sub_ptr->irq = pci_irq_vector(pdev, iter);
354
+
ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,
355
+
pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,
356
+
pci_name(pdev), spi_sub_ptr);
357
+
if (ret < 0) {
358
+
dev_err(&pdev->dev, "Unable to request irq : %d",
359
+
spi_sub_ptr->irq);
360
+
ret = -ENODEV;
361
+
goto error;
362
+
}
363
+
}
364
+
365
+
spi_host = spi_sub_ptr->spi_host;
366
+
spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;
367
+
spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |
368
+
SPI_TX_DUAL | SPI_LOOP;
369
+
spi_host->transfer_one = pci1xxxx_spi_transfer_one;
370
+
spi_host->set_cs = pci1xxxx_spi_set_cs;
371
+
spi_host->bits_per_word_mask = SPI_BPW_MASK(8);
372
+
spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;
373
+
spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;
374
+
spi_host->flags = SPI_MASTER_MUST_TX;
375
+
spi_master_set_devdata(spi_host, spi_sub_ptr);
376
+
ret = devm_spi_register_master(dev, spi_host);
377
+
if (ret)
378
+
goto error;
379
+
}
380
+
pci_set_drvdata(pdev, spi_bus);
381
+
382
+
return 0;
383
+
384
+
error:
385
+
pci_release_regions(pdev);
386
+
return ret;
387
+
}
388
+
389
+
static void store_restore_config(struct pci1xxxx_spi *spi_ptr,
390
+
struct pci1xxxx_spi_internal *spi_sub_ptr,
391
+
u8 inst, bool store)
392
+
{
393
+
u32 regval;
394
+
395
+
if (store) {
396
+
regval = readl(spi_ptr->reg_base +
397
+
SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));
398
+
regval &= SPI_MST_CTL_DEVSEL_MASK;
399
+
spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;
400
+
regval = readl(spi_ptr->reg_base +
401
+
SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));
402
+
regval &= SPI_MSI_VECTOR_SEL_MASK;
403
+
spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;
404
+
} else {
405
+
regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
406
+
regval &= ~SPI_MST_CTL_DEVSEL_MASK;
407
+
regval |= (spi_sub_ptr->prev_val.dev_sel << 25);
408
+
writel(regval,
409
+
spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));
410
+
writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),
411
+
spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));
412
+
}
413
+
}
414
+
415
+
static int pci1xxxx_spi_resume(struct device *dev)
416
+
{
417
+
struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
418
+
struct pci1xxxx_spi_internal *spi_sub_ptr;
419
+
u32 regval = SPI_RESUME_CONFIG;
420
+
u8 iter;
421
+
422
+
for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
423
+
spi_sub_ptr = spi_ptr->spi_int[iter];
424
+
spi_master_resume(spi_sub_ptr->spi_host);
425
+
writel(regval, spi_ptr->reg_base +
426
+
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
427
+
428
+
/* Restore config at resume */
429
+
store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);
430
+
}
431
+
432
+
return 0;
433
+
}
434
+
435
+
static int pci1xxxx_spi_suspend(struct device *dev)
436
+
{
437
+
struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);
438
+
struct pci1xxxx_spi_internal *spi_sub_ptr;
439
+
u32 reg1 = SPI_SUSPEND_CONFIG;
440
+
u8 iter;
441
+
442
+
for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {
443
+
spi_sub_ptr = spi_ptr->spi_int[iter];
444
+
445
+
while (spi_sub_ptr->spi_xfer_in_progress)
446
+
msleep(20);
447
+
448
+
/* Store existing config before suspend */
449
+
store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);
450
+
spi_master_suspend(spi_sub_ptr->spi_host);
451
+
writel(reg1, spi_ptr->reg_base +
452
+
SPI_MST_EVENT_MASK_REG_OFFSET(iter));
453
+
}
454
+
455
+
return 0;
456
+
}
457
+
458
+
static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,
459
+
pci1xxxx_spi_resume);
460
+
461
+
static struct pci_driver pci1xxxx_spi_driver = {
462
+
.name = DRV_NAME,
463
+
.id_table = pci1xxxx_spi_pci_id_table,
464
+
.probe = pci1xxxx_spi_probe,
465
+
.driver = {
466
+
.pm = pm_sleep_ptr(&spi_pm_ops),
467
+
},
468
+
};
469
+
470
+
module_pci_driver(pci1xxxx_spi_driver);
471
+
472
+
MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver");
473
+
MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>");
474
+
MODULE_AUTHOR("Kumaravel Thiagarajan<kumaravel.thiagarajan@microchip.com>");
475
+
MODULE_LICENSE("GPL v2");
+45
-150
drivers/spi/spi-pxa2xx.c
+45
-150
drivers/spi/spi-pxa2xx.c
···
20
20
#include <linux/module.h>
21
21
#include <linux/mod_devicetable.h>
22
22
#include <linux/of.h>
23
-
#include <linux/pci.h>
24
23
#include <linux/platform_device.h>
25
24
#include <linux/pm_runtime.h>
26
25
#include <linux/property.h>
···
1321
1322
kfree(chip);
1322
1323
}
1323
1324
1324
-
#ifdef CONFIG_ACPI
1325
-
static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1326
-
{ "INT33C0", LPSS_LPT_SSP },
1327
-
{ "INT33C1", LPSS_LPT_SSP },
1328
-
{ "INT3430", LPSS_LPT_SSP },
1329
-
{ "INT3431", LPSS_LPT_SSP },
1330
-
{ "80860F0E", LPSS_BYT_SSP },
1331
-
{ "8086228E", LPSS_BSW_SSP },
1332
-
{ },
1333
-
};
1334
-
MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1335
-
#endif
1336
-
1337
-
/*
1338
-
* PCI IDs of compound devices that integrate both host controller and private
1339
-
* integrated DMA engine. Please note these are not used in module
1340
-
* autoloading and probing in this module but matching the LPSS SSP type.
1341
-
*/
1342
-
static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1343
-
/* SPT-LP */
1344
-
{ PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1345
-
{ PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1346
-
/* SPT-H */
1347
-
{ PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1348
-
{ PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1349
-
/* KBL-H */
1350
-
{ PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1351
-
{ PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1352
-
/* CML-V */
1353
-
{ PCI_VDEVICE(INTEL, 0xa3a9), LPSS_SPT_SSP },
1354
-
{ PCI_VDEVICE(INTEL, 0xa3aa), LPSS_SPT_SSP },
1355
-
/* BXT A-Step */
1356
-
{ PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1357
-
{ PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1358
-
{ PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1359
-
/* BXT B-Step */
1360
-
{ PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1361
-
{ PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1362
-
{ PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1363
-
/* GLK */
1364
-
{ PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1365
-
{ PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1366
-
{ PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1367
-
/* ICL-LP */
1368
-
{ PCI_VDEVICE(INTEL, 0x34aa), LPSS_CNL_SSP },
1369
-
{ PCI_VDEVICE(INTEL, 0x34ab), LPSS_CNL_SSP },
1370
-
{ PCI_VDEVICE(INTEL, 0x34fb), LPSS_CNL_SSP },
1371
-
/* EHL */
1372
-
{ PCI_VDEVICE(INTEL, 0x4b2a), LPSS_BXT_SSP },
1373
-
{ PCI_VDEVICE(INTEL, 0x4b2b), LPSS_BXT_SSP },
1374
-
{ PCI_VDEVICE(INTEL, 0x4b37), LPSS_BXT_SSP },
1375
-
/* JSL */
1376
-
{ PCI_VDEVICE(INTEL, 0x4daa), LPSS_CNL_SSP },
1377
-
{ PCI_VDEVICE(INTEL, 0x4dab), LPSS_CNL_SSP },
1378
-
{ PCI_VDEVICE(INTEL, 0x4dfb), LPSS_CNL_SSP },
1379
-
/* TGL-H */
1380
-
{ PCI_VDEVICE(INTEL, 0x43aa), LPSS_CNL_SSP },
1381
-
{ PCI_VDEVICE(INTEL, 0x43ab), LPSS_CNL_SSP },
1382
-
{ PCI_VDEVICE(INTEL, 0x43fb), LPSS_CNL_SSP },
1383
-
{ PCI_VDEVICE(INTEL, 0x43fd), LPSS_CNL_SSP },
1384
-
/* ADL-P */
1385
-
{ PCI_VDEVICE(INTEL, 0x51aa), LPSS_CNL_SSP },
1386
-
{ PCI_VDEVICE(INTEL, 0x51ab), LPSS_CNL_SSP },
1387
-
{ PCI_VDEVICE(INTEL, 0x51fb), LPSS_CNL_SSP },
1388
-
/* ADL-M */
1389
-
{ PCI_VDEVICE(INTEL, 0x54aa), LPSS_CNL_SSP },
1390
-
{ PCI_VDEVICE(INTEL, 0x54ab), LPSS_CNL_SSP },
1391
-
{ PCI_VDEVICE(INTEL, 0x54fb), LPSS_CNL_SSP },
1392
-
/* APL */
1393
-
{ PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1394
-
{ PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1395
-
{ PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1396
-
/* RPL-S */
1397
-
{ PCI_VDEVICE(INTEL, 0x7a2a), LPSS_CNL_SSP },
1398
-
{ PCI_VDEVICE(INTEL, 0x7a2b), LPSS_CNL_SSP },
1399
-
{ PCI_VDEVICE(INTEL, 0x7a79), LPSS_CNL_SSP },
1400
-
{ PCI_VDEVICE(INTEL, 0x7a7b), LPSS_CNL_SSP },
1401
-
/* ADL-S */
1402
-
{ PCI_VDEVICE(INTEL, 0x7aaa), LPSS_CNL_SSP },
1403
-
{ PCI_VDEVICE(INTEL, 0x7aab), LPSS_CNL_SSP },
1404
-
{ PCI_VDEVICE(INTEL, 0x7af9), LPSS_CNL_SSP },
1405
-
{ PCI_VDEVICE(INTEL, 0x7afb), LPSS_CNL_SSP },
1406
-
/* MTL-P */
1407
-
{ PCI_VDEVICE(INTEL, 0x7e27), LPSS_CNL_SSP },
1408
-
{ PCI_VDEVICE(INTEL, 0x7e30), LPSS_CNL_SSP },
1409
-
{ PCI_VDEVICE(INTEL, 0x7e46), LPSS_CNL_SSP },
1410
-
/* CNL-LP */
1411
-
{ PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP },
1412
-
{ PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP },
1413
-
{ PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP },
1414
-
/* CNL-H */
1415
-
{ PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP },
1416
-
{ PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP },
1417
-
{ PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP },
1418
-
/* CML-LP */
1419
-
{ PCI_VDEVICE(INTEL, 0x02aa), LPSS_CNL_SSP },
1420
-
{ PCI_VDEVICE(INTEL, 0x02ab), LPSS_CNL_SSP },
1421
-
{ PCI_VDEVICE(INTEL, 0x02fb), LPSS_CNL_SSP },
1422
-
/* CML-H */
1423
-
{ PCI_VDEVICE(INTEL, 0x06aa), LPSS_CNL_SSP },
1424
-
{ PCI_VDEVICE(INTEL, 0x06ab), LPSS_CNL_SSP },
1425
-
{ PCI_VDEVICE(INTEL, 0x06fb), LPSS_CNL_SSP },
1426
-
/* TGL-LP */
1427
-
{ PCI_VDEVICE(INTEL, 0xa0aa), LPSS_CNL_SSP },
1428
-
{ PCI_VDEVICE(INTEL, 0xa0ab), LPSS_CNL_SSP },
1429
-
{ PCI_VDEVICE(INTEL, 0xa0de), LPSS_CNL_SSP },
1430
-
{ PCI_VDEVICE(INTEL, 0xa0df), LPSS_CNL_SSP },
1431
-
{ PCI_VDEVICE(INTEL, 0xa0fb), LPSS_CNL_SSP },
1432
-
{ PCI_VDEVICE(INTEL, 0xa0fd), LPSS_CNL_SSP },
1433
-
{ PCI_VDEVICE(INTEL, 0xa0fe), LPSS_CNL_SSP },
1434
-
{ },
1435
-
};
1436
-
1437
-
static const struct of_device_id pxa2xx_spi_of_match[] = {
1438
-
{ .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1439
-
{},
1440
-
};
1441
-
MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1442
-
1443
-
#ifdef CONFIG_PCI
1444
-
1445
1325
static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1446
1326
{
1447
1327
return param == chan->device->dev;
1448
1328
}
1449
-
1450
-
#endif /* CONFIG_PCI */
1451
1329
1452
1330
static struct pxa2xx_spi_controller *
1453
1331
pxa2xx_spi_init_pdata(struct platform_device *pdev)
···
1334
1458
struct device *parent = dev->parent;
1335
1459
struct ssp_device *ssp;
1336
1460
struct resource *res;
1337
-
struct pci_dev *pcidev = dev_is_pci(parent) ? to_pci_dev(parent) : NULL;
1338
-
const struct pci_device_id *pcidev_id = NULL;
1339
-
enum pxa_ssp_type type;
1461
+
enum pxa_ssp_type type = SSP_UNDEFINED;
1340
1462
const void *match;
1463
+
bool is_lpss_priv;
1341
1464
int status;
1342
1465
u64 uid;
1343
1466
1344
-
if (pcidev)
1345
-
pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, pcidev);
1467
+
is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv");
1346
1468
1347
-
match = device_get_match_data(&pdev->dev);
1469
+
match = device_get_match_data(dev);
1348
1470
if (match)
1349
1471
type = (enum pxa_ssp_type)match;
1350
-
else if (pcidev_id)
1351
-
type = (enum pxa_ssp_type)pcidev_id->driver_data;
1352
-
else
1472
+
else if (is_lpss_priv) {
1473
+
u32 value;
1474
+
1475
+
status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value);
1476
+
if (status)
1477
+
return ERR_PTR(status);
1478
+
1479
+
type = (enum pxa_ssp_type)value;
1480
+
}
1481
+
1482
+
/* Validate the SSP type correctness */
1483
+
if (!(type > SSP_UNDEFINED && type < SSP_MAX))
1353
1484
return ERR_PTR(-EINVAL);
1354
1485
1355
-
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1486
+
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1356
1487
if (!pdata)
1357
1488
return ERR_PTR(-ENOMEM);
1358
1489
1359
1490
ssp = &pdata->ssp;
1360
1491
1361
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1362
-
ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1492
+
ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1363
1493
if (IS_ERR(ssp->mmio_base))
1364
1494
return ERR_CAST(ssp->mmio_base);
1365
1495
1366
1496
ssp->phys_base = res->start;
1367
1497
1368
-
#ifdef CONFIG_PCI
1369
-
if (pcidev_id) {
1498
+
/* Platforms with iDMA 64-bit */
1499
+
if (is_lpss_priv) {
1370
1500
pdata->tx_param = parent;
1371
1501
pdata->rx_param = parent;
1372
1502
pdata->dma_filter = pxa2xx_spi_idma_filter;
1373
1503
}
1374
-
#endif
1375
1504
1376
-
ssp->clk = devm_clk_get(&pdev->dev, NULL);
1505
+
ssp->clk = devm_clk_get(dev, NULL);
1377
1506
if (IS_ERR(ssp->clk))
1378
1507
return ERR_CAST(ssp->clk);
1379
1508
···
1387
1506
return ERR_PTR(ssp->irq);
1388
1507
1389
1508
ssp->type = type;
1390
-
ssp->dev = &pdev->dev;
1509
+
ssp->dev = dev;
1391
1510
1392
1511
status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid);
1393
1512
if (status)
···
1395
1514
else
1396
1515
ssp->port_id = uid;
1397
1516
1398
-
pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave");
1517
+
pdata->is_slave = device_property_read_bool(dev, "spi-slave");
1399
1518
pdata->num_chipselect = 1;
1400
1519
pdata->enable_dma = true;
1401
1520
pdata->dma_burst_size = 1;
···
1688
1807
return 0;
1689
1808
}
1690
1809
1691
-
#ifdef CONFIG_PM_SLEEP
1692
1810
static int pxa2xx_spi_suspend(struct device *dev)
1693
1811
{
1694
1812
struct driver_data *drv_data = dev_get_drvdata(dev);
···
1722
1842
/* Start the queue running */
1723
1843
return spi_controller_resume(drv_data->controller);
1724
1844
}
1725
-
#endif
1726
1845
1727
-
#ifdef CONFIG_PM
1728
1846
static int pxa2xx_spi_runtime_suspend(struct device *dev)
1729
1847
{
1730
1848
struct driver_data *drv_data = dev_get_drvdata(dev);
···
1737
1859
1738
1860
return clk_prepare_enable(drv_data->ssp->clk);
1739
1861
}
1740
-
#endif
1741
1862
1742
1863
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1743
-
SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1744
-
SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1745
-
pxa2xx_spi_runtime_resume, NULL)
1864
+
SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1865
+
RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL)
1746
1866
};
1867
+
1868
+
#ifdef CONFIG_ACPI
1869
+
static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1870
+
{ "80860F0E", LPSS_BYT_SSP },
1871
+
{ "8086228E", LPSS_BSW_SSP },
1872
+
{ "INT33C0", LPSS_LPT_SSP },
1873
+
{ "INT33C1", LPSS_LPT_SSP },
1874
+
{ "INT3430", LPSS_LPT_SSP },
1875
+
{ "INT3431", LPSS_LPT_SSP },
1876
+
{}
1877
+
};
1878
+
MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1879
+
#endif
1880
+
1881
+
static const struct of_device_id pxa2xx_spi_of_match[] = {
1882
+
{ .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1883
+
{}
1884
+
};
1885
+
MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match);
1747
1886
1748
1887
static struct platform_driver driver = {
1749
1888
.driver = {
1750
1889
.name = "pxa2xx-spi",
1751
-
.pm = &pxa2xx_spi_pm_ops,
1890
+
.pm = pm_ptr(&pxa2xx_spi_pm_ops),
1752
1891
.acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1753
1892
.of_match_table = of_match_ptr(pxa2xx_spi_of_match),
1754
1893
},
+3
-3
drivers/spi/spi-sc18is602.c
+3
-3
drivers/spi/spi-sc18is602.c
···
235
235
return 0;
236
236
}
237
237
238
-
static int sc18is602_probe(struct i2c_client *client,
239
-
const struct i2c_device_id *id)
238
+
static int sc18is602_probe(struct i2c_client *client)
240
239
{
240
+
const struct i2c_device_id *id = i2c_client_get_device_id(client);
241
241
struct device *dev = &client->dev;
242
242
struct device_node *np = dev->of_node;
243
243
struct sc18is602_platform_data *pdata = dev_get_platdata(dev);
···
337
337
.name = "sc18is602",
338
338
.of_match_table = of_match_ptr(sc18is602_of_match),
339
339
},
340
-
.probe = sc18is602_probe,
340
+
.probe_new = sc18is602_probe,
341
341
.id_table = sc18is602_id,
342
342
};
343
343
+703
drivers/spi/spi-sn-f-ospi.c
+703
drivers/spi/spi-sn-f-ospi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Socionext SPI flash controller F_OSPI driver
4
+
* Copyright (C) 2021 Socionext Inc.
5
+
*/
6
+
7
+
#include <linux/bitfield.h>
8
+
#include <linux/clk.h>
9
+
#include <linux/io.h>
10
+
#include <linux/iopoll.h>
11
+
#include <linux/module.h>
12
+
#include <linux/mutex.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/spi/spi.h>
16
+
#include <linux/spi/spi-mem.h>
17
+
18
+
/* Registers */
19
+
#define OSPI_PROT_CTL_INDIR 0x00
20
+
#define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30)
21
+
#define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28)
22
+
#define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26)
23
+
#define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24)
24
+
#define OSPI_PROT_MODE_SINGLE 0
25
+
#define OSPI_PROT_MODE_DUAL 1
26
+
#define OSPI_PROT_MODE_QUAD 2
27
+
#define OSPI_PROT_MODE_OCTAL 3
28
+
#define OSPI_PROT_DATA_RATE_DATA BIT(23)
29
+
#define OSPI_PROT_DATA_RATE_ALT BIT(22)
30
+
#define OSPI_PROT_DATA_RATE_ADDR BIT(21)
31
+
#define OSPI_PROT_DATA_RATE_CODE BIT(20)
32
+
#define OSPI_PROT_SDR 0
33
+
#define OSPI_PROT_DDR 1
34
+
#define OSPI_PROT_BIT_POS_DATA BIT(19)
35
+
#define OSPI_PROT_BIT_POS_ALT BIT(18)
36
+
#define OSPI_PROT_BIT_POS_ADDR BIT(17)
37
+
#define OSPI_PROT_BIT_POS_CODE BIT(16)
38
+
#define OSPI_PROT_SAMP_EDGE BIT(12)
39
+
#define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10)
40
+
#define OSPI_PROT_DATA_UNIT_1B 0
41
+
#define OSPI_PROT_DATA_UNIT_2B 1
42
+
#define OSPI_PROT_DATA_UNIT_4B 3
43
+
#define OSPI_PROT_TRANS_DIR_WRITE BIT(9)
44
+
#define OSPI_PROT_DATA_EN BIT(8)
45
+
#define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5)
46
+
#define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2)
47
+
#define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0)
48
+
49
+
#define OSPI_CLK_CTL 0x10
50
+
#define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16)
51
+
#define OSPI_CLK_CTL_PHA BIT(12)
52
+
#define OSPI_CLK_CTL_PHA_180 0
53
+
#define OSPI_CLK_CTL_PHA_90 1
54
+
#define OSPI_CLK_CTL_DIV GENMASK(9, 8)
55
+
#define OSPI_CLK_CTL_DIV_1 0
56
+
#define OSPI_CLK_CTL_DIV_2 1
57
+
#define OSPI_CLK_CTL_DIV_4 2
58
+
#define OSPI_CLK_CTL_DIV_8 3
59
+
#define OSPI_CLK_CTL_INT_CLK_EN BIT(0)
60
+
61
+
#define OSPI_CS_CTL1 0x14
62
+
#define OSPI_CS_CTL2 0x18
63
+
#define OSPI_SSEL 0x20
64
+
#define OSPI_CMD_IDX_INDIR 0x40
65
+
#define OSPI_ADDR 0x50
66
+
#define OSPI_ALT_INDIR 0x60
67
+
#define OSPI_DMY_INDIR 0x70
68
+
#define OSPI_DAT 0x80
69
+
#define OSPI_DAT_SWP_INDIR 0x90
70
+
71
+
#define OSPI_DAT_SIZE_INDIR 0xA0
72
+
#define OSPI_DAT_SIZE_EN BIT(15)
73
+
#define OSPI_DAT_SIZE_MASK GENMASK(10, 0)
74
+
#define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1)
75
+
76
+
#define OSPI_TRANS_CTL 0xC0
77
+
#define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */
78
+
#define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */
79
+
80
+
#define OSPI_ACC_MODE 0xC4
81
+
#define OSPI_ACC_MODE_BOOT_DISABLE BIT(0)
82
+
83
+
#define OSPI_SWRST 0xD0
84
+
#define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */
85
+
#define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */
86
+
87
+
#define OSPI_STAT 0xE0
88
+
#define OSPI_STAT_IS_AXI_WRITING BIT(10)
89
+
#define OSPI_STAT_IS_AXI_READING BIT(9)
90
+
#define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4)
91
+
#define OSPI_STAT_IS_SPI_IDLE BIT(3)
92
+
93
+
#define OSPI_IRQ 0xF0
94
+
#define OSPI_IRQ_CS_DEASSERT BIT(8)
95
+
#define OSPI_IRQ_WRITE_BUF_READY BIT(2)
96
+
#define OSPI_IRQ_READ_BUF_READY BIT(1)
97
+
#define OSPI_IRQ_CS_TRANS_COMP BIT(0)
98
+
#define OSPI_IRQ_ALL \
99
+
(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \
100
+
| OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP)
101
+
102
+
#define OSPI_IRQ_STAT_EN 0xF4
103
+
#define OSPI_IRQ_SIG_EN 0xF8
104
+
105
+
/* Parameters */
106
+
#define OSPI_NUM_CS 4
107
+
#define OSPI_DUMMY_CYCLE_MAX 255
108
+
#define OSPI_WAIT_MAX_MSEC 100
109
+
110
+
struct f_ospi {
111
+
void __iomem *base;
112
+
struct device *dev;
113
+
struct clk *clk;
114
+
struct mutex mlock;
115
+
};
116
+
117
+
static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op)
118
+
{
119
+
return (op->dummy.nbytes * 8) / op->dummy.buswidth;
120
+
}
121
+
122
+
static void f_ospi_clear_irq(struct f_ospi *ospi)
123
+
{
124
+
writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP,
125
+
ospi->base + OSPI_IRQ);
126
+
}
127
+
128
+
static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits)
129
+
{
130
+
u32 val;
131
+
132
+
val = readl(ospi->base + OSPI_IRQ_STAT_EN);
133
+
val |= irq_bits;
134
+
writel(val, ospi->base + OSPI_IRQ_STAT_EN);
135
+
}
136
+
137
+
static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits)
138
+
{
139
+
u32 val;
140
+
141
+
val = readl(ospi->base + OSPI_IRQ_STAT_EN);
142
+
val &= ~irq_bits;
143
+
writel(val, ospi->base + OSPI_IRQ_STAT_EN);
144
+
}
145
+
146
+
static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits)
147
+
{
148
+
u32 val;
149
+
150
+
val = readl(ospi->base + OSPI_IRQ_SIG_EN);
151
+
val &= ~irq_bits;
152
+
writel(val, ospi->base + OSPI_IRQ_SIG_EN);
153
+
}
154
+
155
+
static int f_ospi_prepare_config(struct f_ospi *ospi)
156
+
{
157
+
u32 val, stat0, stat1;
158
+
159
+
/* G4: Disable internal clock */
160
+
val = readl(ospi->base + OSPI_CLK_CTL);
161
+
val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN);
162
+
writel(val, ospi->base + OSPI_CLK_CTL);
163
+
164
+
/* G5: Wait for stop */
165
+
stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING;
166
+
stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP;
167
+
168
+
return readl_poll_timeout(ospi->base + OSPI_STAT,
169
+
val, (val & (stat0 | stat1)) == stat1,
170
+
0, OSPI_WAIT_MAX_MSEC);
171
+
}
172
+
173
+
static int f_ospi_unprepare_config(struct f_ospi *ospi)
174
+
{
175
+
u32 val;
176
+
177
+
/* G11: Enable internal clock */
178
+
val = readl(ospi->base + OSPI_CLK_CTL);
179
+
val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN;
180
+
writel(val, ospi->base + OSPI_CLK_CTL);
181
+
182
+
/* G12: Wait for clock to start */
183
+
return readl_poll_timeout(ospi->base + OSPI_STAT,
184
+
val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP),
185
+
0, OSPI_WAIT_MAX_MSEC);
186
+
}
187
+
188
+
static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz)
189
+
{
190
+
long rate_hz = clk_get_rate(ospi->clk);
191
+
u32 div = DIV_ROUND_UP(rate_hz, device_hz);
192
+
u32 div_reg;
193
+
u32 val;
194
+
195
+
if (rate_hz < device_hz) {
196
+
dev_warn(ospi->dev, "Device frequency too large: %d\n",
197
+
device_hz);
198
+
div_reg = OSPI_CLK_CTL_DIV_1;
199
+
} else {
200
+
if (div == 1) {
201
+
div_reg = OSPI_CLK_CTL_DIV_1;
202
+
} else if (div == 2) {
203
+
div_reg = OSPI_CLK_CTL_DIV_2;
204
+
} else if (div <= 4) {
205
+
div_reg = OSPI_CLK_CTL_DIV_4;
206
+
} else if (div <= 8) {
207
+
div_reg = OSPI_CLK_CTL_DIV_8;
208
+
} else {
209
+
dev_warn(ospi->dev, "Device frequency too small: %d\n",
210
+
device_hz);
211
+
div_reg = OSPI_CLK_CTL_DIV_8;
212
+
}
213
+
}
214
+
215
+
/*
216
+
* G7: Set clock mode
217
+
* clock phase is fixed at 180 degrees and configure edge direction
218
+
* instead.
219
+
*/
220
+
val = readl(ospi->base + OSPI_CLK_CTL);
221
+
222
+
val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV);
223
+
val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180)
224
+
| FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg);
225
+
226
+
writel(val, ospi->base + OSPI_CLK_CTL);
227
+
}
228
+
229
+
static void f_ospi_config_dll(struct f_ospi *ospi)
230
+
{
231
+
/* G8: Configure DLL, nothing */
232
+
}
233
+
234
+
static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size)
235
+
{
236
+
u8 mode = OSPI_PROT_MODE_SINGLE;
237
+
238
+
switch (width) {
239
+
case 1:
240
+
mode = OSPI_PROT_MODE_SINGLE;
241
+
break;
242
+
case 2:
243
+
mode = OSPI_PROT_MODE_DUAL;
244
+
break;
245
+
case 4:
246
+
mode = OSPI_PROT_MODE_QUAD;
247
+
break;
248
+
case 8:
249
+
mode = OSPI_PROT_MODE_OCTAL;
250
+
break;
251
+
default:
252
+
if (data_size)
253
+
dev_err(ospi->dev, "Invalid buswidth: %d\n", width);
254
+
break;
255
+
}
256
+
257
+
return mode;
258
+
}
259
+
260
+
static void f_ospi_config_indir_protocol(struct f_ospi *ospi,
261
+
struct spi_mem *mem,
262
+
const struct spi_mem_op *op)
263
+
{
264
+
struct spi_device *spi = mem->spi;
265
+
u8 mode;
266
+
u32 prot = 0, val;
267
+
int unit;
268
+
269
+
/* Set one chip select */
270
+
writel(BIT(spi->chip_select), ospi->base + OSPI_SSEL);
271
+
272
+
mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1);
273
+
prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode);
274
+
275
+
mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes);
276
+
prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode);
277
+
278
+
mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes);
279
+
prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode);
280
+
281
+
prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR);
282
+
prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR);
283
+
prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR);
284
+
prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR);
285
+
286
+
if (spi->mode & SPI_LSB_FIRST)
287
+
prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT
288
+
| OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE;
289
+
290
+
if (spi->mode & SPI_CPHA)
291
+
prot |= OSPI_PROT_SAMP_EDGE;
292
+
293
+
/* Examine nbytes % 4 */
294
+
switch (op->data.nbytes & 0x3) {
295
+
case 0:
296
+
unit = OSPI_PROT_DATA_UNIT_4B;
297
+
val = 0;
298
+
break;
299
+
case 2:
300
+
unit = OSPI_PROT_DATA_UNIT_2B;
301
+
val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
302
+
break;
303
+
default:
304
+
unit = OSPI_PROT_DATA_UNIT_1B;
305
+
val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1);
306
+
break;
307
+
}
308
+
prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit);
309
+
310
+
switch (op->data.dir) {
311
+
case SPI_MEM_DATA_IN:
312
+
prot |= OSPI_PROT_DATA_EN;
313
+
break;
314
+
315
+
case SPI_MEM_DATA_OUT:
316
+
prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN;
317
+
break;
318
+
319
+
case SPI_MEM_NO_DATA:
320
+
prot |= OSPI_PROT_TRANS_DIR_WRITE;
321
+
break;
322
+
323
+
default:
324
+
dev_warn(ospi->dev, "Unsupported direction");
325
+
break;
326
+
}
327
+
328
+
prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes);
329
+
prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */
330
+
331
+
writel(prot, ospi->base + OSPI_PROT_CTL_INDIR);
332
+
writel(val, ospi->base + OSPI_DAT_SIZE_INDIR);
333
+
}
334
+
335
+
static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem,
336
+
const struct spi_mem_op *op)
337
+
{
338
+
struct spi_device *spi = mem->spi;
339
+
u32 irq_stat_en;
340
+
int ret;
341
+
342
+
ret = f_ospi_prepare_config(ospi);
343
+
if (ret)
344
+
return ret;
345
+
346
+
f_ospi_config_clk(ospi, spi->max_speed_hz);
347
+
348
+
f_ospi_config_indir_protocol(ospi, mem, op);
349
+
350
+
writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR);
351
+
writel(op->addr.val, ospi->base + OSPI_ADDR);
352
+
writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR);
353
+
354
+
f_ospi_clear_irq(ospi);
355
+
356
+
switch (op->data.dir) {
357
+
case SPI_MEM_DATA_IN:
358
+
irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
359
+
break;
360
+
361
+
case SPI_MEM_DATA_OUT:
362
+
irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP;
363
+
break;
364
+
365
+
case SPI_MEM_NO_DATA:
366
+
irq_stat_en = OSPI_IRQ_CS_TRANS_COMP;
367
+
break;
368
+
369
+
default:
370
+
dev_warn(ospi->dev, "Unsupported direction");
371
+
irq_stat_en = 0;
372
+
}
373
+
374
+
f_ospi_disable_irq_status(ospi, ~irq_stat_en);
375
+
f_ospi_enable_irq_status(ospi, irq_stat_en);
376
+
377
+
return f_ospi_unprepare_config(ospi);
378
+
}
379
+
380
+
static void f_ospi_indir_start_xfer(struct f_ospi *ospi)
381
+
{
382
+
/* Write only 1, auto cleared */
383
+
writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL);
384
+
}
385
+
386
+
static void f_ospi_indir_stop_xfer(struct f_ospi *ospi)
387
+
{
388
+
/* Write only 1, auto cleared */
389
+
writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL);
390
+
}
391
+
392
+
static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi)
393
+
{
394
+
u32 val;
395
+
396
+
return readl_poll_timeout(ospi->base + OSPI_IRQ, val,
397
+
val & OSPI_IRQ_CS_TRANS_COMP,
398
+
0, OSPI_WAIT_MAX_MSEC);
399
+
}
400
+
401
+
static int f_ospi_indir_read(struct f_ospi *ospi, struct spi_mem *mem,
402
+
const struct spi_mem_op *op)
403
+
{
404
+
u8 *buf = op->data.buf.in;
405
+
u32 val;
406
+
int i, ret;
407
+
408
+
mutex_lock(&ospi->mlock);
409
+
410
+
/* E1-2: Prepare transfer operation */
411
+
ret = f_ospi_indir_prepare_op(ospi, mem, op);
412
+
if (ret)
413
+
goto out;
414
+
415
+
f_ospi_indir_start_xfer(ospi);
416
+
417
+
/* E3-4: Wait for ready and read data */
418
+
for (i = 0; i < op->data.nbytes; i++) {
419
+
ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
420
+
val & OSPI_IRQ_READ_BUF_READY,
421
+
0, OSPI_WAIT_MAX_MSEC);
422
+
if (ret)
423
+
goto out;
424
+
425
+
buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF;
426
+
}
427
+
428
+
/* E5-6: Stop transfer if data size is nothing */
429
+
if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
430
+
f_ospi_indir_stop_xfer(ospi);
431
+
432
+
/* E7-8: Wait for completion and clear */
433
+
ret = f_ospi_indir_wait_xfer_complete(ospi);
434
+
if (ret)
435
+
goto out;
436
+
437
+
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
438
+
439
+
/* E9: Do nothing if data size is valid */
440
+
if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)
441
+
goto out;
442
+
443
+
/* E10-11: Reset and check read fifo */
444
+
writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST);
445
+
446
+
ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val,
447
+
!(val & OSPI_SWRST_INDIR_READ_FIFO),
448
+
0, OSPI_WAIT_MAX_MSEC);
449
+
out:
450
+
mutex_unlock(&ospi->mlock);
451
+
452
+
return ret;
453
+
}
454
+
455
+
static int f_ospi_indir_write(struct f_ospi *ospi, struct spi_mem *mem,
456
+
const struct spi_mem_op *op)
457
+
{
458
+
u8 *buf = (u8 *)op->data.buf.out;
459
+
u32 val;
460
+
int i, ret;
461
+
462
+
mutex_lock(&ospi->mlock);
463
+
464
+
/* F1-3: Prepare transfer operation */
465
+
ret = f_ospi_indir_prepare_op(ospi, mem, op);
466
+
if (ret)
467
+
goto out;
468
+
469
+
f_ospi_indir_start_xfer(ospi);
470
+
471
+
if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN))
472
+
goto nodata;
473
+
474
+
/* F4-5: Wait for buffer ready and write data */
475
+
for (i = 0; i < op->data.nbytes; i++) {
476
+
ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val,
477
+
val & OSPI_IRQ_WRITE_BUF_READY,
478
+
0, OSPI_WAIT_MAX_MSEC);
479
+
if (ret)
480
+
goto out;
481
+
482
+
writel(buf[i], ospi->base + OSPI_DAT);
483
+
}
484
+
485
+
/* F6-7: Stop transfer if data size is nothing */
486
+
if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN))
487
+
f_ospi_indir_stop_xfer(ospi);
488
+
489
+
nodata:
490
+
/* F8-9: Wait for completion and clear */
491
+
ret = f_ospi_indir_wait_xfer_complete(ospi);
492
+
if (ret)
493
+
goto out;
494
+
495
+
writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ);
496
+
out:
497
+
mutex_unlock(&ospi->mlock);
498
+
499
+
return ret;
500
+
}
501
+
502
+
static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
503
+
{
504
+
struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->master);
505
+
int err = 0;
506
+
507
+
switch (op->data.dir) {
508
+
case SPI_MEM_DATA_IN:
509
+
err = f_ospi_indir_read(ospi, mem, op);
510
+
break;
511
+
512
+
case SPI_MEM_DATA_OUT:
513
+
fallthrough;
514
+
case SPI_MEM_NO_DATA:
515
+
err = f_ospi_indir_write(ospi, mem, op);
516
+
break;
517
+
518
+
default:
519
+
dev_warn(ospi->dev, "Unsupported direction");
520
+
err = -EOPNOTSUPP;
521
+
}
522
+
523
+
return err;
524
+
}
525
+
526
+
static bool f_ospi_supports_op_width(struct spi_mem *mem,
527
+
const struct spi_mem_op *op)
528
+
{
529
+
u8 width_available[] = { 0, 1, 2, 4, 8 };
530
+
u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth,
531
+
op->dummy.buswidth, op->data.buswidth };
532
+
bool is_match_found;
533
+
int i, j;
534
+
535
+
for (i = 0; i < ARRAY_SIZE(width_op); i++) {
536
+
is_match_found = false;
537
+
538
+
for (j = 0; j < ARRAY_SIZE(width_available); j++) {
539
+
if (width_op[i] == width_available[j]) {
540
+
is_match_found = true;
541
+
break;
542
+
}
543
+
}
544
+
545
+
if (!is_match_found)
546
+
return false;
547
+
}
548
+
549
+
return true;
550
+
}
551
+
552
+
static bool f_ospi_supports_op(struct spi_mem *mem,
553
+
const struct spi_mem_op *op)
554
+
{
555
+
if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX)
556
+
return false;
557
+
558
+
if (op->addr.nbytes > 4)
559
+
return false;
560
+
561
+
if (!f_ospi_supports_op_width(mem, op))
562
+
return false;
563
+
564
+
return true;
565
+
}
566
+
567
+
static int f_ospi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
568
+
{
569
+
op->data.nbytes = min((int)op->data.nbytes, (int)(OSPI_DAT_SIZE_MAX));
570
+
571
+
return 0;
572
+
}
573
+
574
+
static const struct spi_controller_mem_ops f_ospi_mem_ops = {
575
+
.adjust_op_size = f_ospi_adjust_op_size,
576
+
.supports_op = f_ospi_supports_op,
577
+
.exec_op = f_ospi_exec_op,
578
+
};
579
+
580
+
static int f_ospi_init(struct f_ospi *ospi)
581
+
{
582
+
int ret;
583
+
584
+
ret = f_ospi_prepare_config(ospi);
585
+
if (ret)
586
+
return ret;
587
+
588
+
/* Disable boot signal */
589
+
writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE);
590
+
591
+
f_ospi_config_dll(ospi);
592
+
593
+
/* Disable IRQ */
594
+
f_ospi_clear_irq(ospi);
595
+
f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL);
596
+
f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL);
597
+
598
+
return f_ospi_unprepare_config(ospi);
599
+
}
600
+
601
+
static int f_ospi_probe(struct platform_device *pdev)
602
+
{
603
+
struct spi_controller *ctlr;
604
+
struct device *dev = &pdev->dev;
605
+
struct f_ospi *ospi;
606
+
u32 num_cs = OSPI_NUM_CS;
607
+
int ret;
608
+
609
+
ctlr = spi_alloc_master(dev, sizeof(*ospi));
610
+
if (!ctlr)
611
+
return -ENOMEM;
612
+
613
+
ctlr->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL
614
+
| SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL
615
+
| SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST;
616
+
ctlr->mem_ops = &f_ospi_mem_ops;
617
+
ctlr->bus_num = -1;
618
+
of_property_read_u32(dev->of_node, "num-cs", &num_cs);
619
+
if (num_cs > OSPI_NUM_CS) {
620
+
dev_err(dev, "num-cs too large: %d\n", num_cs);
621
+
return -ENOMEM;
622
+
}
623
+
ctlr->num_chipselect = num_cs;
624
+
ctlr->dev.of_node = dev->of_node;
625
+
626
+
ospi = spi_controller_get_devdata(ctlr);
627
+
ospi->dev = dev;
628
+
629
+
platform_set_drvdata(pdev, ospi);
630
+
631
+
ospi->base = devm_platform_ioremap_resource(pdev, 0);
632
+
if (IS_ERR(ospi->base)) {
633
+
ret = PTR_ERR(ospi->base);
634
+
goto err_put_ctlr;
635
+
}
636
+
637
+
ospi->clk = devm_clk_get(dev, NULL);
638
+
if (IS_ERR(ospi->clk)) {
639
+
ret = PTR_ERR(ospi->clk);
640
+
goto err_put_ctlr;
641
+
}
642
+
643
+
ret = clk_prepare_enable(ospi->clk);
644
+
if (ret) {
645
+
dev_err(dev, "Failed to enable the clock\n");
646
+
goto err_disable_clk;
647
+
}
648
+
649
+
mutex_init(&ospi->mlock);
650
+
651
+
ret = f_ospi_init(ospi);
652
+
if (ret)
653
+
goto err_destroy_mutex;
654
+
655
+
ret = devm_spi_register_controller(dev, ctlr);
656
+
if (ret)
657
+
goto err_destroy_mutex;
658
+
659
+
return 0;
660
+
661
+
err_destroy_mutex:
662
+
mutex_destroy(&ospi->mlock);
663
+
664
+
err_disable_clk:
665
+
clk_disable_unprepare(ospi->clk);
666
+
667
+
err_put_ctlr:
668
+
spi_controller_put(ctlr);
669
+
670
+
return ret;
671
+
}
672
+
673
+
static int f_ospi_remove(struct platform_device *pdev)
674
+
{
675
+
struct f_ospi *ospi = platform_get_drvdata(pdev);
676
+
677
+
clk_disable_unprepare(ospi->clk);
678
+
679
+
mutex_destroy(&ospi->mlock);
680
+
681
+
return 0;
682
+
}
683
+
684
+
static const struct of_device_id f_ospi_dt_ids[] = {
685
+
{ .compatible = "socionext,f-ospi" },
686
+
{}
687
+
};
688
+
MODULE_DEVICE_TABLE(of, f_ospi_dt_ids);
689
+
690
+
static struct platform_driver f_ospi_driver = {
691
+
.driver = {
692
+
.name = "socionext,f-ospi",
693
+
.of_match_table = f_ospi_dt_ids,
694
+
},
695
+
.probe = f_ospi_probe,
696
+
.remove = f_ospi_remove,
697
+
};
698
+
module_platform_driver(f_ospi_driver);
699
+
700
+
MODULE_DESCRIPTION("Socionext F_OSPI controller driver");
701
+
MODULE_AUTHOR("Socionext Inc.");
702
+
MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
703
+
MODULE_LICENSE("GPL");
+508
drivers/spi/spi-wpcm-fiu.c
+508
drivers/spi/spi-wpcm-fiu.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
// Copyright (C) 2022 Jonathan Neuschäfer
3
+
4
+
#include <linux/clk.h>
5
+
#include <linux/mfd/syscon.h>
6
+
#include <linux/module.h>
7
+
#include <linux/of_address.h>
8
+
#include <linux/of_device.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
11
+
#include <linux/spi/spi-mem.h>
12
+
13
+
#define FIU_CFG 0x00
14
+
#define FIU_BURST_BFG 0x01
15
+
#define FIU_RESP_CFG 0x02
16
+
#define FIU_CFBB_PROT 0x03
17
+
#define FIU_FWIN1_LOW 0x04
18
+
#define FIU_FWIN1_HIGH 0x06
19
+
#define FIU_FWIN2_LOW 0x08
20
+
#define FIU_FWIN2_HIGH 0x0a
21
+
#define FIU_FWIN3_LOW 0x0c
22
+
#define FIU_FWIN3_HIGH 0x0e
23
+
#define FIU_PROT_LOCK 0x10
24
+
#define FIU_PROT_CLEAR 0x11
25
+
#define FIU_SPI_FL_CFG 0x14
26
+
#define FIU_UMA_CODE 0x16
27
+
#define FIU_UMA_AB0 0x17
28
+
#define FIU_UMA_AB1 0x18
29
+
#define FIU_UMA_AB2 0x19
30
+
#define FIU_UMA_DB0 0x1a
31
+
#define FIU_UMA_DB1 0x1b
32
+
#define FIU_UMA_DB2 0x1c
33
+
#define FIU_UMA_DB3 0x1d
34
+
#define FIU_UMA_CTS 0x1e
35
+
#define FIU_UMA_ECTS 0x1f
36
+
37
+
#define FIU_BURST_CFG_R16 3
38
+
39
+
#define FIU_UMA_CTS_D_SIZE(x) (x)
40
+
#define FIU_UMA_CTS_A_SIZE BIT(3)
41
+
#define FIU_UMA_CTS_WR BIT(4)
42
+
#define FIU_UMA_CTS_CS(x) ((x) << 5)
43
+
#define FIU_UMA_CTS_EXEC_DONE BIT(7)
44
+
45
+
#define SHM_FLASH_SIZE 0x02
46
+
#define SHM_FLASH_SIZE_STALL_HOST BIT(6)
47
+
48
+
/*
49
+
* I observed a typical wait time of 16 iterations for a UMA transfer to
50
+
* finish, so this should be a safe limit.
51
+
*/
52
+
#define UMA_WAIT_ITERATIONS 100
53
+
54
+
/* The memory-mapped view of flash is 16 MiB long */
55
+
#define MAX_MEMORY_SIZE_PER_CS (16 << 20)
56
+
#define MAX_MEMORY_SIZE_TOTAL (4 * MAX_MEMORY_SIZE_PER_CS)
57
+
58
+
struct wpcm_fiu_spi {
59
+
struct device *dev;
60
+
struct clk *clk;
61
+
void __iomem *regs;
62
+
void __iomem *memory;
63
+
size_t memory_size;
64
+
struct regmap *shm_regmap;
65
+
};
66
+
67
+
static void wpcm_fiu_set_opcode(struct wpcm_fiu_spi *fiu, u8 opcode)
68
+
{
69
+
writeb(opcode, fiu->regs + FIU_UMA_CODE);
70
+
}
71
+
72
+
static void wpcm_fiu_set_addr(struct wpcm_fiu_spi *fiu, u32 addr)
73
+
{
74
+
writeb((addr >> 0) & 0xff, fiu->regs + FIU_UMA_AB0);
75
+
writeb((addr >> 8) & 0xff, fiu->regs + FIU_UMA_AB1);
76
+
writeb((addr >> 16) & 0xff, fiu->regs + FIU_UMA_AB2);
77
+
}
78
+
79
+
static void wpcm_fiu_set_data(struct wpcm_fiu_spi *fiu, const u8 *data, unsigned int nbytes)
80
+
{
81
+
int i;
82
+
83
+
for (i = 0; i < nbytes; i++)
84
+
writeb(data[i], fiu->regs + FIU_UMA_DB0 + i);
85
+
}
86
+
87
+
static void wpcm_fiu_get_data(struct wpcm_fiu_spi *fiu, u8 *data, unsigned int nbytes)
88
+
{
89
+
int i;
90
+
91
+
for (i = 0; i < nbytes; i++)
92
+
data[i] = readb(fiu->regs + FIU_UMA_DB0 + i);
93
+
}
94
+
95
+
/*
96
+
* Perform a UMA (User Mode Access) operation, i.e. a software-controlled SPI transfer.
97
+
*/
98
+
static int wpcm_fiu_do_uma(struct wpcm_fiu_spi *fiu, unsigned int cs,
99
+
bool use_addr, bool write, int data_bytes)
100
+
{
101
+
int i = 0;
102
+
u8 cts = FIU_UMA_CTS_EXEC_DONE | FIU_UMA_CTS_CS(cs);
103
+
104
+
if (use_addr)
105
+
cts |= FIU_UMA_CTS_A_SIZE;
106
+
if (write)
107
+
cts |= FIU_UMA_CTS_WR;
108
+
cts |= FIU_UMA_CTS_D_SIZE(data_bytes);
109
+
110
+
writeb(cts, fiu->regs + FIU_UMA_CTS);
111
+
112
+
for (i = 0; i < UMA_WAIT_ITERATIONS; i++)
113
+
if (!(readb(fiu->regs + FIU_UMA_CTS) & FIU_UMA_CTS_EXEC_DONE))
114
+
return 0;
115
+
116
+
dev_info(fiu->dev, "UMA transfer has not finished in %d iterations\n", UMA_WAIT_ITERATIONS);
117
+
return -EIO;
118
+
}
119
+
120
+
static void wpcm_fiu_ects_assert(struct wpcm_fiu_spi *fiu, unsigned int cs)
121
+
{
122
+
u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
123
+
124
+
ects &= ~BIT(cs);
125
+
writeb(ects, fiu->regs + FIU_UMA_ECTS);
126
+
}
127
+
128
+
static void wpcm_fiu_ects_deassert(struct wpcm_fiu_spi *fiu, unsigned int cs)
129
+
{
130
+
u8 ects = readb(fiu->regs + FIU_UMA_ECTS);
131
+
132
+
ects |= BIT(cs);
133
+
writeb(ects, fiu->regs + FIU_UMA_ECTS);
134
+
}
135
+
136
+
struct wpcm_fiu_op_shape {
137
+
bool (*match)(const struct spi_mem_op *op);
138
+
int (*exec)(struct spi_mem *mem, const struct spi_mem_op *op);
139
+
};
140
+
141
+
static bool wpcm_fiu_normal_match(const struct spi_mem_op *op)
142
+
{
143
+
// Opcode 0x0b (FAST READ) is treated differently in hardware
144
+
if (op->cmd.opcode == 0x0b)
145
+
return false;
146
+
147
+
return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
148
+
op->dummy.nbytes == 0 && op->data.nbytes <= 4;
149
+
}
150
+
151
+
static int wpcm_fiu_normal_exec(struct spi_mem *mem, const struct spi_mem_op *op)
152
+
{
153
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
154
+
int ret;
155
+
156
+
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
157
+
wpcm_fiu_set_addr(fiu, op->addr.val);
158
+
if (op->data.dir == SPI_MEM_DATA_OUT)
159
+
wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
160
+
161
+
ret = wpcm_fiu_do_uma(fiu, mem->spi->chip_select, op->addr.nbytes == 3,
162
+
op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
163
+
164
+
if (op->data.dir == SPI_MEM_DATA_IN)
165
+
wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
166
+
167
+
return ret;
168
+
}
169
+
170
+
static bool wpcm_fiu_fast_read_match(const struct spi_mem_op *op)
171
+
{
172
+
return op->cmd.opcode == 0x0b && op->addr.nbytes == 3 &&
173
+
op->dummy.nbytes == 1 &&
174
+
op->data.nbytes >= 1 && op->data.nbytes <= 4 &&
175
+
op->data.dir == SPI_MEM_DATA_IN;
176
+
}
177
+
178
+
static int wpcm_fiu_fast_read_exec(struct spi_mem *mem, const struct spi_mem_op *op)
179
+
{
180
+
return -EINVAL;
181
+
}
182
+
183
+
/*
184
+
* 4-byte addressing.
185
+
*
186
+
* Flash view: [ C A A A A D D D D]
187
+
* bytes: 13 aa bb cc dd -> 5a a5 f0 0f
188
+
* FIU's view: [ C A A A][ C D D D D]
189
+
* FIU mode: [ read/write][ read ]
190
+
*/
191
+
static bool wpcm_fiu_4ba_match(const struct spi_mem_op *op)
192
+
{
193
+
return op->addr.nbytes == 4 && op->dummy.nbytes == 0 && op->data.nbytes <= 4;
194
+
}
195
+
196
+
static int wpcm_fiu_4ba_exec(struct spi_mem *mem, const struct spi_mem_op *op)
197
+
{
198
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
199
+
int cs = mem->spi->chip_select;
200
+
201
+
wpcm_fiu_ects_assert(fiu, cs);
202
+
203
+
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
204
+
wpcm_fiu_set_addr(fiu, op->addr.val >> 8);
205
+
wpcm_fiu_do_uma(fiu, cs, true, false, 0);
206
+
207
+
wpcm_fiu_set_opcode(fiu, op->addr.val & 0xff);
208
+
wpcm_fiu_set_addr(fiu, 0);
209
+
if (op->data.dir == SPI_MEM_DATA_OUT)
210
+
wpcm_fiu_set_data(fiu, op->data.buf.out, op->data.nbytes);
211
+
wpcm_fiu_do_uma(fiu, cs, false, op->data.dir == SPI_MEM_DATA_OUT, op->data.nbytes);
212
+
213
+
wpcm_fiu_ects_deassert(fiu, cs);
214
+
215
+
if (op->data.dir == SPI_MEM_DATA_IN)
216
+
wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
217
+
218
+
return 0;
219
+
}
220
+
221
+
/*
222
+
* RDID (Read Identification) needs special handling because Linux expects to
223
+
* be able to read 6 ID bytes and FIU can only read up to 4 at once.
224
+
*
225
+
* We're lucky in this case, because executing the RDID instruction twice will
226
+
* result in the same result.
227
+
*
228
+
* What we do is as follows (C: write command/opcode byte, D: read data byte,
229
+
* A: write address byte):
230
+
*
231
+
* 1. C D D D
232
+
* 2. C A A A D D D
233
+
*/
234
+
static bool wpcm_fiu_rdid_match(const struct spi_mem_op *op)
235
+
{
236
+
return op->cmd.opcode == 0x9f && op->addr.nbytes == 0 &&
237
+
op->dummy.nbytes == 0 && op->data.nbytes == 6 &&
238
+
op->data.dir == SPI_MEM_DATA_IN;
239
+
}
240
+
241
+
static int wpcm_fiu_rdid_exec(struct spi_mem *mem, const struct spi_mem_op *op)
242
+
{
243
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
244
+
int cs = mem->spi->chip_select;
245
+
246
+
/* First transfer */
247
+
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
248
+
wpcm_fiu_set_addr(fiu, 0);
249
+
wpcm_fiu_do_uma(fiu, cs, false, false, 3);
250
+
wpcm_fiu_get_data(fiu, op->data.buf.in, 3);
251
+
252
+
/* Second transfer */
253
+
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
254
+
wpcm_fiu_set_addr(fiu, 0);
255
+
wpcm_fiu_do_uma(fiu, cs, true, false, 3);
256
+
wpcm_fiu_get_data(fiu, op->data.buf.in + 3, 3);
257
+
258
+
return 0;
259
+
}
260
+
261
+
/*
262
+
* With some dummy bytes.
263
+
*
264
+
* C A A A X* X D D D D
265
+
* [C A A A D*][C D D D D]
266
+
*/
267
+
static bool wpcm_fiu_dummy_match(const struct spi_mem_op *op)
268
+
{
269
+
// Opcode 0x0b (FAST READ) is treated differently in hardware
270
+
if (op->cmd.opcode == 0x0b)
271
+
return false;
272
+
273
+
return (op->addr.nbytes == 0 || op->addr.nbytes == 3) &&
274
+
op->dummy.nbytes >= 1 && op->dummy.nbytes <= 5 &&
275
+
op->data.nbytes <= 4;
276
+
}
277
+
278
+
static int wpcm_fiu_dummy_exec(struct spi_mem *mem, const struct spi_mem_op *op)
279
+
{
280
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
281
+
int cs = mem->spi->chip_select;
282
+
283
+
wpcm_fiu_ects_assert(fiu, cs);
284
+
285
+
/* First transfer */
286
+
wpcm_fiu_set_opcode(fiu, op->cmd.opcode);
287
+
wpcm_fiu_set_addr(fiu, op->addr.val);
288
+
wpcm_fiu_do_uma(fiu, cs, op->addr.nbytes != 0, true, op->dummy.nbytes - 1);
289
+
290
+
/* Second transfer */
291
+
wpcm_fiu_set_opcode(fiu, 0);
292
+
wpcm_fiu_set_addr(fiu, 0);
293
+
wpcm_fiu_do_uma(fiu, cs, false, false, op->data.nbytes);
294
+
wpcm_fiu_get_data(fiu, op->data.buf.in, op->data.nbytes);
295
+
296
+
wpcm_fiu_ects_deassert(fiu, cs);
297
+
298
+
return 0;
299
+
}
300
+
301
+
static const struct wpcm_fiu_op_shape wpcm_fiu_op_shapes[] = {
302
+
{ .match = wpcm_fiu_normal_match, .exec = wpcm_fiu_normal_exec },
303
+
{ .match = wpcm_fiu_fast_read_match, .exec = wpcm_fiu_fast_read_exec },
304
+
{ .match = wpcm_fiu_4ba_match, .exec = wpcm_fiu_4ba_exec },
305
+
{ .match = wpcm_fiu_rdid_match, .exec = wpcm_fiu_rdid_exec },
306
+
{ .match = wpcm_fiu_dummy_match, .exec = wpcm_fiu_dummy_exec },
307
+
};
308
+
309
+
static const struct wpcm_fiu_op_shape *wpcm_fiu_find_op_shape(const struct spi_mem_op *op)
310
+
{
311
+
size_t i;
312
+
313
+
for (i = 0; i < ARRAY_SIZE(wpcm_fiu_op_shapes); i++) {
314
+
const struct wpcm_fiu_op_shape *shape = &wpcm_fiu_op_shapes[i];
315
+
316
+
if (shape->match(op))
317
+
return shape;
318
+
}
319
+
320
+
return NULL;
321
+
}
322
+
323
+
static bool wpcm_fiu_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
324
+
{
325
+
if (!spi_mem_default_supports_op(mem, op))
326
+
return false;
327
+
328
+
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
329
+
return false;
330
+
331
+
if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
332
+
op->dummy.buswidth > 1 || op->data.buswidth > 1)
333
+
return false;
334
+
335
+
return wpcm_fiu_find_op_shape(op) != NULL;
336
+
}
337
+
338
+
/*
339
+
* In order to ensure the integrity of SPI transfers performed via UMA,
340
+
* temporarily disable (stall) memory accesses coming from the host CPU.
341
+
*/
342
+
static void wpcm_fiu_stall_host(struct wpcm_fiu_spi *fiu, bool stall)
343
+
{
344
+
if (fiu->shm_regmap) {
345
+
int res = regmap_update_bits(fiu->shm_regmap, SHM_FLASH_SIZE,
346
+
SHM_FLASH_SIZE_STALL_HOST,
347
+
stall ? SHM_FLASH_SIZE_STALL_HOST : 0);
348
+
if (res)
349
+
dev_warn(fiu->dev, "Failed to (un)stall host memory accesses: %d\n", res);
350
+
}
351
+
}
352
+
353
+
static int wpcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
354
+
{
355
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(mem->spi->controller);
356
+
const struct wpcm_fiu_op_shape *shape = wpcm_fiu_find_op_shape(op);
357
+
358
+
wpcm_fiu_stall_host(fiu, true);
359
+
360
+
if (shape)
361
+
return shape->exec(mem, op);
362
+
363
+
wpcm_fiu_stall_host(fiu, false);
364
+
365
+
return -ENOTSUPP;
366
+
}
367
+
368
+
static int wpcm_fiu_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
369
+
{
370
+
if (op->data.nbytes > 4)
371
+
op->data.nbytes = 4;
372
+
373
+
return 0;
374
+
}
375
+
376
+
static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
377
+
{
378
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
379
+
int cs = desc->mem->spi->chip_select;
380
+
381
+
if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
382
+
return -ENOTSUPP;
383
+
384
+
/*
385
+
* Unfortunately, FIU only supports a 16 MiB direct mapping window (per
386
+
* attached flash chip), but the SPI MEM core doesn't support partial
387
+
* direct mappings. This means that we can't support direct mapping on
388
+
* flashes that are bigger than 16 MiB.
389
+
*/
390
+
if (desc->info.offset + desc->info.length > MAX_MEMORY_SIZE_PER_CS)
391
+
return -ENOTSUPP;
392
+
393
+
/* Don't read past the memory window */
394
+
if (cs * MAX_MEMORY_SIZE_PER_CS + desc->info.offset + desc->info.length > fiu->memory_size)
395
+
return -ENOTSUPP;
396
+
397
+
return 0;
398
+
}
399
+
400
+
static ssize_t wpcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf)
401
+
{
402
+
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
403
+
int cs = desc->mem->spi->chip_select;
404
+
405
+
if (offs >= MAX_MEMORY_SIZE_PER_CS)
406
+
return -ENOTSUPP;
407
+
408
+
offs += cs * MAX_MEMORY_SIZE_PER_CS;
409
+
410
+
if (!fiu->memory || offs >= fiu->memory_size)
411
+
return -ENOTSUPP;
412
+
413
+
len = min_t(size_t, len, fiu->memory_size - offs);
414
+
memcpy_fromio(buf, fiu->memory + offs, len);
415
+
416
+
return len;
417
+
}
418
+
419
+
static const struct spi_controller_mem_ops wpcm_fiu_mem_ops = {
420
+
.adjust_op_size = wpcm_fiu_adjust_op_size,
421
+
.supports_op = wpcm_fiu_supports_op,
422
+
.exec_op = wpcm_fiu_exec_op,
423
+
.dirmap_create = wpcm_fiu_dirmap_create,
424
+
.dirmap_read = wpcm_fiu_direct_read,
425
+
};
426
+
427
+
static void wpcm_fiu_hw_init(struct wpcm_fiu_spi *fiu)
428
+
{
429
+
/* Configure memory-mapped flash access */
430
+
writeb(FIU_BURST_CFG_R16, fiu->regs + FIU_BURST_BFG);
431
+
writeb(MAX_MEMORY_SIZE_TOTAL / (512 << 10), fiu->regs + FIU_CFG);
432
+
writeb(MAX_MEMORY_SIZE_PER_CS / (512 << 10) | BIT(6), fiu->regs + FIU_SPI_FL_CFG);
433
+
434
+
/* Deassert all manually asserted chip selects */
435
+
writeb(0x0f, fiu->regs + FIU_UMA_ECTS);
436
+
}
437
+
438
+
static int wpcm_fiu_probe(struct platform_device *pdev)
439
+
{
440
+
struct device *dev = &pdev->dev;
441
+
struct spi_controller *ctrl;
442
+
struct wpcm_fiu_spi *fiu;
443
+
struct resource *res;
444
+
445
+
ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
446
+
if (!ctrl)
447
+
return -ENOMEM;
448
+
449
+
fiu = spi_controller_get_devdata(ctrl);
450
+
fiu->dev = dev;
451
+
452
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
453
+
fiu->regs = devm_ioremap_resource(dev, res);
454
+
if (IS_ERR(fiu->regs)) {
455
+
dev_err(dev, "Failed to map registers\n");
456
+
return PTR_ERR(fiu->regs);
457
+
}
458
+
459
+
fiu->clk = devm_clk_get_enabled(dev, NULL);
460
+
if (IS_ERR(fiu->clk))
461
+
return PTR_ERR(fiu->clk);
462
+
463
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory");
464
+
fiu->memory = devm_ioremap_resource(dev, res);
465
+
fiu->memory_size = min_t(size_t, resource_size(res), MAX_MEMORY_SIZE_TOTAL);
466
+
if (IS_ERR(fiu->memory)) {
467
+
dev_err(dev, "Failed to map flash memory window\n");
468
+
return PTR_ERR(fiu->memory);
469
+
}
470
+
471
+
fiu->shm_regmap = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "nuvoton,shm");
472
+
473
+
wpcm_fiu_hw_init(fiu);
474
+
475
+
ctrl->bus_num = -1;
476
+
ctrl->mem_ops = &wpcm_fiu_mem_ops;
477
+
ctrl->num_chipselect = 4;
478
+
ctrl->dev.of_node = dev->of_node;
479
+
480
+
/*
481
+
* The FIU doesn't include a clock divider, the clock is entirely
482
+
* determined by the AHB3 bus clock.
483
+
*/
484
+
ctrl->min_speed_hz = clk_get_rate(fiu->clk);
485
+
ctrl->max_speed_hz = clk_get_rate(fiu->clk);
486
+
487
+
return devm_spi_register_controller(dev, ctrl);
488
+
}
489
+
490
+
static const struct of_device_id wpcm_fiu_dt_ids[] = {
491
+
{ .compatible = "nuvoton,wpcm450-fiu", },
492
+
{ }
493
+
};
494
+
MODULE_DEVICE_TABLE(of, wpcm_fiu_dt_ids);
495
+
496
+
static struct platform_driver wpcm_fiu_driver = {
497
+
.driver = {
498
+
.name = "wpcm450-fiu",
499
+
.bus = &platform_bus_type,
500
+
.of_match_table = wpcm_fiu_dt_ids,
501
+
},
502
+
.probe = wpcm_fiu_probe,
503
+
};
504
+
module_platform_driver(wpcm_fiu_driver);
505
+
506
+
MODULE_DESCRIPTION("Nuvoton WPCM450 FIU SPI controller driver");
507
+
MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
508
+
MODULE_LICENSE("GPL");
+2
-3
drivers/spi/spi-xcomm.c
+2
-3
drivers/spi/spi-xcomm.c
···
202
202
return status;
203
203
}
204
204
205
-
static int spi_xcomm_probe(struct i2c_client *i2c,
206
-
const struct i2c_device_id *id)
205
+
static int spi_xcomm_probe(struct i2c_client *i2c)
207
206
{
208
207
struct spi_xcomm *spi_xcomm;
209
208
struct spi_master *master;
···
241
242
.name = "spi-xcomm",
242
243
},
243
244
.id_table = spi_xcomm_ids,
244
-
.probe = spi_xcomm_probe,
245
+
.probe_new = spi_xcomm_probe,
245
246
};
246
247
module_i2c_driver(spi_xcomm_driver);
247
248
+155
-36
drivers/spi/spi-zynqmp-gqspi.c
+155
-36
drivers/spi/spi-zynqmp-gqspi.c
···
16
16
#include <linux/module.h>
17
17
#include <linux/of_irq.h>
18
18
#include <linux/of_address.h>
19
+
#include <linux/of_device.h>
19
20
#include <linux/platform_device.h>
20
21
#include <linux/pm_runtime.h>
21
22
#include <linux/spi/spi.h>
···
35
34
#define GQSPI_RXD_OFST 0x00000120
36
35
#define GQSPI_TX_THRESHOLD_OFST 0x00000128
37
36
#define GQSPI_RX_THRESHOLD_OFST 0x0000012C
37
+
#define IOU_TAPDLY_BYPASS_OFST 0x0000003C
38
38
#define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
39
39
#define GQSPI_GEN_FIFO_OFST 0x00000140
40
40
#define GQSPI_SEL_OFST 0x00000144
···
50
48
#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
51
49
#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
52
50
#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
51
+
#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8
53
52
54
53
/* GQSPI register bit masks */
55
54
#define GQSPI_SEL_MASK 0x00000001
···
139
136
140
137
#define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */
141
138
139
+
#define GQSPI_USE_DATA_DLY 0x1
140
+
#define GQSPI_USE_DATA_DLY_SHIFT 31
141
+
#define GQSPI_DATA_DLY_ADJ_VALUE 0x2
142
+
#define GQSPI_DATA_DLY_ADJ_SHIFT 28
143
+
#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1
144
+
#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 0x3
145
+
#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
146
+
#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 0x2
147
+
148
+
/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
149
+
#define QSPI_QUIRK_HAS_TAPDELAY BIT(0)
150
+
151
+
#define GQSPI_FREQ_37_5MHZ 37500000
152
+
#define GQSPI_FREQ_40MHZ 40000000
153
+
#define GQSPI_FREQ_100MHZ 100000000
154
+
#define GQSPI_FREQ_150MHZ 150000000
155
+
142
156
#define SPI_AUTOSUSPEND_TIMEOUT 3000
143
157
enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
144
158
145
159
/**
160
+
* struct qspi_platform_data - zynqmp qspi platform data structure
161
+
* @quirks: Flags is used to identify the platform
162
+
*/
163
+
struct qspi_platform_data {
164
+
u32 quirks;
165
+
};
166
+
167
+
/**
146
168
* struct zynqmp_qspi - Defines qspi driver instance
169
+
* @ctlr: Pointer to the spi controller information
147
170
* @regs: Virtual address of the QSPI controller registers
148
171
* @refclk: Pointer to the peripheral clock
149
172
* @pclk: Pointer to the APB clock
···
186
157
* @genfifoentry: Used for storing the genfifoentry instruction.
187
158
* @mode: Defines the mode in which QSPI is operating
188
159
* @data_completion: completion structure
160
+
* @op_lock: Operational lock
161
+
* @speed_hz: Current SPI bus clock speed in hz
162
+
* @has_tapdelay: Used for tapdelay register available in qspi
189
163
*/
190
164
struct zynqmp_qspi {
191
165
struct spi_controller *ctlr;
···
209
177
enum mode_type mode;
210
178
struct completion data_completion;
211
179
struct mutex op_lock;
180
+
u32 speed_hz;
181
+
bool has_tapdelay;
212
182
};
213
183
214
184
/**
···
284
250
}
285
251
286
252
/**
253
+
* zynqmp_qspi_set_tapdelay: To configure qspi tap delays
254
+
* @xqspi: Pointer to the zynqmp_qspi structure
255
+
* @baudrateval: Buadrate to configure
256
+
*/
257
+
static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
258
+
{
259
+
u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
260
+
u32 reqhz = 0;
261
+
262
+
clk_rate = clk_get_rate(xqspi->refclk);
263
+
reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
264
+
265
+
if (!xqspi->has_tapdelay) {
266
+
if (reqhz <= GQSPI_FREQ_40MHZ) {
267
+
zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
268
+
PM_TAPDELAY_BYPASS_ENABLE);
269
+
} else if (reqhz <= GQSPI_FREQ_100MHZ) {
270
+
zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
271
+
PM_TAPDELAY_BYPASS_ENABLE);
272
+
lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
273
+
datadlyadj |= ((GQSPI_USE_DATA_DLY <<
274
+
GQSPI_USE_DATA_DLY_SHIFT)
275
+
| (GQSPI_DATA_DLY_ADJ_VALUE <<
276
+
GQSPI_DATA_DLY_ADJ_SHIFT));
277
+
} else if (reqhz <= GQSPI_FREQ_150MHZ) {
278
+
lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;
279
+
}
280
+
} else {
281
+
if (reqhz <= GQSPI_FREQ_37_5MHZ) {
282
+
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
283
+
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
284
+
} else if (reqhz <= GQSPI_FREQ_100MHZ) {
285
+
tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
286
+
TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
287
+
lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
288
+
datadlyadj |= (GQSPI_USE_DATA_DLY <<
289
+
GQSPI_USE_DATA_DLY_SHIFT);
290
+
} else if (reqhz <= GQSPI_FREQ_150MHZ) {
291
+
lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
292
+
| (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
293
+
GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));
294
+
}
295
+
zynqmp_gqspi_write(xqspi,
296
+
IOU_TAPDLY_BYPASS_OFST, tapdlybypass);
297
+
}
298
+
zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
299
+
zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
300
+
}
301
+
302
+
/**
287
303
* zynqmp_qspi_init_hw - Initialize the hardware
288
304
* @xqspi: Pointer to the zynqmp_qspi structure
289
305
*
···
348
264
* - Enable manual slave select
349
265
* - Enable manual start
350
266
* - Deselect all the chip select lines
351
-
* - Set the little endian mode of TX FIFO and
267
+
* - Set the little endian mode of TX FIFO
268
+
* - Set clock phase
269
+
* - Set clock polarity and
352
270
* - Enable the QSPI controller
353
271
*/
354
272
static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
355
273
{
356
-
u32 config_reg;
274
+
u32 config_reg, baud_rate_val = 0;
275
+
ulong clk_rate;
357
276
358
277
/* Select the GQSPI mode */
359
278
zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
···
390
303
config_reg |= GQSPI_CFG_WP_HOLD_MASK;
391
304
/* Clear pre-scalar by default */
392
305
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
393
-
/* CPHA 0 */
394
-
config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
395
-
/* CPOL 0 */
396
-
config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
306
+
/* Set CPHA */
307
+
if (xqspi->ctlr->mode_bits & SPI_CPHA)
308
+
config_reg |= GQSPI_CFG_CLK_PHA_MASK;
309
+
else
310
+
config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
311
+
/* Set CPOL */
312
+
if (xqspi->ctlr->mode_bits & SPI_CPOL)
313
+
config_reg |= GQSPI_CFG_CLK_POL_MASK;
314
+
else
315
+
config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
316
+
317
+
/* Set the clock frequency */
318
+
clk_rate = clk_get_rate(xqspi->refclk);
319
+
while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
320
+
(clk_rate /
321
+
(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
322
+
baud_rate_val++;
323
+
324
+
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
325
+
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
326
+
397
327
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
328
+
329
+
/* Set the tapdelay for clock frequency */
330
+
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
398
331
399
332
/* Clear the TX and RX FIFO */
400
333
zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
401
334
GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
402
335
GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
403
336
GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
404
-
/* Set by default to allow for high frequencies */
405
-
zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
406
-
zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
407
-
GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
408
337
/* Reset thresholds */
409
338
zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
410
339
GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
···
558
455
struct spi_device *qspi)
559
456
{
560
457
ulong clk_rate;
561
-
u32 config_reg, baud_rate_val = 0;
458
+
u32 config_reg, req_speed_hz, baud_rate_val = 0;
562
459
563
-
/* Set the clock frequency */
564
-
/* If req_hz == 0, default to lowest speed */
565
-
clk_rate = clk_get_rate(xqspi->refclk);
460
+
req_speed_hz = qspi->max_speed_hz;
566
461
567
-
while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
568
-
(clk_rate /
569
-
(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz)
570
-
baud_rate_val++;
462
+
if (xqspi->speed_hz != req_speed_hz) {
463
+
xqspi->speed_hz = req_speed_hz;
571
464
572
-
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
465
+
/* Set the clock frequency */
466
+
/* If req_speed_hz == 0, default to lowest speed */
467
+
clk_rate = clk_get_rate(xqspi->refclk);
573
468
574
-
/* Set the QSPI clock phase and clock polarity */
575
-
config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
469
+
while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
470
+
(clk_rate /
471
+
(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >
472
+
req_speed_hz)
473
+
baud_rate_val++;
576
474
577
-
if (qspi->mode & SPI_CPHA)
578
-
config_reg |= GQSPI_CFG_CLK_PHA_MASK;
579
-
if (qspi->mode & SPI_CPOL)
580
-
config_reg |= GQSPI_CFG_CLK_POL_MASK;
475
+
config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
581
476
582
-
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
583
-
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
584
-
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
477
+
config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
478
+
config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
479
+
zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
480
+
zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
481
+
}
585
482
return 0;
586
483
}
587
484
···
842
739
/**
843
740
* zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
844
741
* @xqspi: xqspi is a pointer to the GQSPI instance.
742
+
*
743
+
* Return: 0 on success; error value otherwise.
845
744
*/
846
745
static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
847
746
{
···
928
823
* @rx_nbits: Receive buswidth.
929
824
* @genfifoentry: genfifoentry is pointer to the variable in which
930
825
* GENFIFO mask is returned to calling function
826
+
*
827
+
* Return: 0 on success; error value otherwise.
931
828
*/
932
829
static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
933
830
u32 genfifoentry)
···
1194
1087
SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1195
1088
};
1196
1089
1090
+
static const struct qspi_platform_data versal_qspi_def = {
1091
+
.quirks = QSPI_QUIRK_HAS_TAPDELAY,
1092
+
};
1093
+
1094
+
static const struct of_device_id zynqmp_qspi_of_match[] = {
1095
+
{ .compatible = "xlnx,zynqmp-qspi-1.0"},
1096
+
{ .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
1097
+
{ /* End of table */ }
1098
+
};
1099
+
1197
1100
static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1198
1101
.exec_op = zynqmp_qspi_exec_op,
1199
1102
};
···
1224
1107
struct device *dev = &pdev->dev;
1225
1108
struct device_node *np = dev->of_node;
1226
1109
u32 num_cs;
1110
+
const struct qspi_platform_data *p_data;
1227
1111
1228
1112
ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1229
1113
if (!ctlr)
···
1234
1116
xqspi->dev = dev;
1235
1117
xqspi->ctlr = ctlr;
1236
1118
platform_set_drvdata(pdev, xqspi);
1119
+
1120
+
p_data = of_device_get_match_data(&pdev->dev);
1121
+
if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
1122
+
xqspi->has_tapdelay = true;
1237
1123
1238
1124
xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1239
1125
if (IS_ERR(xqspi->regs)) {
···
1286
1164
goto clk_dis_all;
1287
1165
}
1288
1166
1167
+
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1168
+
SPI_TX_DUAL | SPI_TX_QUAD;
1169
+
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1170
+
xqspi->speed_hz = ctlr->max_speed_hz;
1171
+
1289
1172
/* QSPI controller initializations */
1290
1173
zynqmp_qspi_init_hw(xqspi);
1291
1174
···
1326
1199
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1327
1200
ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1328
1201
ctlr->setup = zynqmp_qspi_setup_op;
1329
-
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1330
1202
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1331
-
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1332
-
SPI_TX_DUAL | SPI_TX_QUAD;
1333
1203
ctlr->dev.of_node = np;
1334
1204
ctlr->auto_runtime_pm = true;
1335
1205
···
1376
1252
1377
1253
return 0;
1378
1254
}
1379
-
1380
-
static const struct of_device_id zynqmp_qspi_of_match[] = {
1381
-
{ .compatible = "xlnx,zynqmp-qspi-1.0", },
1382
-
{ /* End of table */ }
1383
-
};
1384
1255
1385
1256
MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1386
1257
+68
-2
drivers/spi/spi.c
+68
-2
drivers/spi/spi.c
···
127
127
unsigned int start; \
128
128
pcpu_stats = per_cpu_ptr(in, i); \
129
129
do { \
130
-
start = u64_stats_fetch_begin_irq( \
130
+
start = u64_stats_fetch_begin( \
131
131
&pcpu_stats->syncp); \
132
132
inc = u64_stats_read(&pcpu_stats->field); \
133
-
} while (u64_stats_fetch_retry_irq( \
133
+
} while (u64_stats_fetch_retry( \
134
134
&pcpu_stats->syncp, start)); \
135
135
ret += inc; \
136
136
} \
···
359
359
return spi_match_id(sdrv->id_table, sdev->modalias);
360
360
}
361
361
EXPORT_SYMBOL_GPL(spi_get_device_id);
362
+
363
+
const void *spi_get_device_match_data(const struct spi_device *sdev)
364
+
{
365
+
const void *match;
366
+
367
+
match = device_get_match_data(&sdev->dev);
368
+
if (match)
369
+
return match;
370
+
371
+
return (const void *)spi_get_device_id(sdev)->driver_data;
372
+
}
373
+
EXPORT_SYMBOL_GPL(spi_get_device_match_data);
362
374
363
375
static int spi_match_device(struct device *dev, struct device_driver *drv)
364
376
{
···
2224
2212
struct device_node *nc)
2225
2213
{
2226
2214
u32 value;
2215
+
u16 cs_setup;
2227
2216
int rc;
2228
2217
2229
2218
/* Mode (clock phase/polarity/etc.) */
···
2309
2296
/* Device speed */
2310
2297
if (!of_property_read_u32(nc, "spi-max-frequency", &value))
2311
2298
spi->max_speed_hz = value;
2299
+
2300
+
if (!of_property_read_u16(nc, "spi-cs-setup-ns", &cs_setup)) {
2301
+
spi->cs_setup.value = cs_setup;
2302
+
spi->cs_setup.unit = SPI_DELAY_UNIT_NSECS;
2303
+
}
2312
2304
2313
2305
return 0;
2314
2306
}
···
2776
2758
return -ENOTSUPP;
2777
2759
}
2778
2760
EXPORT_SYMBOL_GPL(spi_slave_abort);
2761
+
2762
+
int spi_target_abort(struct spi_device *spi)
2763
+
{
2764
+
struct spi_controller *ctlr = spi->controller;
2765
+
2766
+
if (spi_controller_is_target(ctlr) && ctlr->target_abort)
2767
+
return ctlr->target_abort(ctlr);
2768
+
2769
+
return -ENOTSUPP;
2770
+
}
2771
+
EXPORT_SYMBOL_GPL(spi_target_abort);
2779
2772
2780
2773
static ssize_t slave_show(struct device *dev, struct device_attribute *attr,
2781
2774
char *buf)
···
3622
3593
}
3623
3594
3624
3595
/**
3596
+
* spi_set_cs_timing - configure CS setup, hold, and inactive delays
3597
+
* @spi: the device that requires specific CS timing configuration
3598
+
*
3599
+
* Return: zero on success, else a negative error code.
3600
+
*/
3601
+
static int spi_set_cs_timing(struct spi_device *spi)
3602
+
{
3603
+
struct device *parent = spi->controller->dev.parent;
3604
+
int status = 0;
3605
+
3606
+
if (spi->controller->set_cs_timing && !spi->cs_gpiod) {
3607
+
if (spi->controller->auto_runtime_pm) {
3608
+
status = pm_runtime_get_sync(parent);
3609
+
if (status < 0) {
3610
+
pm_runtime_put_noidle(parent);
3611
+
dev_err(&spi->controller->dev, "Failed to power device: %d\n",
3612
+
status);
3613
+
return status;
3614
+
}
3615
+
3616
+
status = spi->controller->set_cs_timing(spi);
3617
+
pm_runtime_mark_last_busy(parent);
3618
+
pm_runtime_put_autosuspend(parent);
3619
+
} else {
3620
+
status = spi->controller->set_cs_timing(spi);
3621
+
}
3622
+
}
3623
+
return status;
3624
+
}
3625
+
3626
+
/**
3625
3627
* spi_setup - setup SPI mode and clock rate
3626
3628
* @spi: the device whose settings are being modified
3627
3629
* Context: can sleep, and no requests are queued to the device
···
3746
3686
status);
3747
3687
return status;
3748
3688
}
3689
+
}
3690
+
3691
+
status = spi_set_cs_timing(spi);
3692
+
if (status) {
3693
+
mutex_unlock(&spi->controller->io_mutex);
3694
+
return status;
3749
3695
}
3750
3696
3751
3697
if (spi->controller->auto_runtime_pm && spi->controller->set_cs) {
+16
-5
drivers/spi/spidev.c
+16
-5
drivers/spi/spidev.c
···
377
377
switch (cmd) {
378
378
/* read requests */
379
379
case SPI_IOC_RD_MODE:
380
-
retval = put_user(spi->mode & SPI_MODE_MASK,
381
-
(__u8 __user *)arg);
382
-
break;
383
380
case SPI_IOC_RD_MODE32:
384
-
retval = put_user(spi->mode & SPI_MODE_MASK,
385
-
(__u32 __user *)arg);
381
+
tmp = spi->mode;
382
+
383
+
{
384
+
struct spi_controller *ctlr = spi->controller;
385
+
386
+
if (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&
387
+
ctlr->cs_gpiods[spi->chip_select])
388
+
tmp &= ~SPI_CS_HIGH;
389
+
}
390
+
391
+
if (cmd == SPI_IOC_RD_MODE)
392
+
retval = put_user(tmp & SPI_MODE_MASK,
393
+
(__u8 __user *)arg);
394
+
else
395
+
retval = put_user(tmp & SPI_MODE_MASK,
396
+
(__u32 __user *)arg);
386
397
break;
387
398
case SPI_IOC_RD_LSB_FIRST:
388
399
retval = put_user((spi->mode & SPI_LSB_FIRST) ? 1 : 0,
+19
include/linux/firmware/xlnx-zynqmp.h
+19
include/linux/firmware/xlnx-zynqmp.h
···
135
135
};
136
136
137
137
enum pm_ioctl_id {
138
+
IOCTL_SET_TAPDELAY_BYPASS = 4,
138
139
IOCTL_SD_DLL_RESET = 6,
139
140
IOCTL_SET_SD_TAPDELAY = 7,
140
141
IOCTL_SET_PLL_FRAC_MODE = 8,
···
390
389
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
391
390
};
392
391
392
+
enum tap_delay_signal_type {
393
+
PM_TAPDELAY_NAND_DQS_IN = 0,
394
+
PM_TAPDELAY_NAND_DQS_OUT = 1,
395
+
PM_TAPDELAY_QSPI = 2,
396
+
PM_TAPDELAY_MAX = 3,
397
+
};
398
+
399
+
enum tap_delay_bypass_ctrl {
400
+
PM_TAPDELAY_BYPASS_DISABLE = 0,
401
+
PM_TAPDELAY_BYPASS_ENABLE = 1,
402
+
};
403
+
393
404
enum ospi_mux_select_type {
394
405
PM_OSPI_MUX_SEL_DMA = 0,
395
406
PM_OSPI_MUX_SEL_LINEAR = 1,
···
497
484
int zynqmp_pm_read_ggs(u32 index, u32 *value);
498
485
int zynqmp_pm_write_pggs(u32 index, u32 value);
499
486
int zynqmp_pm_read_pggs(u32 index, u32 *value);
487
+
int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
500
488
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
501
489
int zynqmp_pm_set_boot_health_status(u32 value);
502
490
int zynqmp_pm_pinctrl_request(const u32 pin);
···
706
692
}
707
693
708
694
static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
695
+
{
696
+
return -ENODEV;
697
+
}
698
+
699
+
static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
709
700
{
710
701
return -ENODEV;
711
702
}
+1
include/linux/pxa2xx_ssp.h
+1
include/linux/pxa2xx_ssp.h
+51
-3
include/linux/spi/spi.h
+51
-3
include/linux/spi/spi.h
···
356
356
* @max_speed_hz: Highest supported transfer speed
357
357
* @flags: other constraints relevant to this driver
358
358
* @slave: indicates that this is an SPI slave controller
359
+
* @target: indicates that this is an SPI target controller
359
360
* @devm_allocated: whether the allocation of this struct is devres-managed
360
361
* @max_transfer_size: function that returns the max transfer size for
361
362
* a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
···
441
440
* @mem_caps: controller capabilities for the handling of memory operations.
442
441
* @unprepare_message: undo any work done by prepare_message().
443
442
* @slave_abort: abort the ongoing transfer request on an SPI slave controller
443
+
* @target_abort: abort the ongoing transfer request on an SPI target controller
444
444
* @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
445
445
* number. Any individual value may be NULL for CS lines that
446
446
* are not GPIOs (driven by the SPI controller itself).
···
537
535
/* Flag indicating if the allocation of this struct is devres-managed */
538
536
bool devm_allocated;
539
537
540
-
/* Flag indicating this is an SPI slave controller */
541
-
bool slave;
538
+
union {
539
+
/* Flag indicating this is an SPI slave controller */
540
+
bool slave;
541
+
/* Flag indicating this is an SPI target controller */
542
+
bool target;
543
+
};
542
544
543
545
/*
544
546
* on some hardware transfer / message size may be constrained
···
655
649
struct spi_message *message);
656
650
int (*unprepare_message)(struct spi_controller *ctlr,
657
651
struct spi_message *message);
658
-
int (*slave_abort)(struct spi_controller *ctlr);
652
+
union {
653
+
int (*slave_abort)(struct spi_controller *ctlr);
654
+
int (*target_abort)(struct spi_controller *ctlr);
655
+
};
659
656
660
657
/*
661
658
* These hooks are for drivers that use a generic implementation
···
736
727
return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
737
728
}
738
729
730
+
static inline bool spi_controller_is_target(struct spi_controller *ctlr)
731
+
{
732
+
return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;
733
+
}
734
+
739
735
/* PM calls that need to be issued by the driver */
740
736
extern int spi_controller_suspend(struct spi_controller *ctlr);
741
737
extern int spi_controller_resume(struct spi_controller *ctlr);
···
777
763
return __spi_alloc_controller(host, size, true);
778
764
}
779
765
766
+
static inline struct spi_controller *spi_alloc_host(struct device *dev,
767
+
unsigned int size)
768
+
{
769
+
return __spi_alloc_controller(dev, size, false);
770
+
}
771
+
772
+
static inline struct spi_controller *spi_alloc_target(struct device *dev,
773
+
unsigned int size)
774
+
{
775
+
if (!IS_ENABLED(CONFIG_SPI_SLAVE))
776
+
return NULL;
777
+
778
+
return __spi_alloc_controller(dev, size, true);
779
+
}
780
+
780
781
struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
781
782
unsigned int size,
782
783
bool slave);
···
804
775
805
776
static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev,
806
777
unsigned int size)
778
+
{
779
+
if (!IS_ENABLED(CONFIG_SPI_SLAVE))
780
+
return NULL;
781
+
782
+
return __devm_spi_alloc_controller(dev, size, true);
783
+
}
784
+
785
+
static inline struct spi_controller *devm_spi_alloc_host(struct device *dev,
786
+
unsigned int size)
787
+
{
788
+
return __devm_spi_alloc_controller(dev, size, false);
789
+
}
790
+
791
+
static inline struct spi_controller *devm_spi_alloc_target(struct device *dev,
792
+
unsigned int size)
807
793
{
808
794
if (!IS_ENABLED(CONFIG_SPI_SLAVE))
809
795
return NULL;
···
1185
1141
extern int spi_setup(struct spi_device *spi);
1186
1142
extern int spi_async(struct spi_device *spi, struct spi_message *message);
1187
1143
extern int spi_slave_abort(struct spi_device *spi);
1144
+
extern int spi_target_abort(struct spi_device *spi);
1188
1145
1189
1146
static inline size_t
1190
1147
spi_max_message_size(struct spi_device *spi)
···
1558
1513
1559
1514
extern const struct spi_device_id *
1560
1515
spi_get_device_id(const struct spi_device *sdev);
1516
+
1517
+
extern const void *
1518
+
spi_get_device_match_data(const struct spi_device *sdev);
1561
1519
1562
1520
static inline bool
1563
1521
spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)