Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-gt-next-2025-02-26' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
UAPI Changes:
- Add sysfs for SLPC power profiles [slpc] (Vinay Belgaumkar)
Driver Changes:
Fixes/improvements/new stuff:
- Fix zero delta busyness issue [pmu] (Umesh Nerlige Ramappa)
- Fix page cleanup on DMA remap failure (Brian Geffon)
- Debug print LRC state entries only if the context is pinned [guc] (Daniele Ceraolo Spurio)
- Drop custom hotplug code [pmu] (Lucas De Marchi)
- Use spin_lock_irqsave() in interruptible context [guc] (Krzysztof Karas)
- Add wait on depth stall done bit handling [gen12] (Juha-Pekka Heikkila)
Miscellaneous:
- Change throttle criteria for rps [selftest] (Raag Jadav)
- Add debug print about hw config table size (John Harrison)
- Include requested frequency in slow firmware load messages [uc] (John Harrison)
- Remove i915_pmu_event_event_idx() [pmu] (Lucas De Marchi)
- Remove unused live_context_for_engine (Dr. David Alan Gilbert)
- Add Wa_22010465259 in its respective WA list (Ranu Maurya)
- Correct frequency handling in RPS power measurement [selftests] (Sk Anirban)
- Add helper function slpc_measure_power [guc/slpc] (Sk Anirban)
- Revert "drm/i915/gt: Log reason for setting TAINT_WARN at reset" [gt] (Sebastian Brzezinka)
- Avoid using uninitialized context [selftests] (Krzysztof Karas)
- Use struct_size() helper in kmalloc() (luoqing)
- Use prandom in selftest [selftests] (Markus Theil)
- Replace kmap with its safer kmap_local_page counterpart [gt] (Andi Shyti)
Merges:
- Merge drm/drm-next into drm-intel-gt-next (Tvrtko Ursulin)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z77NLt2mR7SqxJ4u@linux
+193
-212
-38
drivers/gpu/drm/i915/gem/selftests/mock_context.c
-38
drivers/gpu/drm/i915/gem/selftests/mock_context.c
···
108
108
}
109
109
110
110
struct i915_gem_context *
111
-
live_context_for_engine(struct intel_engine_cs *engine, struct file *file)
112
-
{
113
-
struct i915_gem_engines *engines;
114
-
struct i915_gem_context *ctx;
115
-
struct intel_sseu null_sseu = {};
116
-
struct intel_context *ce;
117
-
118
-
engines = alloc_engines(1);
119
-
if (!engines)
120
-
return ERR_PTR(-ENOMEM);
121
-
122
-
ctx = live_context(engine->i915, file);
123
-
if (IS_ERR(ctx)) {
124
-
__free_engines(engines, 0);
125
-
return ctx;
126
-
}
127
-
128
-
ce = intel_context_create(engine);
129
-
if (IS_ERR(ce)) {
130
-
__free_engines(engines, 0);
131
-
return ERR_CAST(ce);
132
-
}
133
-
134
-
intel_context_set_gem(ce, ctx, null_sseu);
135
-
engines->engines[0] = ce;
136
-
engines->num_engines = 1;
137
-
138
-
mutex_lock(&ctx->engines_mutex);
139
-
i915_gem_context_set_user_engines(ctx);
140
-
engines = rcu_replace_pointer(ctx->engines, engines, 1);
141
-
mutex_unlock(&ctx->engines_mutex);
142
-
143
-
engines_idle_release(ctx, engines);
144
-
145
-
return ctx;
146
-
}
147
-
148
-
struct i915_gem_context *
149
111
kernel_context(struct drm_i915_private *i915,
150
112
struct i915_address_space *vm)
151
113
{
-3
drivers/gpu/drm/i915/gem/selftests/mock_context.h
-3
drivers/gpu/drm/i915/gem/selftests/mock_context.h
···
23
23
struct i915_gem_context *
24
24
live_context(struct drm_i915_private *i915, struct file *file);
25
25
26
-
struct i915_gem_context *
27
-
live_context_for_engine(struct intel_engine_cs *engine, struct file *file);
28
-
29
26
struct i915_gem_context *kernel_context(struct drm_i915_private *i915,
30
27
struct i915_address_space *vm);
31
28
void kernel_context_close(struct i915_gem_context *ctx);
+1
-2
drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c
+1
-2
drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c
+2
-2
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+2
-2
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
···
750
750
char *vaddr;
751
751
int i;
752
752
753
-
vaddr = kmap(page);
753
+
vaddr = kmap_local_page(page);
754
754
755
755
for (i = 0; i < PAGE_SIZE; i += 128) {
756
756
memcpy(temp, &vaddr[i], 64);
···
758
758
memcpy(&vaddr[i + 64], temp, 64);
759
759
}
760
760
761
-
kunmap(page);
761
+
kunmap_local(vaddr);
762
762
}
763
763
764
764
/**
+3
drivers/gpu/drm/i915/gt/intel_gt_regs.h
+3
drivers/gpu/drm/i915/gt/intel_gt_regs.h
···
409
409
#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
410
410
#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
411
411
412
+
#define GEN8_WM_CHICKEN2 MCR_REG(0x5584)
413
+
#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5)
414
+
412
415
#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
413
416
#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
414
417
+47
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+47
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
···
464
464
return err ?: count;
465
465
}
466
466
467
+
static ssize_t slpc_power_profile_show(struct kobject *kobj,
468
+
struct kobj_attribute *attr,
469
+
char *buff)
470
+
{
471
+
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
472
+
struct intel_guc_slpc *slpc = >->uc.guc.slpc;
473
+
474
+
switch (slpc->power_profile) {
475
+
case SLPC_POWER_PROFILES_BASE:
476
+
return sysfs_emit(buff, "[%s] %s\n", "base", "power_saving");
477
+
case SLPC_POWER_PROFILES_POWER_SAVING:
478
+
return sysfs_emit(buff, "%s [%s]\n", "base", "power_saving");
479
+
}
480
+
481
+
return sysfs_emit(buff, "%u\n", slpc->power_profile);
482
+
}
483
+
484
+
static ssize_t slpc_power_profile_store(struct kobject *kobj,
485
+
struct kobj_attribute *attr,
486
+
const char *buff, size_t count)
487
+
{
488
+
struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name);
489
+
struct intel_guc_slpc *slpc = >->uc.guc.slpc;
490
+
char power_saving[] = "power_saving";
491
+
char base[] = "base";
492
+
int err;
493
+
u32 val;
494
+
495
+
if (!strncmp(buff, power_saving, sizeof(power_saving) - 1))
496
+
val = SLPC_POWER_PROFILES_POWER_SAVING;
497
+
else if (!strncmp(buff, base, sizeof(base) - 1))
498
+
val = SLPC_POWER_PROFILES_BASE;
499
+
else
500
+
return -EINVAL;
501
+
502
+
err = intel_guc_slpc_set_power_profile(slpc, val);
503
+
return err ?: count;
504
+
}
505
+
467
506
struct intel_gt_bool_throttle_attr {
468
507
struct attribute attr;
469
508
ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
···
707
668
INTEL_GT_ATTR_RO(media_RPn_freq_mhz);
708
669
709
670
INTEL_GT_ATTR_RW(slpc_ignore_eff_freq);
671
+
INTEL_GT_ATTR_RW(slpc_power_profile);
710
672
711
673
static const struct attribute *media_perf_power_attrs[] = {
712
674
&attr_media_freq_factor.attr,
···
902
862
ret = sysfs_create_file(kobj, &attr_slpc_ignore_eff_freq.attr);
903
863
if (ret)
904
864
gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret));
865
+
}
866
+
867
+
if (intel_uc_uses_guc_slpc(>->uc)) {
868
+
ret = sysfs_create_file(kobj, &attr_slpc_power_profile.attr);
869
+
if (ret)
870
+
gt_warn(gt, "failed to create slpc_power_profile sysfs (%pe)",
871
+
ERR_PTR(ret));
905
872
}
906
873
907
874
if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) {
+1
-5
drivers/gpu/drm/i915/gt/intel_reset.c
+1
-5
drivers/gpu/drm/i915/gt/intel_reset.c
···
1113
1113
* Warn CI about the unrecoverable wedged condition.
1114
1114
* Time for a reboot.
1115
1115
*/
1116
-
gt_err(gt, "Unrecoverable wedged condition\n");
1117
1116
add_taint_for_CI(gt->i915, TAINT_WARN);
1118
1117
return false;
1119
1118
}
···
1271
1272
}
1272
1273
1273
1274
ret = resume(gt);
1274
-
if (ret) {
1275
-
gt_err(gt, "Failed to resume (%d)\n", ret);
1275
+
if (ret)
1276
1276
goto taint;
1277
-
}
1278
1277
1279
1278
finish:
1280
1279
reset_finish(gt, awake);
···
1638
1641
set_bit(I915_WEDGED_ON_INIT, >->reset.flags);
1639
1642
1640
1643
/* Wedged on init is non-recoverable */
1641
-
gt_err(gt, "Non-recoverable wedged on init\n");
1642
1644
add_taint_for_CI(gt->i915, TAINT_WARN);
1643
1645
}
1644
1646
+4
drivers/gpu/drm/i915/gt/intel_rps.c
+4
drivers/gpu/drm/i915/gt/intel_rps.c
···
1025
1025
if (rps_uses_slpc(rps)) {
1026
1026
slpc = rps_to_slpc(rps);
1027
1027
1028
+
/* Waitboost should not be done with power saving profile */
1029
+
if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING)
1030
+
return;
1031
+
1028
1032
if (slpc->min_freq_softlimit >= slpc->boost_freq)
1029
1033
return;
1030
1034
+13
-6
drivers/gpu/drm/i915/gt/intel_workarounds.c
+13
-6
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
691
691
struct drm_i915_private *i915 = engine->i915;
692
692
693
693
/*
694
-
* Wa_1409142259:tgl,dg1,adl-p
694
+
* Wa_1409142259:tgl,dg1,adl-p,adl-n
695
695
* Wa_1409347922:tgl,dg1,adl-p
696
696
* Wa_1409252684:tgl,dg1,adl-p
697
697
* Wa_1409217633:tgl,dg1,adl-p
698
698
* Wa_1409207793:tgl,dg1,adl-p
699
-
* Wa_1409178076:tgl,dg1,adl-p
700
-
* Wa_1408979724:tgl,dg1,adl-p
701
-
* Wa_14010443199:tgl,rkl,dg1,adl-p
702
-
* Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p
703
-
* Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p
699
+
* Wa_1409178076:tgl,dg1,adl-p,adl-n
700
+
* Wa_1408979724:tgl,dg1,adl-p,adl-n
701
+
* Wa_14010443199:tgl,rkl,dg1,adl-p,adl-n
702
+
* Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p,adl-n
703
+
* Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p,adl-n
704
+
* Wa_22010465259:tgl,rkl,dg1,adl-s,adl-p,adl-n
704
705
*/
705
706
wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
706
707
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
···
742
741
/* Wa_1606376872 */
743
742
wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
744
743
}
744
+
745
+
/*
746
+
* This bit must be set to enable performance optimization for fast
747
+
* clears.
748
+
*/
749
+
wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, WAIT_ON_DEPTH_STALL_DONE_DISABLE);
745
750
}
746
751
747
752
static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+7
-6
drivers/gpu/drm/i915/gt/selftest_rps.c
+7
-6
drivers/gpu/drm/i915/gt/selftest_rps.c
···
477
477
limit, intel_gpu_freq(rps, limit),
478
478
min, max, ktime_to_ns(min_dt), ktime_to_ns(max_dt));
479
479
480
-
if (limit == rps->min_freq) {
481
-
pr_err("%s: GPU throttled to minimum!\n",
482
-
engine->name);
480
+
if (limit != rps->max_freq) {
481
+
u32 throttle = intel_uncore_read(gt->uncore,
482
+
intel_gt_perf_limit_reasons_reg(gt));
483
+
484
+
pr_warn("%s: GPU throttled with reasons 0x%08x\n",
485
+
engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK);
483
486
show_pstate_limits(rps);
484
-
err = -ENODEV;
485
-
break;
486
487
}
487
488
488
489
if (igt_flush_test(gt->i915)) {
···
1116
1115
for (i = 0; i < 5; i++)
1117
1116
x[i] = __measure_power(5);
1118
1117
1119
-
*freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2;
1118
+
*freq = (*freq + read_cagf(rps)) / 2;
1120
1119
1121
1120
/* A simple triangle filter for better result stability */
1122
1121
sort(x, 5, sizeof(*x), cmp_u64, NULL);
+16
-1
drivers/gpu/drm/i915/gt/selftest_slpc.c
+16
-1
drivers/gpu/drm/i915/gt/selftest_slpc.c
···
95
95
return 0;
96
96
}
97
97
98
+
static u64 slpc_measure_power(struct intel_rps *rps, int *freq)
99
+
{
100
+
u64 x[5];
101
+
int i;
102
+
103
+
for (i = 0; i < 5; i++)
104
+
x[i] = __measure_power(5);
105
+
106
+
*freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2;
107
+
108
+
/* A simple triangle filter for better result stability */
109
+
sort(x, 5, sizeof(*x), cmp_u64, NULL);
110
+
return div_u64(x[1] + 2 * x[2] + x[3], 4);
111
+
}
112
+
98
113
static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power)
99
114
{
100
115
int err = 0;
···
118
103
if (err)
119
104
return err;
120
105
*freq = intel_rps_read_actual_frequency(>->rps);
121
-
*power = measure_power(>->rps, freq);
106
+
*power = slpc_measure_power(>->rps, freq);
122
107
123
108
return err;
124
109
}
+4
-4
drivers/gpu/drm/i915/gt/shmem_utils.c
+4
-4
drivers/gpu/drm/i915/gt/shmem_utils.c
···
108
108
if (IS_ERR(page))
109
109
return PTR_ERR(page);
110
110
111
-
vaddr = kmap(page);
111
+
vaddr = kmap_local_page(page);
112
112
if (write) {
113
113
memcpy(vaddr + offset_in_page(off), ptr, this);
114
114
set_page_dirty(page);
···
116
116
memcpy(ptr, vaddr + offset_in_page(off), this);
117
117
}
118
118
mark_page_accessed(page);
119
-
kunmap(page);
119
+
kunmap_local(vaddr);
120
120
put_page(page);
121
121
122
122
len -= this;
···
143
143
if (IS_ERR(page))
144
144
return PTR_ERR(page);
145
145
146
-
vaddr = kmap(page);
146
+
vaddr = kmap_local_page(page);
147
147
iosys_map_memcpy_to(map, map_off, vaddr + offset_in_page(off),
148
148
this);
149
149
mark_page_accessed(page);
150
-
kunmap(page);
150
+
kunmap_local(vaddr);
151
151
put_page(page);
152
152
153
153
len -= this;
+5
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+5
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
+6
-5
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+6
-5
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
···
259
259
} else if (delta_ms > 200) {
260
260
guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
261
261
delta_ms, status, count, ret);
262
-
guc_warn(guc, "excessive init time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
263
-
intel_rps_read_actual_frequency(>->rps), before_freq,
262
+
guc_warn(guc, "excessive init time: [freq = %dMHz -> %dMHz vs %dMHz, perf_limit_reasons = 0x%08X]\n",
263
+
before_freq, intel_rps_read_actual_frequency(>->rps),
264
+
intel_rps_get_requested_frequency(>->rps),
264
265
intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
265
266
} else {
266
-
guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
267
-
delta_ms, intel_rps_read_actual_frequency(>->rps),
268
-
before_freq, status, count, ret);
267
+
guc_dbg(guc, "init took %lldms, freq = %dMHz -> %dMHz vs %dMHz, status = 0x%08X, count = %d, ret = %d\n",
268
+
delta_ms, before_freq, intel_rps_read_actual_frequency(>->rps),
269
+
intel_rps_get_requested_frequency(>->rps), status, count, ret);
269
270
}
270
271
271
272
return ret;
+3
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
+3
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c
···
7
7
#include "gt/intel_hwconfig.h"
8
8
#include "i915_drv.h"
9
9
#include "i915_memcpy.h"
10
+
#include "intel_guc_print.h"
10
11
11
12
/*
12
13
* GuC has a blob containing hardware configuration information (HWConfig).
···
43
42
};
44
43
int ret;
45
44
45
+
guc_dbg(guc, "Querying HW config table: size = %d, offset = 0x%08X\n",
46
+
ggtt_size, ggtt_offset);
46
47
ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
47
48
if (ret == -ENXIO)
48
49
return -ENOENT;
+65
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+65
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
···
15
15
#include "gt/intel_gt_regs.h"
16
16
#include "gt/intel_rps.h"
17
17
18
+
/**
19
+
* DOC: SLPC - Dynamic Frequency management
20
+
*
21
+
* Single Loop Power Control (SLPC) is a GuC algorithm that manages
22
+
* GT frequency based on busyness and how KMD initializes it. SLPC is
23
+
* almost completely in control after initialization except for a few
24
+
* scenarios mentioned below.
25
+
*
26
+
* KMD uses the concept of waitboost to ramp frequency to RP0 when there
27
+
* are pending submissions for a context. It achieves this by sending GuC a
28
+
* request to update the min frequency to RP0. Waitboost is disabled
29
+
* when the request retires.
30
+
*
31
+
* Another form of frequency control happens through per-context hints.
32
+
* A context can be marked as low latency during creation. That will ensure
33
+
* that SLPC uses an aggressive frequency ramp when that context is active.
34
+
*
35
+
* Power profiles add another level of control to these mechanisms.
36
+
* When power saving profile is chosen, SLPC will use conservative
37
+
* thresholds to ramp frequency, thus saving power. KMD will disable
38
+
* waitboosts as well, which achieves further power savings. Base profile
39
+
* is default and ensures balanced performance for any workload.
40
+
*
41
+
* Lastly, users have some level of control through sysfs, where min/max
42
+
* frequency values can be altered and the use of efficient freq
43
+
* can be toggled.
44
+
*/
45
+
18
46
static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
19
47
{
20
48
return container_of(slpc, struct intel_guc, slpc);
···
292
264
atomic_set(&slpc->num_waiters, 0);
293
265
slpc->num_boosts = 0;
294
266
slpc->media_ratio_mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
267
+
268
+
slpc->power_profile = SLPC_POWER_PROFILES_BASE;
295
269
296
270
mutex_init(&slpc->lock);
297
271
INIT_WORK(&slpc->boost_work, slpc_boost_work);
···
605
575
return ret;
606
576
}
607
577
578
+
int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val)
579
+
{
580
+
struct drm_i915_private *i915 = slpc_to_i915(slpc);
581
+
intel_wakeref_t wakeref;
582
+
int ret = 0;
583
+
584
+
if (val > SLPC_POWER_PROFILES_POWER_SAVING)
585
+
return -EINVAL;
586
+
587
+
mutex_lock(&slpc->lock);
588
+
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
589
+
590
+
ret = slpc_set_param(slpc,
591
+
SLPC_PARAM_POWER_PROFILE,
592
+
val);
593
+
if (ret)
594
+
guc_err(slpc_to_guc(slpc),
595
+
"Failed to set power profile to %d: %pe\n",
596
+
val, ERR_PTR(ret));
597
+
else
598
+
slpc->power_profile = val;
599
+
600
+
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
601
+
mutex_unlock(&slpc->lock);
602
+
603
+
return ret;
604
+
}
605
+
608
606
void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
609
607
{
610
608
u32 pm_intrmsk_mbz = 0;
···
793
735
794
736
/* Enable SLPC Optimized Strategy for compute */
795
737
intel_guc_slpc_set_strategy(slpc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
738
+
739
+
/* Set cached value of power_profile */
740
+
ret = intel_guc_slpc_set_power_profile(slpc, slpc->power_profile);
741
+
if (unlikely(ret)) {
742
+
guc_probe_error(guc, "Failed to set SLPC power profile: %pe\n", ERR_PTR(ret));
743
+
return ret;
744
+
}
796
745
797
746
return 0;
798
747
}
+1
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
+1
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
···
46
46
void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc);
47
47
int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val);
48
48
int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val);
49
+
int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val);
49
50
50
51
#endif
+3
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+3
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+7
-5
drivers/gpu/drm/i915/gt/uc/intel_huc.c
+7
-5
drivers/gpu/drm/i915/gt/uc/intel_huc.c
···
489
489
if (delta_ms > 50) {
490
490
huc_warn(huc, "excessive auth time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
491
491
delta_ms, huc->status[type].reg.reg, count, ret);
492
-
huc_warn(huc, "excessive auth time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
493
-
intel_rps_read_actual_frequency(>->rps), before_freq,
492
+
huc_warn(huc, "excessive auth time: [freq = %dMHz -> %dMHz vs %dMHz, perf_limit_reasons = 0x%08X]\n",
493
+
before_freq, intel_rps_read_actual_frequency(>->rps),
494
+
intel_rps_get_requested_frequency(>->rps),
494
495
intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
495
496
} else {
496
-
huc_dbg(huc, "auth took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
497
-
delta_ms, intel_rps_read_actual_frequency(>->rps),
498
-
before_freq, huc->status[type].reg.reg, count, ret);
497
+
huc_dbg(huc, "auth took %lldms, freq = %dMHz -> %dMHz vs %dMHz, status = 0x%08X, count = %d, ret = %d\n",
498
+
delta_ms, before_freq, intel_rps_read_actual_frequency(>->rps),
499
+
intel_rps_get_requested_frequency(>->rps),
500
+
huc->status[type].reg.reg, count, ret);
499
501
}
500
502
501
503
/* mark the load process as complete even if the wait failed */
-2
drivers/gpu/drm/i915/i915_module.c
-2
drivers/gpu/drm/i915/i915_module.c
···
71
71
{ .init = i915_vma_resource_module_init,
72
72
.exit = i915_vma_resource_module_exit },
73
73
{ .init = i915_mock_selftests },
74
-
{ .init = i915_pmu_init,
75
-
.exit = i915_pmu_exit },
76
74
{ .init = i915_pci_register_driver,
77
75
.exit = i915_pci_unregister_driver },
78
76
{ .init = i915_perf_sysctl_register,
+1
-119
drivers/gpu/drm/i915/i915_pmu.c
+1
-119
drivers/gpu/drm/i915/i915_pmu.c
···
28
28
BIT(I915_SAMPLE_WAIT) | \
29
29
BIT(I915_SAMPLE_SEMA))
30
30
31
-
static cpumask_t i915_pmu_cpumask;
32
-
static unsigned int i915_pmu_target_cpu = -1;
33
-
34
31
static struct i915_pmu *event_to_pmu(struct perf_event *event)
35
32
{
36
33
return container_of(event->pmu, struct i915_pmu, base);
···
639
642
if (event->cpu < 0)
640
643
return -EINVAL;
641
644
642
-
/* only allow running on one cpu at a time */
643
-
if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
644
-
return -EINVAL;
645
-
646
645
if (is_engine_event(event))
647
646
ret = engine_event_init(event);
648
647
else
···
884
891
i915_pmu_event_stop(event, PERF_EF_UPDATE);
885
892
}
886
893
887
-
static int i915_pmu_event_event_idx(struct perf_event *event)
888
-
{
889
-
return 0;
890
-
}
891
-
892
894
struct i915_str_attribute {
893
895
struct device_attribute attr;
894
896
const char *str;
···
927
939
eattr = container_of(attr, struct i915_ext_attribute, attr);
928
940
return sprintf(buf, "config=0x%lx\n", eattr->val);
929
941
}
930
-
931
-
static ssize_t cpumask_show(struct device *dev,
932
-
struct device_attribute *attr, char *buf)
933
-
{
934
-
return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
935
-
}
936
-
937
-
static DEVICE_ATTR_RO(cpumask);
938
-
939
-
static struct attribute *i915_cpumask_attrs[] = {
940
-
&dev_attr_cpumask.attr,
941
-
NULL,
942
-
};
943
-
944
-
static const struct attribute_group i915_pmu_cpumask_attr_group = {
945
-
.attrs = i915_cpumask_attrs,
946
-
};
947
942
948
943
#define __event(__counter, __name, __unit) \
949
944
{ \
···
1144
1173
pmu->pmu_attr = NULL;
1145
1174
}
1146
1175
1147
-
static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
1148
-
{
1149
-
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1150
-
1151
-
/* Select the first online CPU as a designated reader. */
1152
-
if (cpumask_empty(&i915_pmu_cpumask))
1153
-
cpumask_set_cpu(cpu, &i915_pmu_cpumask);
1154
-
1155
-
return 0;
1156
-
}
1157
-
1158
-
static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
1159
-
{
1160
-
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1161
-
unsigned int target = i915_pmu_target_cpu;
1162
-
1163
-
/*
1164
-
* Unregistering an instance generates a CPU offline event which we must
1165
-
* ignore to avoid incorrectly modifying the shared i915_pmu_cpumask.
1166
-
*/
1167
-
if (!pmu->registered)
1168
-
return 0;
1169
-
1170
-
if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
1171
-
target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
1172
-
1173
-
/* Migrate events if there is a valid target */
1174
-
if (target < nr_cpu_ids) {
1175
-
cpumask_set_cpu(target, &i915_pmu_cpumask);
1176
-
i915_pmu_target_cpu = target;
1177
-
}
1178
-
}
1179
-
1180
-
if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
1181
-
perf_pmu_migrate_context(&pmu->base, cpu, target);
1182
-
pmu->cpuhp.cpu = target;
1183
-
}
1184
-
1185
-
return 0;
1186
-
}
1187
-
1188
-
static enum cpuhp_state cpuhp_state = CPUHP_INVALID;
1189
-
1190
-
int i915_pmu_init(void)
1191
-
{
1192
-
int ret;
1193
-
1194
-
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
1195
-
"perf/x86/intel/i915:online",
1196
-
i915_pmu_cpu_online,
1197
-
i915_pmu_cpu_offline);
1198
-
if (ret < 0)
1199
-
pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n",
1200
-
ret);
1201
-
else
1202
-
cpuhp_state = ret;
1203
-
1204
-
return 0;
1205
-
}
1206
-
1207
-
void i915_pmu_exit(void)
1208
-
{
1209
-
if (cpuhp_state != CPUHP_INVALID)
1210
-
cpuhp_remove_multi_state(cpuhp_state);
1211
-
}
1212
-
1213
-
static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1214
-
{
1215
-
if (cpuhp_state == CPUHP_INVALID)
1216
-
return -EINVAL;
1217
-
1218
-
return cpuhp_state_add_instance(cpuhp_state, &pmu->cpuhp.node);
1219
-
}
1220
-
1221
-
static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1222
-
{
1223
-
cpuhp_state_remove_instance(cpuhp_state, &pmu->cpuhp.node);
1224
-
}
1225
-
1226
1176
void i915_pmu_register(struct drm_i915_private *i915)
1227
1177
{
1228
1178
struct i915_pmu *pmu = &i915->pmu;
1229
1179
const struct attribute_group *attr_groups[] = {
1230
1180
&i915_pmu_format_attr_group,
1231
1181
&pmu->events_attr_group,
1232
-
&i915_pmu_cpumask_attr_group,
1233
1182
NULL
1234
1183
};
1235
1184
int ret = -ENOMEM;
···
1157
1266
spin_lock_init(&pmu->lock);
1158
1267
hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1159
1268
pmu->timer.function = i915_sample;
1160
-
pmu->cpuhp.cpu = -1;
1161
1269
init_rc6(pmu);
1162
1270
1163
1271
if (IS_DGFX(i915)) {
···
1185
1295
1186
1296
pmu->base.module = THIS_MODULE;
1187
1297
pmu->base.task_ctx_nr = perf_invalid_context;
1298
+
pmu->base.scope = PERF_PMU_SCOPE_SYS_WIDE;
1188
1299
pmu->base.event_init = i915_pmu_event_init;
1189
1300
pmu->base.add = i915_pmu_event_add;
1190
1301
pmu->base.del = i915_pmu_event_del;
1191
1302
pmu->base.start = i915_pmu_event_start;
1192
1303
pmu->base.stop = i915_pmu_event_stop;
1193
1304
pmu->base.read = i915_pmu_event_read;
1194
-
pmu->base.event_idx = i915_pmu_event_event_idx;
1195
1305
1196
1306
ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1197
1307
if (ret)
1198
1308
goto err_groups;
1199
1309
1200
-
ret = i915_pmu_register_cpuhp_state(pmu);
1201
-
if (ret)
1202
-
goto err_unreg;
1203
-
1204
1310
pmu->registered = true;
1205
1311
1206
1312
return;
1207
1313
1208
-
err_unreg:
1209
-
perf_pmu_unregister(&pmu->base);
1210
1314
err_groups:
1211
1315
kfree(pmu->base.attr_groups);
1212
1316
err_attr:
···
1223
1339
pmu->registered = false;
1224
1340
1225
1341
hrtimer_cancel(&pmu->timer);
1226
-
1227
-
i915_pmu_unregister_cpuhp_state(pmu);
1228
1342
1229
1343
perf_pmu_unregister(&pmu->base);
1230
1344
kfree(pmu->base.attr_groups);
-11
drivers/gpu/drm/i915/i915_pmu.h
-11
drivers/gpu/drm/i915/i915_pmu.h
···
57
57
58
58
struct i915_pmu {
59
59
/**
60
-
* @cpuhp: Struct used for CPU hotplug handling.
61
-
*/
62
-
struct {
63
-
struct hlist_node node;
64
-
unsigned int cpu;
65
-
} cpuhp;
66
-
/**
67
60
* @base: PMU base.
68
61
*/
69
62
struct pmu base;
···
148
155
};
149
156
150
157
#ifdef CONFIG_PERF_EVENTS
151
-
int i915_pmu_init(void);
152
-
void i915_pmu_exit(void);
153
158
void i915_pmu_register(struct drm_i915_private *i915);
154
159
void i915_pmu_unregister(struct drm_i915_private *i915);
155
160
void i915_pmu_gt_parked(struct intel_gt *gt);
156
161
void i915_pmu_gt_unparked(struct intel_gt *gt);
157
162
#else
158
-
static inline int i915_pmu_init(void) { return 0; }
159
-
static inline void i915_pmu_exit(void) {}
160
163
static inline void i915_pmu_register(struct drm_i915_private *i915) {}
161
164
static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
162
165
static inline void i915_pmu_gt_parked(struct intel_gt *gt) {}
+4
-3
drivers/gpu/drm/i915/selftests/i915_gem.c
+4
-3
drivers/gpu/drm/i915/selftests/i915_gem.c
···
45
45
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
46
46
const u64 slot = ggtt->error_capture.start;
47
47
const resource_size_t size = resource_size(&i915->dsm.stolen);
48
+
struct rnd_state prng;
48
49
unsigned long page;
49
-
u32 prng = 0x12345678;
50
50
51
51
/* XXX: fsck. needs some more thought... */
52
52
if (!i915_ggtt_has_aperture(ggtt))
53
53
return;
54
+
55
+
prandom_seed_state(&prng, 0x12345678);
54
56
55
57
for (page = 0; page < size; page += PAGE_SIZE) {
56
58
const dma_addr_t dma = i915->dsm.stolen.start + page;
···
66
64
67
65
s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
68
66
for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) {
69
-
prng = next_pseudo_random32(prng);
70
-
iowrite32(prng, &s[x]);
67
+
iowrite32(prandom_u32_state(&prng), &s[x]);
71
68
}
72
69
io_mapping_unmap_atomic(s);
73
70
}