Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

-1

arch/mips/Kbuild.platforms

··· 30 30 platforms += sni 31 31 platforms += txx9 32 32 platforms += vr41xx 33 - platforms += wrppmc 34 33 35 34 # include the platform specific files 36 35 include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

+28 -48

arch/mips/Kconfig

··· 1 1 config MIPS 2 2 bool 3 3 default y 4 + select HAVE_CONTEXT_TRACKING 4 5 select HAVE_GENERIC_DMA_COHERENT 5 6 select HAVE_IDE 6 7 select HAVE_OPROFILE ··· 28 27 select HAVE_GENERIC_HARDIRQS 29 28 select GENERIC_IRQ_PROBE 30 29 select GENERIC_IRQ_SHOW 30 + select GENERIC_PCI_IOMAP 31 31 select HAVE_ARCH_JUMP_LABEL 32 32 select ARCH_WANT_IPC_PARSE_VERSION 33 33 select IRQ_FORCED_THREADING ··· 47 45 select HAVE_DEBUG_STACKOVERFLOW 48 46 49 47 menu "Machine selection" 50 - 51 - config ZONE_DMA 52 - bool 53 48 54 49 choice 55 50 prompt "System type" ··· 123 124 124 125 config BCM63XX 125 126 bool "Broadcom BCM63XX based boards" 127 + select BOOT_RAW 126 128 select CEVT_R4K 127 129 select CSRC_R4K 128 130 select DMA_NONCOHERENT 129 131 select IRQ_CPU 130 132 select SYS_HAS_CPU_MIPS32_R1 133 + select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 134 + select NR_CPUS_DEFAULT_2 131 135 select SYS_SUPPORTS_32BIT_KERNEL 132 136 select SYS_SUPPORTS_BIG_ENDIAN 133 137 select SYS_HAS_EARLY_PRINTK ··· 343 341 select DMA_NONCOHERENT 344 342 select IRQ_CPU 345 343 select IRQ_GIC 346 - select MIPS_CPU_SCACHE 347 344 select MIPS_MSC 348 345 select SYS_HAS_CPU_MIPS32_R1 349 346 select SYS_HAS_CPU_MIPS32_R2 ··· 421 420 select CSRC_POWERTV 422 421 select DMA_NONCOHERENT 423 422 select HW_HAS_PCI 424 - select SYS_HAS_EARLY_PRINTK 425 423 select SYS_HAS_CPU_MIPS32_R2 426 424 select SYS_SUPPORTS_32BIT_KERNEL 427 425 select SYS_SUPPORTS_BIG_ENDIAN ··· 713 713 Support the Mikrotik(tm) RouterBoard 532 series, 714 714 based on the IDT RC32434 SoC. 715 715 716 - config WR_PPMC 717 - bool "Wind River PPMC board" 718 - select CEVT_R4K 719 - select CSRC_R4K 720 - select IRQ_CPU 721 - select BOOT_ELF32 722 - select DMA_NONCOHERENT 723 - select HW_HAS_PCI 724 - select PCI_GT64XXX_PCI0 725 - select SWAP_IO_SPACE 726 - select SYS_HAS_CPU_MIPS32_R1 727 - select SYS_HAS_CPU_MIPS32_R2 728 - select SYS_HAS_CPU_MIPS64_R1 729 - select SYS_HAS_CPU_NEVADA 730 - select SYS_HAS_CPU_RM7000 731 - select SYS_SUPPORTS_32BIT_KERNEL 732 - select SYS_SUPPORTS_64BIT_KERNEL 733 - select SYS_SUPPORTS_BIG_ENDIAN 734 - select SYS_SUPPORTS_LITTLE_ENDIAN 735 - help 736 - This enables support for the Wind River MIPS32 4KC PPMC evaluation 737 - board, which is based on GT64120 bridge chip. 738 - 739 - config CAVIUM_OCTEON_SIMULATOR 740 - bool "Cavium Networks Octeon Simulator" 741 - select CEVT_R4K 742 - select 64BIT_PHYS_ADDR 743 - select DMA_COHERENT 744 - select SYS_SUPPORTS_64BIT_KERNEL 745 - select SYS_SUPPORTS_BIG_ENDIAN 746 - select SYS_SUPPORTS_HOTPLUG_CPU 747 - select SYS_HAS_CPU_CAVIUM_OCTEON 748 - select HOLES_IN_ZONE 749 - help 750 - The Octeon simulator is software performance model of the Cavium 751 - Octeon Processor. It supports simulating Octeon processors on x86 752 - hardware. 753 - 754 - config CAVIUM_OCTEON_REFERENCE_BOARD 755 - bool "Cavium Networks Octeon reference board" 716 + config CAVIUM_OCTEON_SOC 717 + bool "Cavium Networks Octeon SoC based boards" 756 718 select CEVT_R4K 757 719 select 64BIT_PHYS_ADDR 758 720 select DMA_COHERENT ··· 768 806 select SYS_HAS_EARLY_PRINTK 769 807 select USB_ARCH_HAS_OHCI if USB_SUPPORT 770 808 select USB_ARCH_HAS_EHCI if USB_SUPPORT 809 + select SYS_SUPPORTS_ZBOOT 810 + select SYS_SUPPORTS_ZBOOT_UART16550 771 811 help 772 812 Support for systems based on Netlogic XLR and XLS processors. 773 813 Say Y here if you have a XLR or XLS based board. ··· 796 832 select SYNC_R4K 797 833 select SYS_HAS_EARLY_PRINTK 798 834 select USE_OF 835 + select SYS_SUPPORTS_ZBOOT 836 + select SYS_SUPPORTS_ZBOOT_UART16550 799 837 help 800 838 This board is based on Netlogic XLP Processor. 801 839 Say Y here if you have a XLP based board. ··· 997 1031 config CPU_LITTLE_ENDIAN 998 1032 bool "Little endian" 999 1033 depends on SYS_SUPPORTS_LITTLE_ENDIAN 1000 - help 1001 1034 1002 1035 endchoice 1003 1036 ··· 1929 1964 1930 1965 config MIPS_VPE_LOADER 1931 1966 bool "VPE loader support." 1932 - depends on SYS_SUPPORTS_MULTITHREADING 1967 + depends on SYS_SUPPORTS_MULTITHREADING && MODULES 1933 1968 select CPU_MIPSR2_IRQ_VI 1934 1969 select CPU_MIPSR2_IRQ_EI 1935 1970 select MIPS_MT ··· 2347 2382 2348 2383 If unsure, say Y. Only embedded should say N here. 2349 2384 2385 + config CC_STACKPROTECTOR 2386 + bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 2387 + help 2388 + This option turns on the -fstack-protector GCC feature. This 2389 + feature puts, at the beginning of functions, a canary value on 2390 + the stack just before the return address, and validates 2391 + the value just before actually returning. Stack based buffer 2392 + overflows (that need to overwrite this return address) now also 2393 + overwrite the canary, which gets detected and the attack is then 2394 + neutralized via a kernel panic. 2395 + 2396 + This feature requires gcc version 4.2 or above. 2397 + 2350 2398 config USE_OF 2351 2399 bool 2352 2400 select OF ··· 2391 2413 bool "Support for PCI controller" 2392 2414 depends on HW_HAS_PCI 2393 2415 select PCI_DOMAINS 2394 - select GENERIC_PCI_IOMAP 2395 2416 select NO_GENERIC_PCI_IOPORT_MAP 2396 2417 help 2397 2418 Find out whether you have a PCI motherboard. PCI is the name of a ··· 2455 2478 select CLKSRC_I8253 2456 2479 select CLKEVT_I8253 2457 2480 select MIPS_EXTERNAL_TIMER 2481 + 2482 + config ZONE_DMA 2483 + bool 2458 2484 2459 2485 config ZONE_DMA32 2460 2486 bool

+4

arch/mips/Makefile

··· 227 227 228 228 LDFLAGS += -m $(ld-emul) 229 229 230 + ifdef CONFIG_CC_STACKPROTECTOR 231 + KBUILD_CFLAGS += -fstack-protector 232 + endif 233 + 230 234 ifdef CONFIG_MIPS 231 235 CHECKFLAGS += $(shell $(CC) $(KBUILD_CFLAGS) -dM -E -x c /dev/null | \ 232 236 egrep -vw '__GNUC_(|MINOR_|PATCHLEVEL_)_' | \

+1 -1

arch/mips/ath79/mach-ap136.c

··· 132 132 ath79_register_pci(); 133 133 } 134 134 #else 135 - static inline void ap136_pci_init(void) {} 135 + static inline void ap136_pci_init(u8 *eeprom) {} 136 136 #endif /* CONFIG_PCI */ 137 137 138 138 static void __init ap136_setup(void)

+4 -5

arch/mips/bcm63xx/Kconfig

··· 1 1 menu "CPU support" 2 2 depends on BCM63XX 3 3 4 + config BCM63XX_CPU_3368 5 + bool "support 3368 CPU" 6 + select HW_HAS_PCI 7 + 4 8 config BCM63XX_CPU_6328 5 9 bool "support 6328 CPU" 6 10 select HW_HAS_PCI ··· 12 8 config BCM63XX_CPU_6338 13 9 bool "support 6338 CPU" 14 10 select HW_HAS_PCI 15 - select USB_ARCH_HAS_OHCI 16 - select USB_OHCI_BIG_ENDIAN_DESC 17 - select USB_OHCI_BIG_ENDIAN_MMIO 18 11 19 12 config BCM63XX_CPU_6345 20 13 bool "support 6345 CPU" 21 - select USB_OHCI_BIG_ENDIAN_DESC 22 - select USB_OHCI_BIG_ENDIAN_MMIO 23 14 24 15 config BCM63XX_CPU_6348 25 16 bool "support 6348 CPU"

+51 -2

arch/mips/bcm63xx/boards/board_bcm963xx.c

··· 28 28 #include <bcm63xx_dev_usb_usbd.h> 29 29 #include <board_bcm963xx.h> 30 30 31 + #include <uapi/linux/bcm933xx_hcs.h> 32 + 31 33 #define PFX "board_bcm963xx: " 32 34 35 + #define HCS_OFFSET_128K 0x20000 36 + 33 37 static struct board_info board; 38 + 39 + /* 40 + * known 3368 boards 41 + */ 42 + #ifdef CONFIG_BCM63XX_CPU_3368 43 + static struct board_info __initdata board_cvg834g = { 44 + .name = "CVG834G_E15R3921", 45 + .expected_cpu_id = 0x3368, 46 + 47 + .has_uart0 = 1, 48 + .has_uart1 = 1, 49 + 50 + .has_enet0 = 1, 51 + .has_pci = 1, 52 + 53 + .enet0 = { 54 + .has_phy = 1, 55 + .use_internal_phy = 1, 56 + }, 57 + 58 + .leds = { 59 + { 60 + .name = "CVG834G:green:power", 61 + .gpio = 37, 62 + .default_trigger= "default-on", 63 + }, 64 + }, 65 + 66 + .ephy_reset_gpio = 36, 67 + .ephy_reset_gpio_flags = GPIOF_INIT_HIGH, 68 + }; 69 + #endif 34 70 35 71 /* 36 72 * known 6328 boards ··· 675 639 * all boards 676 640 */ 677 641 static const struct board_info __initconst *bcm963xx_boards[] = { 642 + #ifdef CONFIG_BCM63XX_CPU_3368 643 + &board_cvg834g, 644 + #endif 678 645 #ifdef CONFIG_BCM63XX_CPU_6328 679 646 &board_96328avng, 680 647 #endif ··· 761 722 unsigned int i; 762 723 u8 *boot_addr, *cfe; 763 724 char cfe_version[32]; 764 - char *board_name; 725 + char *board_name = NULL; 765 726 u32 val; 727 + struct bcm_hcs *hcs; 766 728 767 729 /* read base address of boot chip select (0) 768 730 * 6328/6362 do not have MPI but boot from a fixed address ··· 787 747 788 748 bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET); 789 749 790 - board_name = bcm63xx_nvram_get_name(); 750 + if (BCMCPU_IS_3368()) { 751 + hcs = (struct bcm_hcs *)boot_addr; 752 + board_name = hcs->filename; 753 + } else { 754 + board_name = bcm63xx_nvram_get_name(); 755 + } 791 756 /* find board by name */ 792 757 for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { 793 758 if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) ··· 921 876 bcm63xx_led_data.leds = board.leds; 922 877 923 878 platform_device_register(&bcm63xx_gpio_leds); 879 + 880 + if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) 881 + gpio_request_one(board.ephy_reset_gpio, 882 + board.ephy_reset_gpio_flags, "ephy-reset"); 924 883 925 884 return 0; 926 885 }

+21 -9

arch/mips/bcm63xx/clk.c

··· 84 84 else 85 85 clk_disable_unlocked(&clk_enet_misc); 86 86 87 - if (BCMCPU_IS_6358()) { 87 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { 88 88 u32 mask; 89 89 90 90 if (clk->id == 0) ··· 110 110 */ 111 111 static void ephy_set(struct clk *clk, int enable) 112 112 { 113 - if (!BCMCPU_IS_6358()) 114 - return; 115 - bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); 113 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) 114 + bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); 116 115 } 117 116 118 117 ··· 154 155 */ 155 156 static void pcm_set(struct clk *clk, int enable) 156 157 { 157 - if (!BCMCPU_IS_6358()) 158 - return; 159 - bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); 158 + if (BCMCPU_IS_3368()) 159 + bcm_hwclock_set(CKCTL_3368_PCM_EN, enable); 160 + if (BCMCPU_IS_6358()) 161 + bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); 160 162 } 161 163 162 164 static struct clk clk_pcm = { ··· 211 211 mask = CKCTL_6338_SPI_EN; 212 212 else if (BCMCPU_IS_6348()) 213 213 mask = CKCTL_6348_SPI_EN; 214 - else if (BCMCPU_IS_6358()) 214 + else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) 215 215 mask = CKCTL_6358_SPI_EN; 216 216 else if (BCMCPU_IS_6362()) 217 217 mask = CKCTL_6362_SPI_EN; ··· 318 318 319 319 EXPORT_SYMBOL(clk_get_rate); 320 320 321 + int clk_set_rate(struct clk *clk, unsigned long rate) 322 + { 323 + return 0; 324 + } 325 + EXPORT_SYMBOL_GPL(clk_set_rate); 326 + 327 + long clk_round_rate(struct clk *clk, unsigned long rate) 328 + { 329 + return 0; 330 + } 331 + EXPORT_SYMBOL_GPL(clk_round_rate); 332 + 321 333 struct clk *clk_get(struct device *dev, const char *id) 322 334 { 323 335 if (!strcmp(id, "enet0")) ··· 350 338 return &clk_xtm; 351 339 if (!strcmp(id, "periph")) 352 340 return &clk_periph; 353 - if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 341 + if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) 354 342 return &clk_pcm; 355 343 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) 356 344 return &clk_ipsec;

+25 -3

arch/mips/bcm63xx/cpu.c

··· 29 29 static unsigned int bcm63xx_cpu_freq; 30 30 static unsigned int bcm63xx_memory_size; 31 31 32 + static const unsigned long bcm3368_regs_base[] = { 33 + __GEN_CPU_REGS_TABLE(3368) 34 + }; 35 + 36 + static const int bcm3368_irqs[] = { 37 + __GEN_CPU_IRQ_TABLE(3368) 38 + }; 39 + 32 40 static const unsigned long bcm6328_regs_base[] = { 33 41 __GEN_CPU_REGS_TABLE(6328) 34 42 }; ··· 124 116 static unsigned int detect_cpu_clock(void) 125 117 { 126 118 switch (bcm63xx_get_cpu_id()) { 119 + case BCM3368_CPU_ID: 120 + return 300000000; 121 + 127 122 case BCM6328_CPU_ID: 128 123 { 129 124 unsigned int tmp, mips_pll_fcvo; ··· 277 266 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 278 267 } 279 268 280 - if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 269 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 281 270 val = bcm_memc_readl(MEMC_CFG_REG); 282 271 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 283 272 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; ··· 313 302 chipid_reg = BCM_6345_PERF_BASE; 314 303 break; 315 304 case CPU_BMIPS4350: 316 - if ((read_c0_prid() & 0xf0) == 0x10) 305 + switch ((read_c0_prid() & 0xff)) { 306 + case 0x04: 307 + chipid_reg = BCM_3368_PERF_BASE; 308 + break; 309 + case 0x10: 317 310 chipid_reg = BCM_6345_PERF_BASE; 318 - else 311 + break; 312 + default: 319 313 chipid_reg = BCM_6368_PERF_BASE; 314 + break; 315 + } 320 316 break; 321 317 } 322 318 ··· 340 322 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 341 323 342 324 switch (bcm63xx_cpu_id) { 325 + case BCM3368_CPU_ID: 326 + bcm63xx_regs_base = bcm3368_regs_base; 327 + bcm63xx_irqs = bcm3368_irqs; 328 + break; 343 329 case BCM6328_CPU_ID: 344 330 bcm63xx_regs_base = bcm6328_regs_base; 345 331 bcm63xx_irqs = bcm6328_irqs;

+1

arch/mips/bcm63xx/dev-flash.c

··· 71 71 case BCM6348_CPU_ID: 72 72 /* no way to auto detect so assume parallel */ 73 73 return BCM63XX_FLASH_TYPE_PARALLEL; 74 + case BCM3368_CPU_ID: 74 75 case BCM6358_CPU_ID: 75 76 val = bcm_gpio_readl(GPIO_STRAPBUS_REG); 76 77 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)

+4 -2

arch/mips/bcm63xx/dev-spi.c

··· 37 37 { 38 38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) 39 39 bcm63xx_regs_spi = bcm6348_regs_spi; 40 - if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) 40 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || 41 + BCMCPU_IS_6362() || BCMCPU_IS_6368()) 41 42 bcm63xx_regs_spi = bcm6358_regs_spi; 42 43 } 43 44 #else ··· 88 87 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH; 89 88 } 90 89 91 - if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { 90 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || 91 + BCMCPU_IS_6368()) { 92 92 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; 93 93 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; 94 94 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;

+2 -1

arch/mips/bcm63xx/dev-uart.c

··· 54 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 55 55 return -ENODEV; 56 56 57 - if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368())) 57 + if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() && 58 + !BCMCPU_IS_6368())) 58 59 return -ENODEV; 59 60 60 61 if (id == 0) {

+23

arch/mips/bcm63xx/irq.c

··· 27 27 static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 28 28 29 29 #ifndef BCMCPU_RUNTIME_DETECT 30 + #ifdef CONFIG_BCM63XX_CPU_3368 31 + #define irq_stat_reg PERF_IRQSTAT_3368_REG 32 + #define irq_mask_reg PERF_IRQMASK_3368_REG 33 + #define irq_bits 32 34 + #define is_ext_irq_cascaded 0 35 + #define ext_irq_start 0 36 + #define ext_irq_end 0 37 + #define ext_irq_count 4 38 + #define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368 39 + #define ext_irq_cfg_reg2 0 40 + #endif 30 41 #ifdef CONFIG_BCM63XX_CPU_6328 31 42 #define irq_stat_reg PERF_IRQSTAT_6328_REG 32 43 #define irq_mask_reg PERF_IRQMASK_6328_REG ··· 151 140 irq_mask_addr = bcm63xx_regset_address(RSET_PERF); 152 141 153 142 switch (bcm63xx_get_cpu_id()) { 143 + case BCM3368_CPU_ID: 144 + irq_stat_addr += PERF_IRQSTAT_3368_REG; 145 + irq_mask_addr += PERF_IRQMASK_3368_REG; 146 + irq_bits = 32; 147 + ext_irq_count = 4; 148 + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; 149 + break; 154 150 case BCM6328_CPU_ID: 155 151 irq_stat_addr += PERF_IRQSTAT_6328_REG; 156 152 irq_mask_addr += PERF_IRQMASK_6328_REG; ··· 312 294 313 295 if (cause & CAUSEF_IP7) 314 296 do_IRQ(7); 297 + if (cause & CAUSEF_IP0) 298 + do_IRQ(0); 299 + if (cause & CAUSEF_IP1) 300 + do_IRQ(1); 315 301 if (cause & CAUSEF_IP2) 316 302 dispatch_internal(); 317 303 if (!is_ext_irq_cascaded) { ··· 497 475 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); 498 476 break; 499 477 478 + case BCM3368_CPU_ID: 500 479 case BCM6328_CPU_ID: 501 480 case BCM6338_CPU_ID: 502 481 case BCM6345_CPU_ID:

+10

arch/mips/bcm63xx/nvram.c

··· 42 42 { 43 43 unsigned int check_len; 44 44 u32 crc, expected_crc; 45 + u8 hcs_mac_addr[ETH_ALEN] = { 0x00, 0x10, 0x18, 0xff, 0xff, 0xff }; 45 46 46 47 /* extract nvram data */ 47 48 memcpy(&nvram, addr, sizeof(nvram)); ··· 63 62 if (crc != expected_crc) 64 63 pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n", 65 64 expected_crc, crc); 65 + 66 + /* Cable modems have a different NVRAM which is embedded in the eCos 67 + * firmware and not easily extractible, give at least a MAC address 68 + * pool. 69 + */ 70 + if (BCMCPU_IS_3368()) { 71 + memcpy(nvram.mac_addr_base, hcs_mac_addr, ETH_ALEN); 72 + nvram.mac_addr_count = 2; 73 + } 66 74 } 67 75 68 76 u8 *bcm63xx_nvram_get_name(void)

+48 -1

arch/mips/bcm63xx/prom.c

··· 8 8 9 9 #include <linux/init.h> 10 10 #include <linux/bootmem.h> 11 + #include <linux/smp.h> 11 12 #include <asm/bootinfo.h> 13 + #include <asm/bmips.h> 14 + #include <asm/smp-ops.h> 15 + #include <asm/mipsregs.h> 12 16 #include <bcm63xx_board.h> 13 17 #include <bcm63xx_cpu.h> 14 18 #include <bcm63xx_io.h> ··· 30 26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 31 27 32 28 /* disable all hardware blocks clock for now */ 33 - if (BCMCPU_IS_6328()) 29 + if (BCMCPU_IS_3368()) 30 + mask = CKCTL_3368_ALL_SAFE_EN; 31 + else if (BCMCPU_IS_6328()) 34 32 mask = CKCTL_6328_ALL_SAFE_EN; 35 33 else if (BCMCPU_IS_6338()) 36 34 mask = CKCTL_6338_ALL_SAFE_EN; ··· 58 52 59 53 /* do low level board init */ 60 54 board_prom_init(); 55 + 56 + if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { 57 + /* set up SMP */ 58 + register_smp_ops(&bmips_smp_ops); 59 + 60 + /* 61 + * BCM6328 might not have its second CPU enabled, while BCM6358 62 + * needs special handling for its shared TLB, so disable SMP 63 + * for now. 64 + */ 65 + if (BCMCPU_IS_6328()) { 66 + reg = bcm_readl(BCM_6328_OTP_BASE + 67 + OTP_USER_BITS_6328_REG(3)); 68 + 69 + if (reg & OTP_6328_REG3_TP1_DISABLED) 70 + bmips_smp_enabled = 0; 71 + } else if (BCMCPU_IS_6358()) { 72 + bmips_smp_enabled = 0; 73 + } 74 + 75 + if (!bmips_smp_enabled) 76 + return; 77 + 78 + /* 79 + * The bootloader has set up the CPU1 reset vector at 80 + * 0xa000_0200. 81 + * This conflicts with the special interrupt vector (IV). 82 + * The bootloader has also set up CPU1 to respond to the wrong 83 + * IPI interrupt. 84 + * Here we will start up CPU1 in the background and ask it to 85 + * reconfigure itself then go back to sleep. 86 + */ 87 + memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); 88 + __sync(); 89 + set_c0_cause(C_SW0); 90 + cpumask_set_cpu(1, &bmips_booted_mask); 91 + 92 + /* 93 + * FIXME: we really should have some sort of hazard barrier here 94 + */ 95 + } 61 96 } 62 97 63 98 void __init prom_free_prom_memory(void)

+28 -1

arch/mips/bcm63xx/reset.c

··· 30 30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ 31 31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, 32 32 33 + #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK 34 + #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK 35 + #define BCM3368_RESET_USBH 0 36 + #define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK 37 + #define BCM3368_RESET_DSL 0 38 + #define BCM3368_RESET_SAR 0 39 + #define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK 40 + #define BCM3368_RESET_ENETSW 0 41 + #define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK 42 + #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK 43 + #define BCM3368_RESET_PCIE 0 44 + #define BCM3368_RESET_PCIE_EXT 0 45 + 33 46 #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK 34 47 #define BCM6328_RESET_ENET 0 35 48 #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK ··· 130 117 /* 131 118 * core reset bits 132 119 */ 120 + static const u32 bcm3368_reset_bits[] = { 121 + __GEN_RESET_BITS_TABLE(3368) 122 + }; 123 + 133 124 static const u32 bcm6328_reset_bits[] = { 134 125 __GEN_RESET_BITS_TABLE(6328) 135 126 }; ··· 163 146 164 147 static int __init bcm63xx_reset_bits_init(void) 165 148 { 166 - if (BCMCPU_IS_6328()) { 149 + if (BCMCPU_IS_3368()) { 150 + reset_reg = PERF_SOFTRESET_6358_REG; 151 + bcm63xx_reset_bits = bcm3368_reset_bits; 152 + } else if (BCMCPU_IS_6328()) { 167 153 reset_reg = PERF_SOFTRESET_6328_REG; 168 154 bcm63xx_reset_bits = bcm6328_reset_bits; 169 155 } else if (BCMCPU_IS_6338()) { ··· 189 169 return 0; 190 170 } 191 171 #else 172 + 173 + #ifdef CONFIG_BCM63XX_CPU_3368 174 + static const u32 bcm63xx_reset_bits[] = { 175 + __GEN_RESET_BITS_TABLE(3368) 176 + }; 177 + #define reset_reg PERF_SOFTRESET_6358_REG 178 + #endif 192 179 193 180 #ifdef CONFIG_BCM63XX_CPU_6328 194 181 static const u32 bcm63xx_reset_bits[] = {

+3

arch/mips/bcm63xx/setup.c

··· 68 68 69 69 /* mask and clear all external irq */ 70 70 switch (bcm63xx_get_cpu_id()) { 71 + case BCM3368_CPU_ID: 72 + perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; 73 + break; 71 74 case BCM6328_CPU_ID: 72 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; 73 76 break;

+2

arch/mips/boot/compressed/Makefile

··· 18 18 # Disable Function Tracer 19 19 KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//") 20 20 21 + KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS)) 22 + 21 23 KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ 22 24 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" 23 25

+19 -3

arch/mips/boot/compressed/uart-16550.c

··· 23 23 #define PORT(offset) (UART0_BASE + (4 * offset)) 24 24 #endif 25 25 26 + #ifdef CONFIG_CPU_XLR 27 + #define UART0_BASE 0x1EF14000 28 + #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) 29 + #define IOTYPE unsigned int 30 + #endif 31 + 32 + #ifdef CONFIG_CPU_XLP 33 + #define UART0_BASE 0x18030100 34 + #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) 35 + #define IOTYPE unsigned int 36 + #endif 37 + 38 + #ifndef IOTYPE 39 + #define IOTYPE char 40 + #endif 41 + 26 42 #ifndef PORT 27 43 #error please define the serial port address for your own machine 28 44 #endif 29 45 30 46 static inline unsigned int serial_in(int offset) 31 47 { 32 - return *((char *)PORT(offset)); 48 + return *((volatile IOTYPE *)PORT(offset)) & 0xFF; 33 49 } 34 50 35 51 static inline void serial_out(int offset, int value) 36 52 { 37 - *((char *)PORT(offset)) = value; 53 + *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; 38 54 } 39 55 40 56 void putc(char c) 41 57 { 42 - int timeout = 1024; 58 + int timeout = 1000000; 43 59 44 60 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) 45 61 ;

+5 -12

arch/mips/cavium-octeon/Kconfig

··· 10 10 non-CN63XXP1 hardware, so it is recommended to select "n" 11 11 unless it is known the workarounds are needed. 12 12 13 + endif # CPU_CAVIUM_OCTEON 14 + 15 + if CAVIUM_OCTEON_SOC 16 + 13 17 config CAVIUM_OCTEON_2ND_KERNEL 14 18 bool "Build the kernel to be used as a 2nd kernel on the same chip" 15 19 default "n" ··· 22 18 address and use the 2nd uart for output. This allows a kernel built 23 19 with this option to be run at the same time as one built without this 24 20 option. 25 - 26 - config CAVIUM_OCTEON_HW_FIX_UNALIGNED 27 - bool "Enable hardware fixups of unaligned loads and stores" 28 - default "y" 29 - help 30 - Configure the Octeon hardware to automatically fix unaligned loads 31 - and stores. Normally unaligned accesses are fixed using a kernel 32 - exception handler. This option enables the hardware automatic fixups, 33 - which requires only an extra 3 cycles. Disable this option if you 34 - are running code that relies on address exceptions on unaligned 35 - accesses. 36 21 37 22 config CAVIUM_OCTEON_CVMSEG_SIZE 38 23 int "Number of L1 cache lines reserved for CVMSEG memory" ··· 96 103 To compile this driver as a module, choose M here. The module 97 104 will be called octeon-ilm 98 105 99 - endif # CPU_CAVIUM_OCTEON 106 + endif # CAVIUM_OCTEON_SOC

+3 -2

arch/mips/cavium-octeon/Makefile

··· 12 12 CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt 13 13 CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt 14 14 15 - obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 16 - obj-y += dma-octeon.o flash_setup.o 15 + obj-y := cpu.o setup.o octeon-platform.o octeon-irq.o csrc-octeon.o 16 + obj-y += dma-octeon.o 17 17 obj-y += octeon-memcpy.o 18 18 obj-y += executive/ 19 19 20 + obj-$(CONFIG_MTD) += flash_setup.o 20 21 obj-$(CONFIG_SMP) += smp.o 21 22 obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o 22 23

+4 -4

arch/mips/cavium-octeon/Platform

··· 1 1 # 2 2 # Cavium Octeon 3 3 # 4 - platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/ 5 - cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \ 4 + platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/ 5 + cflags-$(CONFIG_CAVIUM_OCTEON_SOC) += \ 6 6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon 7 7 ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 8 - load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000 8 + load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff84100000 9 9 else 10 - load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000 10 + load-$(CONFIG_CAVIUM_OCTEON_SOC) += 0xffffffff81100000 11 11 endif

+13

arch/mips/cavium-octeon/executive/cvmx-helper-board.c

··· 181 181 return ipd_port - 16 + 4; 182 182 else 183 183 return -1; 184 + case CVMX_BOARD_TYPE_UBNT_E100: 185 + if (ipd_port >= 0 && ipd_port <= 2) 186 + return 7 - ipd_port; 187 + else 188 + return -1; 184 189 } 185 190 186 191 /* Some unknown board. Somebody forgot to update this function... */ ··· 711 706 } 712 707 } 713 708 } 709 + } else if (cvmx_sysinfo_get()->board_type == 710 + CVMX_BOARD_TYPE_UBNT_E100) { 711 + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); 712 + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); 713 + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); 714 + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); 715 + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); 716 + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); 714 717 } 715 718 return 0; 716 719 }

+8 -1

arch/mips/cavium-octeon/octeon-platform.c

··· 490 490 491 491 if (alias_prop) { 492 492 uart = fdt_path_offset(initial_boot_params, alias_prop); 493 - if (uart_mask & (1 << i)) 493 + if (uart_mask & (1 << i)) { 494 + __be32 f; 495 + 496 + f = cpu_to_be32(octeon_get_io_clock_rate()); 497 + fdt_setprop_inplace(initial_boot_params, 498 + uart, "clock-frequency", 499 + &f, sizeof(f)); 494 500 continue; 501 + } 495 502 pr_debug("Deleting uart%d\n", i); 496 503 fdt_nop_node(initial_boot_params, uart); 497 504 fdt_nop_property(initial_boot_params, aliases,

-109

arch/mips/cavium-octeon/serial.c

··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2004-2007 Cavium Networks 7 - */ 8 - #include <linux/console.h> 9 - #include <linux/module.h> 10 - #include <linux/init.h> 11 - #include <linux/platform_device.h> 12 - #include <linux/serial.h> 13 - #include <linux/serial_8250.h> 14 - #include <linux/serial_reg.h> 15 - #include <linux/tty.h> 16 - #include <linux/irq.h> 17 - 18 - #include <asm/time.h> 19 - 20 - #include <asm/octeon/octeon.h> 21 - 22 - #define DEBUG_UART 1 23 - 24 - unsigned int octeon_serial_in(struct uart_port *up, int offset) 25 - { 26 - int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); 27 - if (offset == UART_IIR && (rv & 0xf) == 7) { 28 - /* Busy interrupt, read the USR (39) and try again. */ 29 - cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); 30 - rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); 31 - } 32 - return rv; 33 - } 34 - 35 - void octeon_serial_out(struct uart_port *up, int offset, int value) 36 - { 37 - /* 38 - * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits 39 - * working. 40 - */ 41 - if (offset == UART_LCR) 42 - value &= 0x9f; 43 - cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); 44 - } 45 - 46 - static int octeon_serial_probe(struct platform_device *pdev) 47 - { 48 - int irq, res; 49 - struct resource *res_mem; 50 - struct uart_8250_port up; 51 - 52 - /* All adaptors have an irq. */ 53 - irq = platform_get_irq(pdev, 0); 54 - if (irq < 0) 55 - return irq; 56 - 57 - memset(&up, 0, sizeof(up)); 58 - 59 - up.port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 60 - up.port.type = PORT_OCTEON; 61 - up.port.iotype = UPIO_MEM; 62 - up.port.regshift = 3; 63 - up.port.dev = &pdev->dev; 64 - 65 - if (octeon_is_simulation()) 66 - /* Make simulator output fast*/ 67 - up.port.uartclk = 115200 * 16; 68 - else 69 - up.port.uartclk = octeon_get_io_clock_rate(); 70 - 71 - up.port.serial_in = octeon_serial_in; 72 - up.port.serial_out = octeon_serial_out; 73 - up.port.irq = irq; 74 - 75 - res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 76 - if (res_mem == NULL) { 77 - dev_err(&pdev->dev, "found no memory resource\n"); 78 - return -ENXIO; 79 - } 80 - up.port.mapbase = res_mem->start; 81 - up.port.membase = ioremap(res_mem->start, resource_size(res_mem)); 82 - 83 - res = serial8250_register_8250_port(&up); 84 - 85 - return res >= 0 ? 0 : res; 86 - } 87 - 88 - static struct of_device_id octeon_serial_match[] = { 89 - { 90 - .compatible = "cavium,octeon-3860-uart", 91 - }, 92 - {}, 93 - }; 94 - MODULE_DEVICE_TABLE(of, octeon_serial_match); 95 - 96 - static struct platform_driver octeon_serial_driver = { 97 - .probe = octeon_serial_probe, 98 - .driver = { 99 - .owner = THIS_MODULE, 100 - .name = "octeon_serial", 101 - .of_match_table = octeon_serial_match, 102 - }, 103 - }; 104 - 105 - static int __init octeon_serial_init(void) 106 - { 107 - return platform_driver_register(&octeon_serial_driver); 108 - } 109 - late_initcall(octeon_serial_init);

+3 -29

arch/mips/cavium-octeon/setup.c

··· 7 7 * Copyright (C) 2008, 2009 Wind River Systems 8 8 * written by Ralf Baechle <ralf@linux-mips.org> 9 9 */ 10 + #include <linux/compiler.h> 10 11 #include <linux/init.h> 11 12 #include <linux/kernel.h> 12 13 #include <linux/console.h> ··· 40 39 #include <asm/octeon/octeon.h> 41 40 #include <asm/octeon/pci-octeon.h> 42 41 #include <asm/octeon/cvmx-mio-defs.h> 43 - 44 - #ifdef CONFIG_CAVIUM_DECODE_RSL 45 - extern void cvmx_interrupt_rsl_decode(void); 46 - extern int __cvmx_interrupt_ecc_report_single_bit_errors; 47 - extern void cvmx_interrupt_rsl_enable(void); 48 - #endif 49 42 50 43 extern struct plat_smp_ops octeon_smp_ops; 51 44 ··· 458 463 } 459 464 460 465 /** 461 - * Handle all the error condition interrupts that might occur. 462 - * 463 - */ 464 - #ifdef CONFIG_CAVIUM_DECODE_RSL 465 - static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) 466 - { 467 - cvmx_interrupt_rsl_decode(); 468 - return IRQ_HANDLED; 469 - } 470 - #endif 471 - 472 - /** 473 466 * Return a string representing the system type 474 467 * 475 468 * Returns ··· 695 712 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { 696 713 pr_info("Skipping L2 locking due to reduced L2 cache size\n"); 697 714 } else { 698 - uint32_t ebase = read_c0_ebase() & 0x3ffff000; 715 + uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000; 699 716 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB 700 717 /* TLB refill */ 701 718 cvmx_l2c_lock_mem_region(ebase, 0x100); ··· 979 996 cvmx_bootmem_unlock(); 980 997 /* Add the memory region for the kernel. */ 981 998 kernel_start = (unsigned long) _text; 982 - kernel_size = ALIGN(_end - _text, 0x100000); 999 + kernel_size = _end - _text; 983 1000 984 1001 /* Adjust for physical offset. */ 985 1002 kernel_start &= ~0xffffffff80000000ULL; ··· 1047 1064 panic("Core-14449 WAR not in place (%04x).\n" 1048 1065 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn); 1049 1066 } 1050 - #ifdef CONFIG_CAVIUM_DECODE_RSL 1051 - cvmx_interrupt_rsl_enable(); 1052 - 1053 - /* Add an interrupt handler for general failures. */ 1054 - if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, 1055 - "RML/RSL", octeon_rlm_interrupt)) { 1056 - panic("Unable to request_irq(OCTEON_IRQ_RML)"); 1057 - } 1058 - #endif 1059 1067 } 1060 1068 1061 1069 int octeon_prune_device_tree(void);

+2 -4

arch/mips/configs/cavium_octeon_defconfig

··· 1 - CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y 1 + CONFIG_CAVIUM_OCTEON_SOC=y 2 2 CONFIG_CAVIUM_CN63XXP1=y 3 3 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 4 - CONFIG_SPARSEMEM_MANUAL=y 5 4 CONFIG_TRANSPARENT_HUGEPAGE=y 6 5 CONFIG_SMP=y 7 6 CONFIG_NR_CPUS=32 8 7 CONFIG_HZ_100=y 9 8 CONFIG_PREEMPT=y 10 - CONFIG_EXPERIMENTAL=y 11 9 CONFIG_SYSVIPC=y 12 10 CONFIG_POSIX_MQUEUE=y 13 11 CONFIG_BSD_PROCESS_ACCT=y ··· 48 50 # CONFIG_FW_LOADER is not set 49 51 CONFIG_MTD=y 50 52 # CONFIG_MTD_OF_PARTS is not set 51 - CONFIG_MTD_CHAR=y 52 53 CONFIG_MTD_BLOCK=y 53 54 CONFIG_MTD_CFI=y 54 55 CONFIG_MTD_CFI_AMDSTD=y ··· 111 114 CONFIG_SERIAL_8250_CONSOLE=y 112 115 CONFIG_SERIAL_8250_NR_UARTS=2 113 116 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 117 + CONFIG_SERIAL_8250_DW=y 114 118 # CONFIG_HW_RANDOM is not set 115 119 CONFIG_I2C=y 116 120 CONFIG_I2C_OCTEON=y

-97

arch/mips/configs/wrppmc_defconfig

··· 1 - CONFIG_WR_PPMC=y 2 - CONFIG_HZ_1000=y 3 - CONFIG_EXPERIMENTAL=y 4 - # CONFIG_SWAP is not set 5 - CONFIG_SYSVIPC=y 6 - CONFIG_BSD_PROCESS_ACCT=y 7 - CONFIG_LOG_BUF_SHIFT=14 8 - CONFIG_BLK_DEV_INITRD=y 9 - # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 10 - CONFIG_EXPERT=y 11 - CONFIG_KALLSYMS_EXTRA_PASS=y 12 - # CONFIG_EPOLL is not set 13 - CONFIG_SLAB=y 14 - CONFIG_MODULES=y 15 - CONFIG_MODULE_UNLOAD=y 16 - CONFIG_MODVERSIONS=y 17 - CONFIG_MODULE_SRCVERSION_ALL=y 18 - CONFIG_PCI=y 19 - CONFIG_HOTPLUG_PCI=y 20 - CONFIG_BINFMT_MISC=y 21 - CONFIG_PM=y 22 - CONFIG_NET=y 23 - CONFIG_PACKET=y 24 - CONFIG_UNIX=y 25 - CONFIG_XFRM_MIGRATE=y 26 - CONFIG_INET=y 27 - CONFIG_IP_MULTICAST=y 28 - CONFIG_IP_PNP=y 29 - CONFIG_IP_PNP_DHCP=y 30 - CONFIG_IP_PNP_BOOTP=y 31 - CONFIG_IP_PNP_RARP=y 32 - CONFIG_IP_MROUTE=y 33 - CONFIG_ARPD=y 34 - CONFIG_INET_XFRM_MODE_TRANSPORT=m 35 - CONFIG_INET_XFRM_MODE_TUNNEL=m 36 - CONFIG_INET_XFRM_MODE_BEET=m 37 - CONFIG_TCP_MD5SIG=y 38 - # CONFIG_IPV6 is not set 39 - CONFIG_NETWORK_SECMARK=y 40 - CONFIG_FW_LOADER=m 41 - CONFIG_BLK_DEV_RAM=y 42 - CONFIG_SGI_IOC4=m 43 - CONFIG_NETDEVICES=y 44 - CONFIG_PHYLIB=y 45 - CONFIG_VITESSE_PHY=m 46 - CONFIG_SMSC_PHY=m 47 - CONFIG_NET_ETHERNET=y 48 - CONFIG_NET_PCI=y 49 - CONFIG_E100=y 50 - CONFIG_QLA3XXX=m 51 - CONFIG_CHELSIO_T3=m 52 - CONFIG_NETXEN_NIC=m 53 - # CONFIG_INPUT is not set 54 - # CONFIG_SERIO is not set 55 - # CONFIG_VT is not set 56 - CONFIG_SERIAL_8250=y 57 - CONFIG_SERIAL_8250_CONSOLE=y 58 - CONFIG_SERIAL_8250_NR_UARTS=1 59 - CONFIG_SERIAL_8250_RUNTIME_UARTS=1 60 - # CONFIG_HW_RANDOM is not set 61 - CONFIG_PROC_KCORE=y 62 - CONFIG_TMPFS=y 63 - CONFIG_TMPFS_POSIX_ACL=y 64 - CONFIG_NFS_FS=y 65 - CONFIG_NFS_V3=y 66 - CONFIG_ROOT_NFS=y 67 - CONFIG_DLM=m 68 - CONFIG_CMDLINE_BOOL=y 69 - CONFIG_CMDLINE="console=ttyS0,115200n8" 70 - CONFIG_CRYPTO_NULL=m 71 - CONFIG_CRYPTO_CBC=m 72 - CONFIG_CRYPTO_ECB=m 73 - CONFIG_CRYPTO_LRW=m 74 - CONFIG_CRYPTO_PCBC=m 75 - CONFIG_CRYPTO_XCBC=m 76 - CONFIG_CRYPTO_MD4=m 77 - CONFIG_CRYPTO_MICHAEL_MIC=m 78 - CONFIG_CRYPTO_SHA256=m 79 - CONFIG_CRYPTO_SHA512=m 80 - CONFIG_CRYPTO_TGR192=m 81 - CONFIG_CRYPTO_WP512=m 82 - CONFIG_CRYPTO_ANUBIS=m 83 - CONFIG_CRYPTO_ARC4=m 84 - CONFIG_CRYPTO_BLOWFISH=m 85 - CONFIG_CRYPTO_CAMELLIA=m 86 - CONFIG_CRYPTO_CAST5=m 87 - CONFIG_CRYPTO_CAST6=m 88 - CONFIG_CRYPTO_DES=m 89 - CONFIG_CRYPTO_FCRYPT=m 90 - CONFIG_CRYPTO_KHAZAD=m 91 - CONFIG_CRYPTO_SERPENT=m 92 - CONFIG_CRYPTO_TEA=m 93 - CONFIG_CRYPTO_TWOFISH=m 94 - CONFIG_CRYPTO_DEFLATE=m 95 - CONFIG_CRC_CCITT=y 96 - CONFIG_CRC16=y 97 - CONFIG_LIBCRC32C=y

-1

arch/mips/dec/Makefile

··· 5 5 obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \ 6 6 kn02-irq.o kn02xa-berr.o reset.o setup.o time.o 7 7 8 - obj-$(CONFIG_PROM_CONSOLE) += promcon.o 9 8 obj-$(CONFIG_TC) += tc.o 10 9 obj-$(CONFIG_CPU_HAS_WB) += wbflush.o

-54

arch/mips/dec/promcon.c

··· 1 - /* 2 - * Wrap-around code for a console using the 3 - * DECstation PROM io-routines. 4 - * 5 - * Copyright (c) 1998 Harald Koerfgen 6 - */ 7 - 8 - #include <linux/tty.h> 9 - #include <linux/ptrace.h> 10 - #include <linux/init.h> 11 - #include <linux/console.h> 12 - #include <linux/fs.h> 13 - 14 - #include <asm/dec/prom.h> 15 - 16 - static void prom_console_write(struct console *co, const char *s, 17 - unsigned count) 18 - { 19 - unsigned i; 20 - 21 - /* 22 - * Now, do each character 23 - */ 24 - for (i = 0; i < count; i++) { 25 - if (*s == 10) 26 - prom_printf("%c", 13); 27 - prom_printf("%c", *s++); 28 - } 29 - } 30 - 31 - static int __init prom_console_setup(struct console *co, char *options) 32 - { 33 - return 0; 34 - } 35 - 36 - static struct console sercons = { 37 - .name = "ttyS", 38 - .write = prom_console_write, 39 - .setup = prom_console_setup, 40 - .flags = CON_PRINTBUFFER, 41 - .index = -1, 42 - }; 43 - 44 - /* 45 - * Register console. 46 - */ 47 - 48 - static int __init prom_console_init(void) 49 - { 50 - register_console(&sercons); 51 - 52 - return 0; 53 - } 54 - console_initcall(prom_console_init);

+2 -2

arch/mips/fw/cfe/cfe_api.c

··· 406 406 return xiocb.xiocb_status; 407 407 } 408 408 409 - int cfe_write(int handle, unsigned char *buffer, int length) 409 + int cfe_write(int handle, const char *buffer, int length) 410 410 { 411 411 return cfe_writeblk(handle, 0, buffer, length); 412 412 } 413 413 414 - int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) 414 + int cfe_writeblk(int handle, s64 offset, const char *buffer, int length) 415 415 { 416 416 struct cfe_xiocb xiocb; 417 417

+29

arch/mips/include/asm/cop2.h

··· 11 11 12 12 #include <linux/notifier.h> 13 13 14 + #if defined(CONFIG_CPU_CAVIUM_OCTEON) 15 + 16 + extern void octeon_cop2_save(struct octeon_cop2_state *); 17 + extern void octeon_cop2_restore(struct octeon_cop2_state *); 18 + 19 + #define cop2_save(r) octeon_cop2_save(r) 20 + #define cop2_restore(r) octeon_cop2_restore(r) 21 + 22 + #define cop2_present 1 23 + #define cop2_lazy_restore 1 24 + 25 + #elif defined(CONFIG_CPU_XLP) 26 + 27 + extern void nlm_cop2_save(struct nlm_cop2_state *); 28 + extern void nlm_cop2_restore(struct nlm_cop2_state *); 29 + #define cop2_save(r) nlm_cop2_save(r) 30 + #define cop2_restore(r) nlm_cop2_restore(r) 31 + 32 + #define cop2_present 1 33 + #define cop2_lazy_restore 0 34 + 35 + #else 36 + 37 + #define cop2_present 0 38 + #define cop2_lazy_restore 0 39 + #define cop2_save(r) 40 + #define cop2_restore(r) 41 + #endif 42 + 14 43 enum cu2_ops { 15 44 CU2_EXCEPTION, 16 45 CU2_LWC2_OP,

+31 -18

arch/mips/include/asm/cpu-features.h

··· 24 24 #ifndef cpu_has_tlb 25 25 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 26 26 #endif 27 + 28 + /* 29 + * For the moment we don't consider R6000 and R8000 so we can assume that 30 + * anything that doesn't support R4000-style exceptions and interrupts is 31 + * R3000-like. Users should still treat these two macro definitions as 32 + * opaque. 33 + */ 34 + #ifndef cpu_has_3kex 35 + #define cpu_has_3kex (!cpu_has_4kex) 36 + #endif 27 37 #ifndef cpu_has_4kex 28 38 #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) 29 39 #endif ··· 97 87 #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) 98 88 #endif 99 89 #ifndef cpu_has_mdmx 100 - #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 90 + #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) 101 91 #endif 102 92 #ifndef cpu_has_mips3d 103 - #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 93 + #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) 104 94 #endif 105 95 #ifndef cpu_has_smartmips 106 - #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 96 + #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) 107 97 #endif 108 98 #ifndef cpu_has_rixi 109 99 #define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 110 100 #endif 111 101 #ifndef cpu_has_mmips 112 - #define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 102 + # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 103 + # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) 104 + # else 105 + # define cpu_has_mmips 0 106 + # endif 113 107 #endif 114 108 #ifndef cpu_has_vtag_icache 115 109 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) ··· 125 111 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 126 112 #endif 127 113 #ifndef cpu_has_pindexed_dcache 128 - #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 114 + #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 129 115 #endif 130 116 #ifndef cpu_has_local_ebase 131 117 #define cpu_has_local_ebase 1 ··· 150 136 #endif 151 137 #endif 152 138 153 - # define cpu_has_mips_1 (cpu_data[0].isa_level & MIPS_CPU_ISA_I) 154 139 #ifndef cpu_has_mips_2 155 140 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 156 141 #endif ··· 162 149 #ifndef cpu_has_mips_5 163 150 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 164 151 #endif 165 - # ifndef cpu_has_mips32r1 152 + #ifndef cpu_has_mips32r1 166 153 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 167 - # endif 168 - # ifndef cpu_has_mips32r2 154 + #endif 155 + #ifndef cpu_has_mips32r2 169 156 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 170 - # endif 171 - # ifndef cpu_has_mips64r1 157 + #endif 158 + #ifndef cpu_has_mips64r1 172 159 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 173 - # endif 174 - # ifndef cpu_has_mips64r2 160 + #endif 161 + #ifndef cpu_has_mips64r2 175 162 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 176 - # endif 163 + #endif 177 164 178 165 /* 179 166 * Shortcuts ... ··· 195 182 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 196 183 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 197 184 */ 198 - # ifndef cpu_has_clo_clz 199 - # define cpu_has_clo_clz cpu_has_mips_r 200 - # endif 185 + #ifndef cpu_has_clo_clz 186 + #define cpu_has_clo_clz cpu_has_mips_r 187 + #endif 201 188 202 189 #ifndef cpu_has_dsp 203 190 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) ··· 223 210 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 224 211 # endif 225 212 # ifndef cpu_has_64bit_zero_reg 226 - # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 213 + # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 227 214 # endif 228 215 # ifndef cpu_has_64bit_gp_regs 229 216 # define cpu_has_64bit_gp_regs 0

+10 -11

arch/mips/include/asm/cpu.h

··· 282 282 * ISA Level encodings 283 283 * 284 284 */ 285 - #define MIPS_CPU_ISA_I 0x00000001 286 - #define MIPS_CPU_ISA_II 0x00000002 287 - #define MIPS_CPU_ISA_III 0x00000004 288 - #define MIPS_CPU_ISA_IV 0x00000008 289 - #define MIPS_CPU_ISA_V 0x00000010 290 - #define MIPS_CPU_ISA_M32R1 0x00000020 291 - #define MIPS_CPU_ISA_M32R2 0x00000040 292 - #define MIPS_CPU_ISA_M64R1 0x00000080 293 - #define MIPS_CPU_ISA_M64R2 0x00000100 285 + #define MIPS_CPU_ISA_II 0x00000001 286 + #define MIPS_CPU_ISA_III 0x00000002 287 + #define MIPS_CPU_ISA_IV 0x00000004 288 + #define MIPS_CPU_ISA_V 0x00000008 289 + #define MIPS_CPU_ISA_M32R1 0x00000010 290 + #define MIPS_CPU_ISA_M32R2 0x00000020 291 + #define MIPS_CPU_ISA_M64R1 0x00000040 292 + #define MIPS_CPU_ISA_M64R2 0x00000080 294 293 295 - #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ 296 - MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) 294 + #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 295 + MIPS_CPU_ISA_M32R2) 297 296 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 298 297 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) 299 298

+2 -2

arch/mips/include/asm/fw/cfe/cfe_api.h

··· 115 115 int cfe_readblk(int handle, int64_t offset, unsigned char *buffer, 116 116 int length); 117 117 int cfe_setenv(char *name, char *val); 118 - int cfe_write(int handle, unsigned char *buffer, int length); 119 - int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer, 118 + int cfe_write(int handle, const char *buffer, int length); 119 + int cfe_writeblk(int handle, int64_t offset, const char *buffer, 120 120 int length); 121 121 122 122 #endif /* CFE_API_H */

+1 -1

arch/mips/include/asm/gic.h

··· 347 347 #define GIC_CPU_INT2 2 /* . */ 348 348 #define GIC_CPU_INT3 3 /* . */ 349 349 #define GIC_CPU_INT4 4 /* . */ 350 - #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ 350 + #define GIC_CPU_INT5 5 /* Core Interrupt 7 */ 351 351 352 352 /* Local GIC interrupts. */ 353 353 #define GIC_INT_TMR (GIC_CPU_INT5)

+10

arch/mips/include/asm/io.h

··· 170 170 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); 171 171 extern void __iounmap(const volatile void __iomem *addr); 172 172 173 + #ifndef CONFIG_PCI 174 + struct pci_dev; 175 + static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} 176 + #endif 177 + 173 178 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 174 179 unsigned long flags) 175 180 { ··· 453 448 #define readw_relaxed readw 454 449 #define readl_relaxed readl 455 450 #define readq_relaxed readq 451 + 452 + #define writeb_relaxed writeb 453 + #define writew_relaxed writew 454 + #define writel_relaxed writel 455 + #define writeq_relaxed writeq 456 456 457 457 #define readb_be(addr) \ 458 458 __raw_readb((__force unsigned *)(addr))

-32

arch/mips/include/asm/kspd.h

··· 1 - /* 2 - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 3 - * 4 - * This program is free software; you can distribute it and/or modify it 5 - * under the terms of the GNU General Public License (Version 2) as 6 - * published by the Free Software Foundation. 7 - * 8 - * This program is distributed in the hope it will be useful, but WITHOUT 9 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 - * for more details. 12 - * 13 - * You should have received a copy of the GNU General Public License along 14 - * with this program; if not, write to the Free Software Foundation, Inc., 15 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 - * 17 - */ 18 - 19 - #ifndef _ASM_KSPD_H 20 - #define _ASM_KSPD_H 21 - 22 - struct kspd_notifications { 23 - void (*kspd_sp_exit)(int sp_id); 24 - 25 - struct list_head list; 26 - }; 27 - 28 - static inline void kspd_notify(struct kspd_notifications *notify) 29 - { 30 - } 31 - 32 - #endif

+5 -2

arch/mips/include/asm/mach-ar7/spaces.h

··· 14 14 * This handles the memory map. 15 15 * We handle pages at KSEG0 for kernels with 32 bit address space. 16 16 */ 17 - #define PAGE_OFFSET 0x94000000UL 18 - #define PHYS_OFFSET 0x14000000UL 17 + #define PAGE_OFFSET _AC(0x94000000, UL) 18 + #define PHYS_OFFSET _AC(0x14000000, UL) 19 + 20 + #define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */ 21 + #define IO_BASE UNCAC_BASE 19 22 20 23 #include <asm/mach-generic/spaces.h> 21 24

+112

arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h

··· 9 9 * compile time if only one CPU support is enabled (idea stolen from 10 10 * arm mach-types) 11 11 */ 12 + #define BCM3368_CPU_ID 0x3368 12 13 #define BCM6328_CPU_ID 0x6328 13 14 #define BCM6338_CPU_ID 0x6338 14 15 #define BCM6345_CPU_ID 0x6345 ··· 22 21 u16 __bcm63xx_get_cpu_id(void); 23 22 u8 bcm63xx_get_cpu_rev(void); 24 23 unsigned int bcm63xx_get_cpu_freq(void); 24 + 25 + #ifdef CONFIG_BCM63XX_CPU_3368 26 + # ifdef bcm63xx_get_cpu_id 27 + # undef bcm63xx_get_cpu_id 28 + # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() 29 + # define BCMCPU_RUNTIME_DETECT 30 + # else 31 + # define bcm63xx_get_cpu_id() BCM3368_CPU_ID 32 + # endif 33 + # define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) 34 + #else 35 + # define BCMCPU_IS_3368() (0) 36 + #endif 25 37 26 38 #ifdef CONFIG_BCM63XX_CPU_6328 27 39 # ifdef bcm63xx_get_cpu_id ··· 208 194 #define RSET_RNG_SIZE 20 209 195 210 196 /* 197 + * 3368 register sets base address 198 + */ 199 + #define BCM_3368_DSL_LMEM_BASE (0xdeadbeef) 200 + #define BCM_3368_PERF_BASE (0xfff8c000) 201 + #define BCM_3368_TIMER_BASE (0xfff8c040) 202 + #define BCM_3368_WDT_BASE (0xfff8c080) 203 + #define BCM_3368_UART0_BASE (0xfff8c100) 204 + #define BCM_3368_UART1_BASE (0xfff8c120) 205 + #define BCM_3368_GPIO_BASE (0xfff8c080) 206 + #define BCM_3368_SPI_BASE (0xfff8c800) 207 + #define BCM_3368_HSSPI_BASE (0xdeadbeef) 208 + #define BCM_3368_UDC0_BASE (0xdeadbeef) 209 + #define BCM_3368_USBDMA_BASE (0xdeadbeef) 210 + #define BCM_3368_OHCI0_BASE (0xdeadbeef) 211 + #define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef) 212 + #define BCM_3368_USBH_PRIV_BASE (0xdeadbeef) 213 + #define BCM_3368_USBD_BASE (0xdeadbeef) 214 + #define BCM_3368_MPI_BASE (0xfff80000) 215 + #define BCM_3368_PCMCIA_BASE (0xfff80054) 216 + #define BCM_3368_PCIE_BASE (0xdeadbeef) 217 + #define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef) 218 + #define BCM_3368_DSL_BASE (0xdeadbeef) 219 + #define BCM_3368_UBUS_BASE (0xdeadbeef) 220 + #define BCM_3368_ENET0_BASE (0xfff98000) 221 + #define BCM_3368_ENET1_BASE (0xfff98800) 222 + #define BCM_3368_ENETDMA_BASE (0xfff99800) 223 + #define BCM_3368_ENETDMAC_BASE (0xfff99900) 224 + #define BCM_3368_ENETDMAS_BASE (0xfff99a00) 225 + #define BCM_3368_ENETSW_BASE (0xdeadbeef) 226 + #define BCM_3368_EHCI0_BASE (0xdeadbeef) 227 + #define BCM_3368_SDRAM_BASE (0xdeadbeef) 228 + #define BCM_3368_MEMC_BASE (0xfff84000) 229 + #define BCM_3368_DDR_BASE (0xdeadbeef) 230 + #define BCM_3368_M2M_BASE (0xdeadbeef) 231 + #define BCM_3368_ATM_BASE (0xdeadbeef) 232 + #define BCM_3368_XTM_BASE (0xdeadbeef) 233 + #define BCM_3368_XTMDMA_BASE (0xdeadbeef) 234 + #define BCM_3368_XTMDMAC_BASE (0xdeadbeef) 235 + #define BCM_3368_XTMDMAS_BASE (0xdeadbeef) 236 + #define BCM_3368_PCM_BASE (0xfff9c200) 237 + #define BCM_3368_PCMDMA_BASE (0xdeadbeef) 238 + #define BCM_3368_PCMDMAC_BASE (0xdeadbeef) 239 + #define BCM_3368_PCMDMAS_BASE (0xdeadbeef) 240 + #define BCM_3368_RNG_BASE (0xdeadbeef) 241 + #define BCM_3368_MISC_BASE (0xdeadbeef) 242 + 243 + /* 211 244 * 6328 register sets base address 212 245 */ 213 246 #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) ··· 299 238 #define BCM_6328_PCMDMAS_BASE (0xdeadbeef) 300 239 #define BCM_6328_RNG_BASE (0xdeadbeef) 301 240 #define BCM_6328_MISC_BASE (0xb0001800) 241 + #define BCM_6328_OTP_BASE (0xb0000600) 242 + 302 243 /* 303 244 * 6338 register sets base address 304 245 */ ··· 686 623 #ifdef BCMCPU_RUNTIME_DETECT 687 624 return bcm63xx_regs_base[set]; 688 625 #else 626 + #ifdef CONFIG_BCM63XX_CPU_3368 627 + __GEN_RSET(3368) 628 + #endif 689 629 #ifdef CONFIG_BCM63XX_CPU_6328 690 630 __GEN_RSET(6328) 691 631 #endif ··· 754 688 IRQ_XTM, 755 689 IRQ_XTM_DMA0, 756 690 }; 691 + 692 + /* 693 + * 3368 irqs 694 + */ 695 + #define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 696 + #define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 697 + #define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 698 + #define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 699 + #define BCM_3368_DSL_IRQ 0 700 + #define BCM_3368_UDC0_IRQ 0 701 + #define BCM_3368_OHCI0_IRQ 0 702 + #define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 703 + #define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 704 + #define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 705 + #define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 706 + #define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 707 + #define BCM_3368_HSSPI_IRQ 0 708 + #define BCM_3368_EHCI0_IRQ 0 709 + #define BCM_3368_USBD_IRQ 0 710 + #define BCM_3368_USBD_RXDMA0_IRQ 0 711 + #define BCM_3368_USBD_TXDMA0_IRQ 0 712 + #define BCM_3368_USBD_RXDMA1_IRQ 0 713 + #define BCM_3368_USBD_TXDMA1_IRQ 0 714 + #define BCM_3368_USBD_RXDMA2_IRQ 0 715 + #define BCM_3368_USBD_TXDMA2_IRQ 0 716 + #define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 717 + #define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 718 + #define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 719 + #define BCM_3368_PCMCIA_IRQ 0 720 + #define BCM_3368_ATM_IRQ 0 721 + #define BCM_3368_ENETSW_RXDMA0_IRQ 0 722 + #define BCM_3368_ENETSW_RXDMA1_IRQ 0 723 + #define BCM_3368_ENETSW_RXDMA2_IRQ 0 724 + #define BCM_3368_ENETSW_RXDMA3_IRQ 0 725 + #define BCM_3368_ENETSW_TXDMA0_IRQ 0 726 + #define BCM_3368_ENETSW_TXDMA1_IRQ 0 727 + #define BCM_3368_ENETSW_TXDMA2_IRQ 0 728 + #define BCM_3368_ENETSW_TXDMA3_IRQ 0 729 + #define BCM_3368_XTM_IRQ 0 730 + #define BCM_3368_XTM_DMA0_IRQ 0 731 + 732 + #define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) 733 + #define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) 734 + #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 735 + #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 736 + 757 737 758 738 /* 759 739 * 6328 irqs

+1

arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h

··· 11 11 switch (bcm63xx_get_cpu_id()) { 12 12 case BCM6328_CPU_ID: 13 13 return 32; 14 + case BCM3368_CPU_ID: 14 15 case BCM6358_CPU_ID: 15 16 return 40; 16 17 case BCM6338_CPU_ID:

+51 -1

arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

··· 15 15 /* Clock Control register */ 16 16 #define PERF_CKCTL_REG 0x4 17 17 18 + #define CKCTL_3368_MAC_EN (1 << 3) 19 + #define CKCTL_3368_TC_EN (1 << 5) 20 + #define CKCTL_3368_US_TOP_EN (1 << 6) 21 + #define CKCTL_3368_DS_TOP_EN (1 << 7) 22 + #define CKCTL_3368_APM_EN (1 << 8) 23 + #define CKCTL_3368_SPI_EN (1 << 9) 24 + #define CKCTL_3368_USBS_EN (1 << 10) 25 + #define CKCTL_3368_BMU_EN (1 << 11) 26 + #define CKCTL_3368_PCM_EN (1 << 12) 27 + #define CKCTL_3368_NTP_EN (1 << 13) 28 + #define CKCTL_3368_ACP_B_EN (1 << 14) 29 + #define CKCTL_3368_ACP_A_EN (1 << 15) 30 + #define CKCTL_3368_EMUSB_EN (1 << 17) 31 + #define CKCTL_3368_ENET0_EN (1 << 18) 32 + #define CKCTL_3368_ENET1_EN (1 << 19) 33 + #define CKCTL_3368_USBU_EN (1 << 20) 34 + #define CKCTL_3368_EPHY_EN (1 << 21) 35 + 36 + #define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \ 37 + CKCTL_3368_TC_EN | \ 38 + CKCTL_3368_US_TOP_EN | \ 39 + CKCTL_3368_DS_TOP_EN | \ 40 + CKCTL_3368_APM_EN | \ 41 + CKCTL_3368_SPI_EN | \ 42 + CKCTL_3368_USBS_EN | \ 43 + CKCTL_3368_BMU_EN | \ 44 + CKCTL_3368_PCM_EN | \ 45 + CKCTL_3368_NTP_EN | \ 46 + CKCTL_3368_ACP_B_EN | \ 47 + CKCTL_3368_ACP_A_EN | \ 48 + CKCTL_3368_EMUSB_EN | \ 49 + CKCTL_3368_USBU_EN) 50 + 18 51 #define CKCTL_6328_PHYMIPS_EN (1 << 0) 19 52 #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 20 53 #define CKCTL_6328_ADSL_AFE_EN (1 << 2) ··· 214 181 #define SYS_PLL_SOFT_RESET 0x1 215 182 216 183 /* Interrupt Mask register */ 184 + #define PERF_IRQMASK_3368_REG 0xc 217 185 #define PERF_IRQMASK_6328_REG 0x20 218 186 #define PERF_IRQMASK_6338_REG 0xc 219 187 #define PERF_IRQMASK_6345_REG 0xc ··· 224 190 #define PERF_IRQMASK_6368_REG 0x20 225 191 226 192 /* Interrupt Status register */ 193 + #define PERF_IRQSTAT_3368_REG 0x10 227 194 #define PERF_IRQSTAT_6328_REG 0x28 228 195 #define PERF_IRQSTAT_6338_REG 0x10 229 196 #define PERF_IRQSTAT_6345_REG 0x10 ··· 234 199 #define PERF_IRQSTAT_6368_REG 0x28 235 200 236 201 /* External Interrupt Configuration register */ 202 + #define PERF_EXTIRQ_CFG_REG_3368 0x14 237 203 #define PERF_EXTIRQ_CFG_REG_6328 0x18 238 204 #define PERF_EXTIRQ_CFG_REG_6338 0x14 239 205 #define PERF_EXTIRQ_CFG_REG_6345 0x14 ··· 271 235 #define PERF_SOFTRESET_6358_REG 0x34 272 236 #define PERF_SOFTRESET_6362_REG 0x10 273 237 #define PERF_SOFTRESET_6368_REG 0x10 238 + 239 + #define SOFTRESET_3368_SPI_MASK (1 << 0) 240 + #define SOFTRESET_3368_ENET_MASK (1 << 2) 241 + #define SOFTRESET_3368_MPI_MASK (1 << 3) 242 + #define SOFTRESET_3368_EPHY_MASK (1 << 6) 243 + #define SOFTRESET_3368_USBS_MASK (1 << 11) 244 + #define SOFTRESET_3368_PCM_MASK (1 << 13) 274 245 275 246 #define SOFTRESET_6328_SPI_MASK (1 << 0) 276 247 #define SOFTRESET_6328_EPHY_MASK (1 << 1) ··· 1413 1370 #define SPI_6348_RX_DATA 0x80 1414 1371 #define SPI_6348_RX_DATA_SIZE 0x3f 1415 1372 1416 - /* BCM 6358/6262/6368 SPI core */ 1373 + /* BCM 3368/6358/6262/6368 SPI core */ 1417 1374 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1418 1375 #define SPI_6358_MSG_CTL_WIDTH 16 1419 1376 #define SPI_6358_MSG_DATA 0x02 ··· 1553 1510 #define PCIE_RC_INT_D (1 << 3) 1554 1511 1555 1512 #define PCIE_DEVICE_OFFSET 0x8000 1513 + 1514 + /************************************************************************* 1515 + * _REG relative to RSET_OTP 1516 + *************************************************************************/ 1517 + 1518 + #define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4) 1519 + #define OTP_6328_REG3_TP1_DISABLED BIT(9) 1556 1520 1557 1521 #endif /* BCM63XX_REGS_H_ */

+6

arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h

··· 47 47 48 48 /* GPIO LEDs */ 49 49 struct gpio_led leds[5]; 50 + 51 + /* External PHY reset GPIO */ 52 + unsigned int ephy_reset_gpio; 53 + 54 + /* External PHY reset GPIO flags from gpio.h */ 55 + unsigned long ephy_reset_gpio_flags; 50 56 }; 51 57 52 58 #endif /* ! BOARD_BCM963XX_H_ */

+4

arch/mips/include/asm/mach-bcm63xx/ioremap.h

··· 11 11 static inline int is_bcm63xx_internal_registers(phys_t offset) 12 12 { 13 13 switch (bcm63xx_get_cpu_id()) { 14 + case BCM3368_CPU_ID: 15 + if (offset >= 0xfff80000) 16 + return 1; 17 + break; 14 18 case BCM6338_CPU_ID: 15 19 case BCM6345_CPU_ID: 16 20 case BCM6348_CPU_ID:

+7

arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h

··· 13 13 #ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 14 14 #define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H 15 15 16 + #include <linux/bug.h> 17 + 16 18 struct device; 17 19 18 20 extern void octeon_pci_dma_init(void); ··· 23 21 size_t size) 24 22 { 25 23 BUG(); 24 + return 0; 26 25 } 27 26 28 27 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 29 28 struct page *page) 30 29 { 31 30 BUG(); 31 + return 0; 32 32 } 33 33 34 34 static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 35 35 dma_addr_t dma_addr) 36 36 { 37 37 BUG(); 38 + return 0; 38 39 } 39 40 40 41 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, ··· 49 44 static inline int plat_dma_supported(struct device *dev, u64 mask) 50 45 { 51 46 BUG(); 47 + return 0; 52 48 } 53 49 54 50 static inline void plat_extra_sync_for_device(struct device *dev) ··· 66 60 dma_addr_t dma_addr) 67 61 { 68 62 BUG(); 63 + return 0; 69 64 } 70 65 71 66 dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);

+1 -6

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

··· 34 34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 35 35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register 36 36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register 37 - #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED 38 37 # Disable unaligned load/store support but leave HW fixup enabled 38 + # Needed for octeon specific memcpy 39 39 or v0, v0, 0x5001 40 40 xor v0, v0, 0x1001 41 - #else 42 - # Disable unaligned load/store and HW fixup support 43 - or v0, v0, 0x5001 44 - xor v0, v0, 0x5001 45 - #endif 46 41 # Read the processor ID register 47 42 mfc0 v1, CP0_PRID_REG 48 43 # Disable instruction prefetching (Octeon Pass1 errata)

+24

arch/mips/include/asm/mach-cavium-octeon/spaces.h

··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2012 Cavium, Inc. 7 + */ 8 + #ifndef _ASM_MACH_CAVIUM_OCTEON_SPACES_H 9 + #define _ASM_MACH_CAVIUM_OCTEON_SPACES_H 10 + 11 + #include <linux/const.h> 12 + 13 + #ifdef CONFIG_64BIT 14 + /* They are all the same and some OCTEON II cores cannot handle 0xa8.. */ 15 + #define CAC_BASE _AC(0x8000000000000000, UL) 16 + #define UNCAC_BASE _AC(0x8000000000000000, UL) 17 + #define IO_BASE _AC(0x8000000000000000, UL) 18 + 19 + 20 + #endif /* CONFIG_64BIT */ 21 + 22 + #include <asm/mach-generic/spaces.h> 23 + 24 + #endif /* _ASM_MACH_CAVIUM_OCTEON_SPACES_H */

+12

arch/mips/include/asm/mach-generic/dma-coherence.h

··· 66 66 #endif 67 67 } 68 68 69 + #ifdef CONFIG_SWIOTLB 70 + static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) 71 + { 72 + return paddr; 73 + } 74 + 75 + static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) 76 + { 77 + return daddr; 78 + } 79 + #endif 80 + 69 81 #endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */

+2 -2

arch/mips/include/asm/mach-generic/kernel-entry-init.h

··· 12 12 /* Intentionally empty macro, used in head.S. Override in 13 13 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 14 14 */ 15 - .macro kernel_entry_setup 16 - .endm 15 + .macro kernel_entry_setup 16 + .endm 17 17 18 18 /* 19 19 * Do SMP slave processor setup necessary before we can savely execute C code.

+47

arch/mips/include/asm/mach-ip27/kernel-entry-init.h

··· 24 24 .endm 25 25 26 26 /* 27 + * TLB bits 28 + */ 29 + #define PAGE_GLOBAL (1 << 6) 30 + #define PAGE_VALID (1 << 7) 31 + #define PAGE_DIRTY (1 << 8) 32 + #define CACHE_CACHABLE_COW (5 << 9) 33 + 34 + /* 35 + * inputs are the text nasid in t1, data nasid in t2. 36 + */ 37 + .macro MAPPED_KERNEL_SETUP_TLB 38 + #ifdef CONFIG_MAPPED_KERNEL 39 + /* 40 + * This needs to read the nasid - assume 0 for now. 41 + * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, 42 + * 0+DVG in tlblo_1. 43 + */ 44 + dli t0, 0xffffffffc0000000 45 + dmtc0 t0, CP0_ENTRYHI 46 + li t0, 0x1c000 # Offset of text into node memory 47 + dsll t1, NASID_SHFT # Shift text nasid into place 48 + dsll t2, NASID_SHFT # Same for data nasid 49 + or t1, t1, t0 # Physical load address of kernel text 50 + or t2, t2, t0 # Physical load address of kernel data 51 + dsrl t1, 12 # 4K pfn 52 + dsrl t2, 12 # 4K pfn 53 + dsll t1, 6 # Get pfn into place 54 + dsll t2, 6 # Get pfn into place 55 + li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6) 56 + or t0, t0, t1 57 + mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr 58 + li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6) 59 + or t0, t0, t2 60 + mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr 61 + li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M 62 + mtc0 t0, CP0_PAGEMASK 63 + li t0, 0 # KMAP_INX 64 + mtc0 t0, CP0_INDEX 65 + li t0, 1 66 + mtc0 t0, CP0_WIRED 67 + tlbwi 68 + #else 69 + mtc0 zero, CP0_WIRED 70 + #endif 71 + .endm 72 + 73 + /* 27 74 * Intentionally empty macro, used in head.S. Override in 28 75 * arch/mips/mach-xxx/kernel-entry-init.h when necessary. 29 76 */

+6 -3

arch/mips/include/asm/mach-ip28/spaces.h

··· 11 11 #ifndef _ASM_MACH_IP28_SPACES_H 12 12 #define _ASM_MACH_IP28_SPACES_H 13 13 14 - #define CAC_BASE 0xa800000000000000 14 + #define CAC_BASE _AC(0xa800000000000000, UL) 15 15 16 - #define HIGHMEM_START (~0UL) 16 + #define HIGHMEM_START (~0UL) 17 17 18 - #define PHYS_OFFSET _AC(0x20000000, UL) 18 + #define PHYS_OFFSET _AC(0x20000000, UL) 19 + 20 + #define UNCAC_BASE _AC(0xc0000000, UL) /* 0xa0000000 + PHYS_OFFSET */ 21 + #define IO_BASE UNCAC_BASE 19 22 20 23 #include <asm/mach-generic/spaces.h> 21 24

-46

arch/mips/include/asm/mach-pmcs-msp71xx/gpio.h

··· 1 - /* 2 - * include/asm-mips/pmc-sierra/msp71xx/gpio.h 3 - * 4 - * This program is free software; you can redistribute it and/or modify 5 - * it under the terms of the GNU General Public License version 2 as 6 - * published by the Free Software Foundation. 7 - * 8 - * @author Patrick Glass <patrickglass@gmail.com> 9 - */ 10 - 11 - #ifndef __PMC_MSP71XX_GPIO_H 12 - #define __PMC_MSP71XX_GPIO_H 13 - 14 - /* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */ 15 - #define ARCH_NR_GPIOS (28 + (3 * 8)) 16 - 17 - /* new generic GPIO API - see Documentation/gpio.txt */ 18 - #include <asm-generic/gpio.h> 19 - 20 - #define gpio_get_value __gpio_get_value 21 - #define gpio_set_value __gpio_set_value 22 - #define gpio_cansleep __gpio_cansleep 23 - 24 - /* Setup calls for the gpio and gpio extended */ 25 - extern void msp71xx_init_gpio(void); 26 - extern void msp71xx_init_gpio_extended(void); 27 - extern int msp71xx_set_output_drive(unsigned gpio, int value); 28 - 29 - /* Custom output drive functionss */ 30 - static inline int gpio_set_output_drive(unsigned gpio, int value) 31 - { 32 - return msp71xx_set_output_drive(gpio, value); 33 - } 34 - 35 - /* IRQ's are not supported for gpio lines */ 36 - static inline int gpio_to_irq(unsigned gpio) 37 - { 38 - return -EINVAL; 39 - } 40 - 41 - static inline int irq_to_gpio(unsigned irq) 42 - { 43 - return -EINVAL; 44 - } 45 - 46 - #endif /* __PMC_MSP71XX_GPIO_H */

-83

arch/mips/include/asm/mach-wrppmc/mach-gt64120.h

··· 1 - /* 2 - * This is a direct copy of the ev96100.h file, with a global 3 - * search and replace. The numbers are the same. 4 - * 5 - * The reason I'm duplicating this is so that the 64120/96100 6 - * defines won't be confusing in the source code. 7 - */ 8 - #ifndef __ASM_MIPS_GT64120_H 9 - #define __ASM_MIPS_GT64120_H 10 - 11 - /* 12 - * This is the CPU physical memory map of PPMC Board: 13 - * 14 - * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#) 15 - * 0x1C000000-0x1C000000 - LED (CS0) 16 - * 0x1C800000-0x1C800007 - UART 16550 port (CS1) 17 - * 0x1F000000-0x1F000000 - MailBox (CS3) 18 - * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS) 19 - */ 20 - 21 - #define WRPPMC_SDRAM_SCS0_BASE 0x00000000 22 - #define WRPPMC_SDRAM_SCS0_SIZE 0x04000000 23 - 24 - #define WRPPMC_UART16550_BASE 0x1C800000 25 - #define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */ 26 - 27 - #define WRPPMC_LED_BASE 0x1C000000 28 - #define WRPPMC_MBOX_BASE 0x1F000000 29 - 30 - #define WRPPMC_BOOTROM_BASE 0x1FC00000 31 - #define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */ 32 - 33 - #define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */ 34 - #define WRPPMC_UART16550_IRQ 6 35 - #define WRPPMC_PCI_INTA_IRQ 3 36 - 37 - /* 38 - * PCI Bus I/O and Memory resources allocation 39 - * 40 - * NOTE: We only have PCI_0 hose interface 41 - */ 42 - #define GT_PCI_MEM_BASE 0x13000000UL 43 - #define GT_PCI_MEM_SIZE 0x02000000UL 44 - #define GT_PCI_IO_BASE 0x11000000UL 45 - #define GT_PCI_IO_SIZE 0x02000000UL 46 - 47 - /* 48 - * PCI interrupts will come in on either the INTA or INTD interrupt lines, 49 - * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our 50 - * boards, they all either come in on IntD or they all come in on IntA, they 51 - * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the 52 - * "requested" interrupt numbers and go through the list whenever we get an 53 - * IntA/D. 54 - * 55 - * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and 56 - * INTD is 11. 57 - */ 58 - #define GT_TIMER 4 59 - #define GT_INTA 2 60 - #define GT_INTD 5 61 - 62 - #ifndef __ASSEMBLY__ 63 - 64 - /* 65 - * GT64120 internal register space base address 66 - */ 67 - extern unsigned long gt64120_base; 68 - 69 - #define GT64120_BASE (gt64120_base) 70 - 71 - /* define WRPPMC_EARLY_DEBUG to enable early output something to UART */ 72 - #undef WRPPMC_EARLY_DEBUG 73 - 74 - #ifdef WRPPMC_EARLY_DEBUG 75 - extern void wrppmc_led_on(int mask); 76 - extern void wrppmc_led_off(int mask); 77 - extern void wrppmc_early_printk(const char *fmt, ...); 78 - #else 79 - #define wrppmc_early_printk(fmt, ...) do {} while (0) 80 - #endif /* WRPPMC_EARLY_DEBUG */ 81 - 82 - #endif /* __ASSEMBLY__ */ 83 - #endif /* __ASM_MIPS_GT64120_H */

-24

arch/mips/include/asm/mach-wrppmc/war.h

··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 7 - */ 8 - #ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H 9 - #define __ASM_MIPS_MACH_WRPPMC_WAR_H 10 - 11 - #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 - #define R4600_V1_HIT_CACHEOP_WAR 0 13 - #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 - #define BCM1250_M3_WAR 0 16 - #define SIBYTE_1956_WAR 0 17 - #define MIPS4K_ICACHE_REFILL_WAR 0 18 - #define MIPS_CACHE_SYNC_WAR 0 19 - #define TX49XX_ICACHE_INDEX_INV_WAR 0 20 - #define ICACHE_REFILLS_WORKAROUND_WAR 1 21 - #define R10000_LLSC_WAR 0 22 - #define MIPS34K_MISSED_ITLB_WAR 0 23 - 24 - #endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */

-6

arch/mips/include/asm/mips-boards/generic.h

··· 24 24 #define ASCII_DISPLAY_POS_BASE 0x1f000418 25 25 26 26 /* 27 - * Reset register. 28 - */ 29 - #define SOFTRES_REG 0x1f000500 30 - #define GORESET 0x42 31 - 32 - /* 33 27 * Revision register. 34 28 */ 35 29 #define MIPS_REVISION_REG 0x1fc00010

+1 -1

arch/mips/include/asm/mipsregs.h

··· 596 596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 597 597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 598 598 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 599 - #define MIPS_CONF3_ISA_OE (_ULCAST_(3) << 16) 599 + #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 600 600 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 601 601 602 602 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)

+1 -5

arch/mips/include/asm/mmu_context.h

··· 28 28 29 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 30 do { \ 31 - void (*tlbmiss_handler_setup_pgd)(unsigned long); \ 32 - extern u32 tlbmiss_handler_setup_pgd_array[16]; \ 33 - \ 34 - tlbmiss_handler_setup_pgd = \ 35 - (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \ 31 + extern void tlbmiss_handler_setup_pgd(unsigned long); \ 36 32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 37 33 } while (0) 38 34

+18 -3

arch/mips/include/asm/netlogic/common.h

··· 39 39 * Common SMP definitions 40 40 */ 41 41 #define RESET_VEC_PHYS 0x1fc00000 42 + #define RESET_VEC_SIZE 8192 /* 8KB reset code and data */ 42 43 #define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) 44 + 45 + /* Offsets of parameters in the RESET_DATA_PHYS area */ 43 46 #define BOOT_THREAD_MODE 0 44 47 #define BOOT_NMI_LOCK 4 45 48 #define BOOT_NMI_HANDLER 8 49 + 50 + /* CPU ready flags for each CPU */ 51 + #define BOOT_CPU_READY 2048 46 52 47 53 #ifndef __ASSEMBLY__ 48 54 #include <linux/cpumask.h> ··· 65 59 void nlm_rmiboot_preboot(void); 66 60 void nlm_percpu_init(int hwcpuid); 67 61 62 + static inline void * 63 + nlm_get_boot_data(int offset) 64 + { 65 + return (void *)(CKSEG1ADDR(RESET_DATA_PHYS) + offset); 66 + } 67 + 68 68 static inline void 69 69 nlm_set_nmi_handler(void *handler) 70 70 { 71 - char *reset_data; 71 + void *nmih = nlm_get_boot_data(BOOT_NMI_HANDLER); 72 72 73 - reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); 74 - *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler; 73 + *(int64_t *)nmih = (long)handler; 75 74 } 76 75 77 76 /* 78 77 * Misc. 79 78 */ 79 + void nlm_init_boot_cpu(void); 80 80 unsigned int nlm_get_cpu_frequency(void); 81 81 void nlm_node_init(int node); 82 82 extern struct plat_smp_ops nlm_smp_ops; 83 83 extern char nlm_reset_entry[], nlm_reset_entry_end[]; 84 + 85 + /* SWIOTLB */ 86 + extern struct dma_map_ops nlm_swiotlb_dma_ops; 84 87 85 88 extern unsigned int nlm_threads_per_core; 86 89 extern cpumask_t nlm_cpumask;

+1 -1

arch/mips/include/asm/netlogic/xlp-hal/pic.h

··· 315 315 { 316 316 uint64_t ipi; 317 317 318 - ipi = (nmi << 31) | (irq << 20); 318 + ipi = ((uint64_t)nmi << 31) | (irq << 20); 319 319 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 320 320 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 321 321 }

+1

arch/mips/include/asm/netlogic/xlp-hal/xlp.h

··· 59 59 60 60 void xlp_mmu_init(void); 61 61 void nlm_hal_init(void); 62 + void *xlp_dt_init(void *fdtp); 62 63 63 64 #endif /* !__ASSEMBLY__ */ 64 65 #endif /* _ASM_NLM_XLP_H */

+8 -4

arch/mips/include/asm/netlogic/xlr/fmn.h

··· 175 175 #define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) 176 176 #define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) 177 177 178 + #define nlm_read_c2_status0() __read_32bit_c2_register($2, 0) 179 + #define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v) 180 + #define nlm_read_c2_status1() __read_32bit_c2_register($2, 1) 181 + #define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v) 178 182 #define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) 179 183 #define nlm_read_c2_config() __read_32bit_c2_register($3, 0) 180 184 #define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) ··· 241 237 /* 242 238 * Disable interrupts and enable COP2 access 243 239 */ 244 - static inline uint32_t nlm_cop2_enable(void) 240 + static inline uint32_t nlm_cop2_enable_irqsave(void) 245 241 { 246 242 uint32_t sr = read_c0_status(); 247 243 ··· 249 245 return sr; 250 246 } 251 247 252 - static inline void nlm_cop2_restore(uint32_t sr) 248 + static inline void nlm_cop2_disable_irqrestore(uint32_t sr) 253 249 { 254 250 write_c0_status(sr); 255 251 } ··· 300 296 */ 301 297 for (i = 0; i < 8; i++) { 302 298 nlm_msgsnd(dest); 303 - status = nlm_read_c2_status(0); 299 + status = nlm_read_c2_status0(); 304 300 if ((status & 0x2) == 1) 305 301 pr_info("Send pending fail!\n"); 306 302 if ((status & 0x4) == 0) ··· 320 316 321 317 /* wait for load pending to clear */ 322 318 do { 323 - status = nlm_read_c2_status(1); 319 + status = nlm_read_c2_status0(); 324 320 } while ((status & 0x08) != 0); 325 321 326 322 /* receive error bits */

+2

arch/mips/include/asm/octeon/cvmx-bootinfo.h

··· 227 227 * use any numbers in this range. 228 228 */ 229 229 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, 230 + CVMX_BOARD_TYPE_UBNT_E100 = 20002, 230 231 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, 231 232 232 233 /* The remaining range is reserved for future use. */ ··· 326 325 327 326 /* Customer private range */ 328 327 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) 328 + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) 329 329 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) 330 330 } 331 331 return "Unsupported Board";

+2 -4

arch/mips/include/asm/page.h

··· 205 205 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 206 206 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 207 207 208 - #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE + \ 209 - PHYS_OFFSET) 210 - #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET - \ 211 - PHYS_OFFSET) 208 + #define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE) 209 + #define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET) 212 210 213 211 #include <asm-generic/memory_model.h> 214 212 #include <asm-generic/getorder.h>

-1

arch/mips/include/asm/pci.h

··· 52 52 /* 53 53 * Used by boards to register their PCI busses before the actual scanning. 54 54 */ 55 - extern struct pci_controller * alloc_pci_controller(void); 56 55 extern void register_pci_controller(struct pci_controller *hose); 57 56 58 57 /*

+22 -13

arch/mips/include/asm/processor.h

··· 137 137 struct mips3264_watch_reg_state mips3264; 138 138 }; 139 139 140 - #ifdef CONFIG_CPU_CAVIUM_OCTEON 140 + #if defined(CONFIG_CPU_CAVIUM_OCTEON) 141 141 142 142 struct octeon_cop2_state { 143 143 /* DMFC2 rt, 0x0201 */ ··· 182 182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 183 183 unsigned long cop2_gfm_result[2]; 184 184 }; 185 - #define INIT_OCTEON_COP2 {0,} 185 + #define COP2_INIT \ 186 + .cp2 = {0,}, 186 187 187 188 struct octeon_cvmseg_state { 188 189 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 189 190 [cpu_dcache_line_size() / sizeof(unsigned long)]; 190 191 }; 191 192 193 + #elif defined(CONFIG_CPU_XLP) 194 + struct nlm_cop2_state { 195 + u64 rx[4]; 196 + u64 tx[4]; 197 + u32 tx_msg_status; 198 + u32 rx_msg_status; 199 + }; 200 + 201 + #define COP2_INIT \ 202 + .cp2 = {{0}, {0}, 0, 0}, 203 + #else 204 + #define COP2_INIT 192 205 #endif 193 206 194 207 typedef struct { ··· 244 231 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 245 232 unsigned long error_code; 246 233 #ifdef CONFIG_CPU_CAVIUM_OCTEON 247 - struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 248 - struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 234 + struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 235 + struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 236 + #endif 237 + #ifdef CONFIG_CPU_XLP 238 + struct nlm_cop2_state cp2; 249 239 #endif 250 240 struct mips_abi *abi; 251 241 }; ··· 260 244 #else 261 245 #define FPAFF_INIT 262 246 #endif /* CONFIG_MIPS_MT_FPAFF */ 263 - 264 - #ifdef CONFIG_CPU_CAVIUM_OCTEON 265 - #define OCTEON_INIT \ 266 - .cp2 = INIT_OCTEON_COP2, 267 - #else 268 - #define OCTEON_INIT 269 - #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 270 247 271 248 #define INIT_THREAD { \ 272 249 /* \ ··· 309 300 .cp0_baduaddr = 0, \ 310 301 .error_code = 0, \ 311 302 /* \ 312 - * Cavium Octeon specifics (null if not Octeon) \ 303 + * Platform specific cop2 registers(null if no COP2) \ 313 304 */ \ 314 - OCTEON_INIT \ 305 + COP2_INIT \ 315 306 } 316 307 317 308 struct task_struct;

+14 -15

arch/mips/include/asm/stackframe.h

··· 70 70 #ifndef CONFIG_CPU_HAS_SMARTMIPS 71 71 LONG_S v1, PT_LO(sp) 72 72 #endif 73 + #ifdef CONFIG_CPU_CAVIUM_OCTEON 74 + /* 75 + * The Octeon multiplier state is affected by general 76 + * multiply instructions. It must be saved before and 77 + * kernel code might corrupt it 78 + */ 79 + jal octeon_mult_save 80 + #endif 73 81 .endm 74 82 75 83 .macro SAVE_STATIC ··· 226 218 ori $28, sp, _THREAD_MASK 227 219 xori $28, _THREAD_MASK 228 220 #ifdef CONFIG_CPU_CAVIUM_OCTEON 229 - .set mips64 230 - pref 0, 0($28) /* Prefetch the current pointer */ 231 - pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ 232 - /* The Octeon multiplier state is affected by general multiply 233 - instructions. It must be saved before and kernel code might 234 - corrupt it */ 235 - jal octeon_mult_save 236 - LONG_L v1, 0($28) /* Load the current pointer */ 237 - /* Restore $31(ra) that was changed by the jal */ 238 - LONG_L ra, PT_R31(sp) 239 - pref 0, 0(v1) /* Prefetch the current thread */ 221 + .set mips64 222 + pref 0, 0($28) /* Prefetch the current pointer */ 240 223 #endif 241 224 .set pop 242 225 .endm ··· 247 248 .endm 248 249 249 250 .macro RESTORE_TEMP 251 + #ifdef CONFIG_CPU_CAVIUM_OCTEON 252 + /* Restore the Octeon multiplier state */ 253 + jal octeon_mult_restore 254 + #endif 250 255 #ifdef CONFIG_CPU_HAS_SMARTMIPS 251 256 LONG_L $24, PT_ACX(sp) 252 257 mtlhx $24 ··· 363 360 DVPE 5 # dvpe a1 364 361 jal mips_ihb 365 362 #endif /* CONFIG_MIPS_MT_SMTC */ 366 - #ifdef CONFIG_CPU_CAVIUM_OCTEON 367 - /* Restore the Octeon multiplier state */ 368 - jal octeon_mult_restore 369 - #endif 370 363 mfc0 a0, CP0_STATUS 371 364 ori a0, STATMASK 372 365 xori a0, STATMASK

+40

arch/mips/include/asm/stackprotector.h

··· 1 + /* 2 + * GCC stack protector support. 3 + * 4 + * (This is directly adopted from the ARM implementation) 5 + * 6 + * Stack protector works by putting predefined pattern at the start of 7 + * the stack frame and verifying that it hasn't been overwritten when 8 + * returning from the function. The pattern is called stack canary 9 + * and gcc expects it to be defined by a global variable called 10 + * "__stack_chk_guard" on MIPS. This unfortunately means that on SMP 11 + * we cannot have a different canary value per task. 12 + */ 13 + 14 + #ifndef _ASM_STACKPROTECTOR_H 15 + #define _ASM_STACKPROTECTOR_H 1 16 + 17 + #include <linux/random.h> 18 + #include <linux/version.h> 19 + 20 + extern unsigned long __stack_chk_guard; 21 + 22 + /* 23 + * Initialize the stackprotector canary value. 24 + * 25 + * NOTE: this must only be called from functions that never return, 26 + * and it must always be inlined. 27 + */ 28 + static __always_inline void boot_init_stack_canary(void) 29 + { 30 + unsigned long canary; 31 + 32 + /* Try to get a semi random initial value. */ 33 + get_random_bytes(&canary, sizeof(canary)); 34 + canary ^= LINUX_VERSION_CODE; 35 + 36 + current->stack_canary = canary; 37 + __stack_chk_guard = current->stack_canary; 38 + } 39 + 40 + #endif /* _ASM_STACKPROTECTOR_H */

+18 -1

arch/mips/include/asm/switch_to.h

··· 15 15 #include <asm/cpu-features.h> 16 16 #include <asm/watch.h> 17 17 #include <asm/dsp.h> 18 + #include <asm/cop2.h> 18 19 19 20 struct task_struct; 20 21 ··· 67 66 68 67 #define switch_to(prev, next, last) \ 69 68 do { \ 70 - u32 __usedfpu; \ 69 + u32 __usedfpu, __c0_stat; \ 71 70 __mips_mt_fpaff_switch_to(prev); \ 72 71 if (cpu_has_dsp) \ 73 72 __save_dsp(prev); \ 73 + if (cop2_present && (KSTK_STATUS(prev) & ST0_CU2)) { \ 74 + if (cop2_lazy_restore) \ 75 + KSTK_STATUS(prev) &= ~ST0_CU2; \ 76 + __c0_stat = read_c0_status(); \ 77 + write_c0_status(__c0_stat | ST0_CU2); \ 78 + cop2_save(&prev->thread.cp2); \ 79 + write_c0_status(__c0_stat & ~ST0_CU2); \ 80 + } \ 74 81 __clear_software_ll_bit(); \ 75 82 __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ 76 83 (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ ··· 86 77 87 78 #define finish_arch_switch(prev) \ 88 79 do { \ 80 + u32 __c0_stat; \ 81 + if (cop2_present && !cop2_lazy_restore && \ 82 + (KSTK_STATUS(current) & ST0_CU2)) { \ 83 + __c0_stat = read_c0_status(); \ 84 + write_c0_status(__c0_stat | ST0_CU2); \ 85 + cop2_restore(&current->thread.cp2); \ 86 + write_c0_status(__c0_stat & ~ST0_CU2); \ 87 + } \ 89 88 if (cpu_has_dsp) \ 90 89 __restore_dsp(current); \ 91 90 if (cpu_has_userlocal) \

+9 -2

arch/mips/include/asm/thread_info.h

··· 109 109 #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ 110 110 #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ 111 111 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ 112 + #define TIF_NOHZ 19 /* in adaptive nohz mode */ 112 113 #define TIF_FIXADE 20 /* Fix address errors in software */ 113 114 #define TIF_LOGADE 21 /* Log address errors to syslog */ 114 115 #define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ ··· 125 124 #define _TIF_SECCOMP (1<<TIF_SECCOMP) 126 125 #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) 127 126 #define _TIF_USEDFPU (1<<TIF_USEDFPU) 127 + #define _TIF_NOHZ (1<<TIF_NOHZ) 128 128 #define _TIF_FIXADE (1<<TIF_FIXADE) 129 129 #define _TIF_LOGADE (1<<TIF_LOGADE) 130 130 #define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) ··· 133 131 #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 134 132 #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 135 133 134 + #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 135 + _TIF_SYSCALL_AUDIT) 136 + 136 137 /* work to do in syscall_trace_leave() */ 137 - #define _TIF_WORK_SYSCALL_EXIT (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT) 138 + #define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ 139 + _TIF_SYSCALL_AUDIT) 138 140 139 141 /* work to do on interrupt/exception return */ 140 142 #define _TIF_WORK_MASK \ 141 143 (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME) 142 144 /* work to do on any return to u-space */ 143 - #define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_WORK_SYSCALL_EXIT) 145 + #define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ 146 + _TIF_WORK_SYSCALL_EXIT) 144 147 145 148 #endif /* __KERNEL__ */ 146 149

+9

arch/mips/include/asm/xtalk/xtalk.h

··· 47 47 #define XIO_PORT(x) ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT)) 48 48 #define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS)) 49 49 50 + #ifdef CONFIG_PCI 51 + extern int bridge_probe(nasid_t nasid, int widget, int masterwid); 52 + #else 53 + static inline int bridge_probe(nasid_t nasid, int widget, int masterwid) 54 + { 55 + return 0; 56 + } 57 + #endif 58 + 50 59 #endif /* !__ASSEMBLY__ */ 51 60 52 61 #endif /* _ASM_XTALK_XTALK_H */

+9 -7

arch/mips/include/uapi/asm/fcntl.h

··· 5 5 * 6 6 * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle 7 7 */ 8 - #ifndef _ASM_FCNTL_H 9 - #define _ASM_FCNTL_H 8 + #ifndef _UAPI_ASM_FCNTL_H 9 + #define _UAPI_ASM_FCNTL_H 10 10 11 + #include <asm/sgidefs.h> 11 12 12 13 #define O_APPEND 0x0008 13 14 #define O_DSYNC 0x0010 /* used to be O_SYNC, see below */ ··· 56 55 * contain all the same fields as struct flock. 57 56 */ 58 57 59 - #ifdef CONFIG_32BIT 58 + #if _MIPS_SIM != _MIPS_SIM_ABI64 59 + 60 60 #include <linux/types.h> 61 61 62 62 struct flock { 63 63 short l_type; 64 64 short l_whence; 65 - off_t l_start; 66 - off_t l_len; 65 + __kernel_off_t l_start; 66 + __kernel_off_t l_len; 67 67 long l_sysid; 68 68 __kernel_pid_t l_pid; 69 69 long pad[4]; ··· 72 70 73 71 #define HAVE_ARCH_STRUCT_FLOCK 74 72 75 - #endif /* CONFIG_32BIT */ 73 + #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 76 74 77 75 #include <asm-generic/fcntl.h> 78 76 79 - #endif /* _ASM_FCNTL_H */ 77 + #endif /* _UAPI_ASM_FCNTL_H */

+5 -4

arch/mips/include/uapi/asm/inst.h

··· 409 409 enum mm_16c_minor_op { 410 410 mm_lwm16_op = 0x04, 411 411 mm_swm16_op = 0x05, 412 - mm_jr16_op = 0x18, 413 - mm_jrc_op = 0x1a, 414 - mm_jalr16_op = 0x1c, 415 - mm_jalrs16_op = 0x1e, 412 + mm_jr16_op = 0x0c, 413 + mm_jrc_op = 0x0d, 414 + mm_jalr16_op = 0x0e, 415 + mm_jalrs16_op = 0x0f, 416 + mm_jraddiusp_op = 0x18, 416 417 }; 417 418 418 419 /*

+6 -6

arch/mips/include/uapi/asm/msgbuf.h

··· 14 14 15 15 struct msqid64_ds { 16 16 struct ipc64_perm msg_perm; 17 - #if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 17 + #if !defined(__mips64) && defined(__MIPSEB__) 18 18 unsigned long __unused1; 19 19 #endif 20 20 __kernel_time_t msg_stime; /* last msgsnd time */ 21 - #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 21 + #if !defined(__mips64) && defined(__MIPSEL__) 22 22 unsigned long __unused1; 23 23 #endif 24 - #if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 24 + #if !defined(__mips64) && defined(__MIPSEB__) 25 25 unsigned long __unused2; 26 26 #endif 27 27 __kernel_time_t msg_rtime; /* last msgrcv time */ 28 - #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 28 + #if !defined(__mips64) && defined(__MIPSEL__) 29 29 unsigned long __unused2; 30 30 #endif 31 - #if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN) 31 + #if !defined(__mips64) && defined(__MIPSEB__) 32 32 unsigned long __unused3; 33 33 #endif 34 34 __kernel_time_t msg_ctime; /* last change time */ 35 - #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN) 35 + #if !defined(__mips64) && defined(__MIPSEL__) 36 36 unsigned long __unused3; 37 37 #endif 38 38 unsigned long msg_cbytes; /* current number of bytes on queue */

+1 -1

arch/mips/include/uapi/asm/resource.h

··· 26 26 * but we keep the old value on MIPS32, 27 27 * for compatibility: 28 28 */ 29 - #ifdef CONFIG_32BIT 29 + #ifndef __mips64 30 30 # define RLIM_INFINITY 0x7fffffffUL 31 31 #endif 32 32

+2 -2

arch/mips/include/uapi/asm/siginfo.h

··· 25 25 /* 26 26 * Careful to keep union _sifields from shifting ... 27 27 */ 28 - #ifdef CONFIG_32BIT 28 + #if __SIZEOF_LONG__ == 4 29 29 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int)) 30 30 #endif 31 - #ifdef CONFIG_64BIT 31 + #if __SIZEOF_LONG__ == 8 32 32 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) 33 33 #endif 34 34

+6 -6

arch/mips/include/uapi/asm/swab.h

··· 13 13 14 14 #define __SWAB_64_THRU_32__ 15 15 16 - #ifdef CONFIG_CPU_MIPSR2 16 + #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 17 17 18 18 static inline __attribute_const__ __u16 __arch_swab16(__u16 x) 19 19 { ··· 39 39 #define __arch_swab32 __arch_swab32 40 40 41 41 /* 42 - * Having already checked for CONFIG_CPU_MIPSR2, enable the 43 - * optimized version for 64-bit kernel on r2 CPUs. 42 + * Having already checked for MIPS R2, enable the optimized version for 43 + * 64-bit kernel on r2 CPUs. 44 44 */ 45 - #ifdef CONFIG_64BIT 45 + #ifdef __mips64 46 46 static inline __attribute_const__ __u64 __arch_swab64(__u64 x) 47 47 { 48 48 __asm__( ··· 54 54 return x; 55 55 } 56 56 #define __arch_swab64 __arch_swab64 57 - #endif /* CONFIG_64BIT */ 58 - #endif /* CONFIG_CPU_MIPSR2 */ 57 + #endif /* __mips64 */ 58 + #endif /* MIPS R2 or newer */ 59 59 #endif /* _ASM_SWAB_H */

+3

arch/mips/kernel/asm-offsets.c

··· 82 82 OFFSET(TASK_FLAGS, task_struct, flags); 83 83 OFFSET(TASK_MM, task_struct, mm); 84 84 OFFSET(TASK_PID, task_struct, pid); 85 + #if defined(CONFIG_CC_STACKPROTECTOR) 86 + OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); 87 + #endif 85 88 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); 86 89 BLANK(); 87 90 }

-1

arch/mips/kernel/branch.c

··· 467 467 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 468 468 force_sig(SIGBUS, current); 469 469 return -EFAULT; 470 - 471 470 }

+5

arch/mips/kernel/cpu-bugs64.c

··· 6 6 * as published by the Free Software Foundation; either version 7 7 * 2 of the License, or (at your option) any later version. 8 8 */ 9 + #include <linux/context_tracking.h> 9 10 #include <linux/init.h> 10 11 #include <linux/kernel.h> 11 12 #include <linux/ptrace.h> ··· 172 171 173 172 asmlinkage void __init do_daddi_ov(struct pt_regs *regs) 174 173 { 174 + enum ctx_state prev_state; 175 + 176 + prev_state = exception_enter(); 175 177 daddi_ov = 1; 176 178 regs->cp0_epc += 4; 179 + exception_exit(prev_state); 177 180 } 178 181 179 182 static inline void check_daddi(void)

+2 -10

arch/mips/kernel/cpu-probe.c

··· 146 146 case MIPS_CPU_ISA_IV: 147 147 c->isa_level |= MIPS_CPU_ISA_IV; 148 148 case MIPS_CPU_ISA_III: 149 - c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | 150 - MIPS_CPU_ISA_III; 149 + c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 151 150 break; 152 151 153 152 case MIPS_CPU_ISA_M32R2: ··· 155 156 c->isa_level |= MIPS_CPU_ISA_M32R1; 156 157 case MIPS_CPU_ISA_II: 157 158 c->isa_level |= MIPS_CPU_ISA_II; 158 - case MIPS_CPU_ISA_I: 159 - c->isa_level |= MIPS_CPU_ISA_I; 160 159 break; 161 160 } 162 161 } ··· 269 272 c->options |= MIPS_CPU_ULRI; 270 273 if (config3 & MIPS_CONF3_ISA) 271 274 c->options |= MIPS_CPU_MICROMIPS; 272 - #ifdef CONFIG_CPU_MICROMIPS 273 - write_c0_config3(read_c0_config3() | MIPS_CONF3_ISA_OE); 274 - #endif 275 275 if (config3 & MIPS_CONF3_VZ) 276 276 c->ases |= MIPS_ASE_VZ; 277 277 ··· 326 332 case PRID_IMP_R2000: 327 333 c->cputype = CPU_R2000; 328 334 __cpu_name[cpu] = "R2000"; 329 - set_isa(c, MIPS_CPU_ISA_I); 330 335 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 331 336 MIPS_CPU_NOFPUEX; 332 337 if (__cpu_has_fpu()) ··· 345 352 c->cputype = CPU_R3000; 346 353 __cpu_name[cpu] = "R3000"; 347 354 } 348 - set_isa(c, MIPS_CPU_ISA_I); 349 355 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 350 356 MIPS_CPU_NOFPUEX; 351 357 if (__cpu_has_fpu()) ··· 447 455 break; 448 456 #endif 449 457 case PRID_IMP_TX39: 450 - set_isa(c, MIPS_CPU_ISA_I); 451 458 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 452 459 453 460 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { ··· 950 959 set_isa(c, MIPS_CPU_ISA_M64R1); 951 960 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 952 961 } 962 + c->kscratch_mask = 0xf; 953 963 } 954 964 955 965 #ifdef CONFIG_64BIT

-39

arch/mips/kernel/head.S

··· 28 28 #include <kernel-entry-init.h> 29 29 30 30 /* 31 - * inputs are the text nasid in t1, data nasid in t2. 32 - */ 33 - .macro MAPPED_KERNEL_SETUP_TLB 34 - #ifdef CONFIG_MAPPED_KERNEL 35 - /* 36 - * This needs to read the nasid - assume 0 for now. 37 - * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, 38 - * 0+DVG in tlblo_1. 39 - */ 40 - dli t0, 0xffffffffc0000000 41 - dmtc0 t0, CP0_ENTRYHI 42 - li t0, 0x1c000 # Offset of text into node memory 43 - dsll t1, NASID_SHFT # Shift text nasid into place 44 - dsll t2, NASID_SHFT # Same for data nasid 45 - or t1, t1, t0 # Physical load address of kernel text 46 - or t2, t2, t0 # Physical load address of kernel data 47 - dsrl t1, 12 # 4K pfn 48 - dsrl t2, 12 # 4K pfn 49 - dsll t1, 6 # Get pfn into place 50 - dsll t2, 6 # Get pfn into place 51 - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) 52 - or t0, t0, t1 53 - mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr 54 - li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) 55 - or t0, t0, t2 56 - mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr 57 - li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M 58 - mtc0 t0, CP0_PAGEMASK 59 - li t0, 0 # KMAP_INX 60 - mtc0 t0, CP0_INDEX 61 - li t0, 1 62 - mtc0 t0, CP0_WIRED 63 - tlbwi 64 - #else 65 - mtc0 zero, CP0_WIRED 66 - #endif 67 - .endm 68 - 69 - /* 70 31 * For the moment disable interrupts, mark the kernel mode and 71 32 * set ST0_KX so that the CPU does not spit fire when using 72 33 * 64-bit addresses. A full initialization of the CPU's status

+7 -8

arch/mips/kernel/irq-gic.c

··· 219 219 220 220 /* Assumption : cpumask refers to a single CPU */ 221 221 spin_lock_irqsave(&gic_lock, flags); 222 - for (;;) { 223 - /* Re-route this IRQ */ 224 - GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); 225 222 226 - /* Update the pcpu_masks */ 227 - for (i = 0; i < NR_CPUS; i++) 228 - clear_bit(irq, pcpu_masks[i].pcpu_mask); 229 - set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); 223 + /* Re-route this IRQ */ 224 + GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); 230 225 231 - } 226 + /* Update the pcpu_masks */ 227 + for (i = 0; i < NR_CPUS; i++) 228 + clear_bit(irq, pcpu_masks[i].pcpu_mask); 229 + set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); 230 + 232 231 cpumask_copy(d->affinity, cpumask); 233 232 spin_unlock_irqrestore(&gic_lock, flags); 234 233

-4

arch/mips/kernel/mcount.S

··· 168 168 #endif 169 169 170 170 /* arg3: Get frame pointer of current stack */ 171 - #ifdef CONFIG_FRAME_POINTER 172 - move a2, fp 173 - #else /* ! CONFIG_FRAME_POINTER */ 174 171 #ifdef CONFIG_64BIT 175 172 PTR_LA a2, PT_SIZE(sp) 176 173 #else 177 174 PTR_LA a2, (PT_SIZE+8)(sp) 178 - #endif 179 175 #endif 180 176 181 177 jal prepare_ftrace_return

+7 -27

arch/mips/kernel/octeon_switch.S

··· 40 40 cpu_save_nonscratch a0 41 41 LONG_S ra, THREAD_REG31(a0) 42 42 43 - /* check if we need to save COP2 registers */ 44 - PTR_L t2, TASK_THREAD_INFO(a0) 45 - LONG_L t0, ST_OFF(t2) 46 - bbit0 t0, 30, 1f 47 - 48 - /* Disable COP2 in the stored process state */ 49 - li t1, ST0_CU2 50 - xor t0, t1 51 - LONG_S t0, ST_OFF(t2) 52 - 53 - /* Enable COP2 so we can save it */ 54 - mfc0 t0, CP0_STATUS 55 - or t0, t1 56 - mtc0 t0, CP0_STATUS 57 - 58 - /* Save COP2 */ 59 - daddu a0, THREAD_CP2 60 - jal octeon_cop2_save 61 - dsubu a0, THREAD_CP2 62 - 63 - /* Disable COP2 now that we are done */ 64 - mfc0 t0, CP0_STATUS 65 - li t1, ST0_CU2 66 - xor t0, t1 67 - mtc0 t0, CP0_STATUS 68 - 69 - 1: 70 43 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 71 44 /* Check if we need to store CVMSEG state */ 72 45 mfc0 t0, $11,7 /* CvmMemCtl */ ··· 71 98 mtc0 t0, $11,7 /* CvmMemCtl */ 72 99 #endif 73 100 3: 101 + 102 + #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 103 + PTR_L t8, __stack_chk_guard 104 + LONG_L t9, TASK_STACK_CANARY(a1) 105 + LONG_S t9, 0(t8) 106 + #endif 107 + 74 108 /* 75 109 * The order of restoring the registers takes care of the race 76 110 * updating $28, $29 and kernelsp without disabling ints.

+1 -3

arch/mips/kernel/proc.c

··· 66 66 seq_printf(m, "]\n"); 67 67 } 68 68 if (cpu_has_mips_r) { 69 - seq_printf(m, "isa\t\t\t:"); 70 - if (cpu_has_mips_1) 71 - seq_printf(m, "%s", " mips1"); 69 + seq_printf(m, "isa\t\t\t: mips1"); 72 70 if (cpu_has_mips_2) 73 71 seq_printf(m, "%s", " mips2"); 74 72 if (cpu_has_mips_3)

+6 -3

arch/mips/kernel/process.c

··· 201 201 return 1; 202 202 } 203 203 204 - /* 205 - * 206 - */ 204 + #ifdef CONFIG_CC_STACKPROTECTOR 205 + #include <linux/stackprotector.h> 206 + unsigned long __stack_chk_guard __read_mostly; 207 + EXPORT_SYMBOL(__stack_chk_guard); 208 + #endif 209 + 207 210 struct mips_frame_info { 208 211 void *func; 209 212 unsigned long func_size;

+1 -1

arch/mips/kernel/prom.c

··· 30 30 if (name == NULL) 31 31 return; 32 32 33 - strncpy(mips_machine_name, name, sizeof(mips_machine_name)); 33 + strlcpy(mips_machine_name, name, sizeof(mips_machine_name)); 34 34 pr_info("MIPS: machine is %s\n", mips_get_machine_name()); 35 35 } 36 36

+12

arch/mips/kernel/ptrace.c

··· 15 15 * binaries. 16 16 */ 17 17 #include <linux/compiler.h> 18 + #include <linux/context_tracking.h> 18 19 #include <linux/kernel.h> 19 20 #include <linux/sched.h> 20 21 #include <linux/mm.h> ··· 535 534 */ 536 535 asmlinkage void syscall_trace_enter(struct pt_regs *regs) 537 536 { 537 + user_exit(); 538 + 538 539 /* do the secure computing check first */ 539 540 secure_computing_strict(regs->regs[2]); 540 541 ··· 573 570 */ 574 571 asmlinkage void syscall_trace_leave(struct pt_regs *regs) 575 572 { 573 + /* 574 + * We may come here right after calling schedule_user() 575 + * or do_notify_resume(), in which case we can be in RCU 576 + * user mode. 577 + */ 578 + user_exit(); 579 + 576 580 audit_syscall_exit(regs); 577 581 578 582 if (!(current->ptrace & PT_PTRACED)) ··· 602 592 send_sig(current->exit_code, current, 1); 603 593 current->exit_code = 0; 604 594 } 595 + 596 + user_enter(); 605 597 }

+7

arch/mips/kernel/r2300_switch.S

··· 65 65 fpu_save_single a0, t0 # clobbers t0 66 66 67 67 1: 68 + 69 + #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 70 + PTR_L t8, __stack_chk_guard 71 + LONG_L t9, TASK_STACK_CANARY(a1) 72 + LONG_S t9, 0(t8) 73 + #endif 74 + 68 75 /* 69 76 * The order of restoring the registers takes care of the race 70 77 * updating $28, $29 and kernelsp without disabling ints.

+6

arch/mips/kernel/r4k_switch.S

··· 68 68 # clobbers t1 69 69 1: 70 70 71 + #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) 72 + PTR_L t8, __stack_chk_guard 73 + LONG_L t9, TASK_STACK_CANARY(a1) 74 + LONG_S t9, 0(t8) 75 + #endif 76 + 71 77 /* 72 78 * The order of restoring the registers takes care of the race 73 79 * updating $28, $29 and kernelsp without disabling ints.

-1

arch/mips/kernel/rtlx.c

··· 437 437 size_t count, loff_t * ppos) 438 438 { 439 439 int minor = iminor(file_inode(file)); 440 - struct rtlx_channel *rt = &rtlx->channel[minor]; 441 440 442 441 /* any space left... */ 443 442 if (!rtlx_write_poll(minor)) {

+1 -1

arch/mips/kernel/scall32-o32.S

··· 52 52 53 53 stack_done: 54 54 lw t0, TI_FLAGS($28) # syscall tracing enabled? 55 - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 55 + li t1, _TIF_WORK_SYSCALL_ENTRY 56 56 and t0, t1 57 57 bnez t0, syscall_trace_entry # -> yes 58 58

+1 -1

arch/mips/kernel/scall64-64.S

··· 54 54 55 55 sd a3, PT_R26(sp) # save a3 for syscall restarting 56 56 57 - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 57 + li t1, _TIF_WORK_SYSCALL_ENTRY 58 58 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 59 59 and t0, t1, t0 60 60 bnez t0, syscall_trace_entry

+1 -1

arch/mips/kernel/scall64-n32.S

··· 47 47 48 48 sd a3, PT_R26(sp) # save a3 for syscall restarting 49 49 50 - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 50 + li t1, _TIF_WORK_SYSCALL_ENTRY 51 51 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 52 52 and t0, t1, t0 53 53 bnez t0, n32_syscall_trace_entry

+1 -1

arch/mips/kernel/scall64-o32.S

··· 81 81 PTR 4b, bad_stack 82 82 .previous 83 83 84 - li t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT 84 + li t1, _TIF_WORK_SYSCALL_ENTRY 85 85 LONG_L t0, TI_FLAGS($28) # syscall tracing enabled? 86 86 and t0, t1, t0 87 87 bnez t0, trace_a_syscall

+5

arch/mips/kernel/signal.c

··· 8 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 9 */ 10 10 #include <linux/cache.h> 11 + #include <linux/context_tracking.h> 11 12 #include <linux/irqflags.h> 12 13 #include <linux/sched.h> 13 14 #include <linux/mm.h> ··· 574 573 { 575 574 local_irq_enable(); 576 575 576 + user_exit(); 577 + 577 578 /* deal with pending signal delivery */ 578 579 if (thread_info_flags & _TIF_SIGPENDING) 579 580 do_signal(regs); ··· 584 581 clear_thread_flag(TIF_NOTIFY_RESUME); 585 582 tracehook_notify_resume(regs); 586 583 } 584 + 585 + user_enter(); 587 586 } 588 587 589 588 #ifdef CONFIG_SMP

+23 -6

arch/mips/kernel/smp-bmips.c

··· 63 63 64 64 static void __init bmips_smp_setup(void) 65 65 { 66 - int i; 66 + int i, cpu = 1, boot_cpu = 0; 67 67 68 68 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 69 69 /* arbitration priority */ ··· 72 72 /* NBK and weak order flags */ 73 73 set_c0_brcm_config_0(0x30000); 74 74 75 + /* Find out if we are running on TP0 or TP1 */ 76 + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 77 + 75 78 /* 76 79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread 77 80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 78 81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 82 + * 83 + * If booting from TP1, leave the existing CMT interrupt routing 84 + * such that TP0 responds to SW1 and TP1 responds to SW0. 79 85 */ 80 - change_c0_brcm_cmt_intr(0xf8018000, 81 - (0x02 << 27) | (0x03 << 15)); 86 + if (boot_cpu == 0) 87 + change_c0_brcm_cmt_intr(0xf8018000, 88 + (0x02 << 27) | (0x03 << 15)); 89 + else 90 + change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27)); 82 91 83 92 /* single core, 2 threads (2 pipelines) */ 84 93 max_cpus = 2; ··· 115 106 if (!board_ebase_setup) 116 107 board_ebase_setup = &bmips_ebase_setup; 117 108 109 + __cpu_number_map[boot_cpu] = 0; 110 + __cpu_logical_map[0] = boot_cpu; 111 + 118 112 for (i = 0; i < max_cpus; i++) { 119 - __cpu_number_map[i] = 1; 120 - __cpu_logical_map[i] = 1; 113 + if (i != boot_cpu) { 114 + __cpu_number_map[i] = cpu; 115 + __cpu_logical_map[cpu] = i; 116 + cpu++; 117 + } 121 118 set_cpu_possible(i, 1); 122 119 set_cpu_present(i, 1); 123 120 } ··· 172 157 bmips_send_ipi_single(cpu, 0); 173 158 else { 174 159 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 175 - set_c0_brcm_cmt_ctrl(0x01); 160 + /* Reset slave TP1 if booting from TP0 */ 161 + if (cpu_logical_map(cpu) == 0) 162 + set_c0_brcm_cmt_ctrl(0x01); 176 163 #elif defined(CONFIG_CPU_BMIPS5000) 177 164 if (cpu & 0x01) 178 165 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));

+76 -28

arch/mips/kernel/traps.c

··· 13 13 */ 14 14 #include <linux/bug.h> 15 15 #include <linux/compiler.h> 16 + #include <linux/context_tracking.h> 16 17 #include <linux/kexec.h> 17 18 #include <linux/init.h> 18 19 #include <linux/kernel.h> ··· 265 264 266 265 printk("Status: %08x ", (uint32_t) regs->cp0_status); 267 266 268 - if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { 267 + if (cpu_has_3kex) { 269 268 if (regs->cp0_status & ST0_KUO) 270 269 printk("KUo "); 271 270 if (regs->cp0_status & ST0_IEO) ··· 278 277 printk("KUc "); 279 278 if (regs->cp0_status & ST0_IEC) 280 279 printk("IEc "); 281 - } else { 280 + } else if (cpu_has_4kex) { 282 281 if (regs->cp0_status & ST0_KX) 283 282 printk("KX "); 284 283 if (regs->cp0_status & ST0_SX) ··· 424 423 const struct exception_table_entry *fixup = NULL; 425 424 int data = regs->cp0_cause & 4; 426 425 int action = MIPS_BE_FATAL; 426 + enum ctx_state prev_state; 427 427 428 + prev_state = exception_enter(); 428 429 /* XXX For now. Fixme, this searches the wrong table ... */ 429 430 if (data && !user_mode(regs)) 430 431 fixup = search_dbe_tables(exception_epc(regs)); ··· 439 436 440 437 switch (action) { 441 438 case MIPS_BE_DISCARD: 442 - return; 439 + goto out; 443 440 case MIPS_BE_FIXUP: 444 441 if (fixup) { 445 442 regs->cp0_epc = fixup->nextinsn; 446 - return; 443 + goto out; 447 444 } 448 445 break; 449 446 default: ··· 458 455 field, regs->cp0_epc, field, regs->regs[31]); 459 456 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) 460 457 == NOTIFY_STOP) 461 - return; 458 + goto out; 462 459 463 460 die_if_kernel("Oops", regs); 464 461 force_sig(SIGBUS, current); 462 + 463 + out: 464 + exception_exit(prev_state); 465 465 } 466 466 467 467 /* ··· 679 673 680 674 asmlinkage void do_ov(struct pt_regs *regs) 681 675 { 676 + enum ctx_state prev_state; 682 677 siginfo_t info; 683 678 679 + prev_state = exception_enter(); 684 680 die_if_kernel("Integer overflow", regs); 685 681 686 682 info.si_code = FPE_INTOVF; ··· 690 682 info.si_errno = 0; 691 683 info.si_addr = (void __user *) regs->cp0_epc; 692 684 force_sig_info(SIGFPE, &info, current); 685 + exception_exit(prev_state); 693 686 } 694 687 695 688 int process_fpemu_return(int sig, void __user *fault_addr) ··· 722 713 */ 723 714 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 724 715 { 716 + enum ctx_state prev_state; 725 717 siginfo_t info = {0}; 726 718 719 + prev_state = exception_enter(); 727 720 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) 728 721 == NOTIFY_STOP) 729 - return; 722 + goto out; 730 723 die_if_kernel("FP exception in kernel code", regs); 731 724 732 725 if (fcr31 & FPU_CSR_UNI_X) { ··· 764 753 /* If something went wrong, signal */ 765 754 process_fpemu_return(sig, fault_addr); 766 755 767 - return; 756 + goto out; 768 757 } else if (fcr31 & FPU_CSR_INV_X) 769 758 info.si_code = FPE_FLTINV; 770 759 else if (fcr31 & FPU_CSR_DIV_X) ··· 781 770 info.si_errno = 0; 782 771 info.si_addr = (void __user *) regs->cp0_epc; 783 772 force_sig_info(SIGFPE, &info, current); 773 + 774 + out: 775 + exception_exit(prev_state); 784 776 } 785 777 786 778 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, ··· 849 835 asmlinkage void do_bp(struct pt_regs *regs) 850 836 { 851 837 unsigned int opcode, bcode; 838 + enum ctx_state prev_state; 852 839 unsigned long epc; 853 840 u16 instr[2]; 854 841 842 + prev_state = exception_enter(); 855 843 if (get_isa16_mode(regs->cp0_epc)) { 856 844 /* Calculate EPC. */ 857 845 epc = exception_epc(regs); ··· 868 852 goto out_sigsegv; 869 853 bcode = (instr[0] >> 6) & 0x3f; 870 854 do_trap_or_bp(regs, bcode, "Break"); 871 - return; 855 + goto out; 872 856 } 873 857 } else { 874 858 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) ··· 892 876 switch (bcode) { 893 877 case BRK_KPROBE_BP: 894 878 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 895 - return; 879 + goto out; 896 880 else 897 881 break; 898 882 case BRK_KPROBE_SSTEPBP: 899 883 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 900 - return; 884 + goto out; 901 885 else 902 886 break; 903 887 default: ··· 905 889 } 906 890 907 891 do_trap_or_bp(regs, bcode, "Break"); 892 + 893 + out: 894 + exception_exit(prev_state); 908 895 return; 909 896 910 897 out_sigsegv: 911 898 force_sig(SIGSEGV, current); 899 + goto out; 912 900 } 913 901 914 902 asmlinkage void do_tr(struct pt_regs *regs) 915 903 { 916 904 u32 opcode, tcode = 0; 905 + enum ctx_state prev_state; 917 906 u16 instr[2]; 918 907 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 919 908 909 + prev_state = exception_enter(); 920 910 if (get_isa16_mode(regs->cp0_epc)) { 921 911 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 922 912 __get_user(instr[1], (u16 __user *)(epc + 2))) ··· 940 918 } 941 919 942 920 do_trap_or_bp(regs, tcode, "Trap"); 921 + 922 + out: 923 + exception_exit(prev_state); 943 924 return; 944 925 945 926 out_sigsegv: 946 927 force_sig(SIGSEGV, current); 928 + goto out; 947 929 } 948 930 949 931 asmlinkage void do_ri(struct pt_regs *regs) ··· 955 929 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 956 930 unsigned long old_epc = regs->cp0_epc; 957 931 unsigned long old31 = regs->regs[31]; 932 + enum ctx_state prev_state; 958 933 unsigned int opcode = 0; 959 934 int status = -1; 960 935 936 + prev_state = exception_enter(); 961 937 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) 962 938 == NOTIFY_STOP) 963 - return; 939 + goto out; 964 940 965 941 die_if_kernel("Reserved instruction in kernel code", regs); 966 942 967 943 if (unlikely(compute_return_epc(regs) < 0)) 968 - return; 944 + goto out; 969 945 970 946 if (get_isa16_mode(regs->cp0_epc)) { 971 947 unsigned short mmop[2] = { 0 }; ··· 1002 974 regs->regs[31] = old31; 1003 975 force_sig(status, current); 1004 976 } 977 + 978 + out: 979 + exception_exit(prev_state); 1005 980 } 1006 981 1007 982 /* ··· 1056 1025 { 1057 1026 struct pt_regs *regs = data; 1058 1027 1059 - switch (action) { 1060 - default: 1061 - die_if_kernel("Unhandled kernel unaligned access or invalid " 1028 + die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1062 1029 "instruction", regs); 1063 - /* Fall through */ 1064 - 1065 - case CU2_EXCEPTION: 1066 - force_sig(SIGILL, current); 1067 - } 1030 + force_sig(SIGILL, current); 1068 1031 1069 1032 return NOTIFY_OK; 1070 1033 } 1071 1034 1072 1035 asmlinkage void do_cpu(struct pt_regs *regs) 1073 1036 { 1037 + enum ctx_state prev_state; 1074 1038 unsigned int __user *epc; 1075 1039 unsigned long old_epc, old31; 1076 1040 unsigned int opcode; ··· 1073 1047 int status; 1074 1048 unsigned long __maybe_unused flags; 1075 1049 1076 - die_if_kernel("do_cpu invoked from kernel context!", regs); 1077 - 1050 + prev_state = exception_enter(); 1078 1051 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1052 + 1053 + if (cpid != 2) 1054 + die_if_kernel("do_cpu invoked from kernel context!", regs); 1079 1055 1080 1056 switch (cpid) { 1081 1057 case 0: ··· 1088 1060 status = -1; 1089 1061 1090 1062 if (unlikely(compute_return_epc(regs) < 0)) 1091 - return; 1063 + goto out; 1092 1064 1093 1065 if (get_isa16_mode(regs->cp0_epc)) { 1094 1066 unsigned short mmop[2] = { 0 }; ··· 1121 1093 force_sig(status, current); 1122 1094 } 1123 1095 1124 - return; 1096 + goto out; 1125 1097 1126 1098 case 3: 1127 1099 /* ··· 1159 1131 mt_ase_fp_affinity(); 1160 1132 } 1161 1133 1162 - return; 1134 + goto out; 1163 1135 1164 1136 case 2: 1165 1137 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1166 - return; 1138 + goto out; 1167 1139 } 1168 1140 1169 1141 force_sig(SIGILL, current); 1142 + 1143 + out: 1144 + exception_exit(prev_state); 1170 1145 } 1171 1146 1172 1147 asmlinkage void do_mdmx(struct pt_regs *regs) 1173 1148 { 1149 + enum ctx_state prev_state; 1150 + 1151 + prev_state = exception_enter(); 1174 1152 force_sig(SIGILL, current); 1153 + exception_exit(prev_state); 1175 1154 } 1176 1155 1177 1156 /* ··· 1186 1151 */ 1187 1152 asmlinkage void do_watch(struct pt_regs *regs) 1188 1153 { 1154 + enum ctx_state prev_state; 1189 1155 u32 cause; 1190 1156 1157 + prev_state = exception_enter(); 1191 1158 /* 1192 1159 * Clear WP (bit 22) bit of cause register so we don't loop 1193 1160 * forever. ··· 1211 1174 mips_clear_watch_registers(); 1212 1175 local_irq_enable(); 1213 1176 } 1177 + exception_exit(prev_state); 1214 1178 } 1215 1179 1216 1180 asmlinkage void do_mcheck(struct pt_regs *regs) 1217 1181 { 1218 1182 const int field = 2 * sizeof(unsigned long); 1219 1183 int multi_match = regs->cp0_status & ST0_TS; 1184 + enum ctx_state prev_state; 1220 1185 1186 + prev_state = exception_enter(); 1221 1187 show_regs(regs); 1222 1188 1223 1189 if (multi_match) { ··· 1242 1202 panic("Caught Machine Check exception - %scaused by multiple " 1243 1203 "matching entries in the TLB.", 1244 1204 (multi_match) ? "" : "not "); 1205 + exception_exit(prev_state); 1245 1206 } 1246 1207 1247 1208 asmlinkage void do_mt(struct pt_regs *regs) ··· 1668 1627 } 1669 1628 1670 1629 extern void tlb_init(void); 1671 - extern void flush_tlb_handlers(void); 1672 1630 1673 1631 /* 1674 1632 * Timer interrupt ··· 1877 1837 ebase += (read_c0_ebase() & 0x3ffff000); 1878 1838 } 1879 1839 1840 + if (cpu_has_mmips) { 1841 + unsigned int config3 = read_c0_config3(); 1842 + 1843 + if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 1844 + write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 1845 + else 1846 + write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 1847 + } 1848 + 1880 1849 if (board_ebase_setup) 1881 1850 board_ebase_setup(); 1882 1851 per_cpu_trap_init(true); ··· 2005 1956 set_handler(0x080, &except_vec3_generic, 0x80); 2006 1957 2007 1958 local_flush_icache_range(ebase, ebase + 0x400); 2008 - flush_tlb_handlers(); 2009 1959 2010 1960 sort_extable(__start___dbe_table, __stop___dbe_table); 2011 1961

+7 -1

arch/mips/kernel/unaligned.c

··· 72 72 * A store crossing a page boundary might be executed only partially. 73 73 * Undo the partial store in this case. 74 74 */ 75 + #include <linux/context_tracking.h> 75 76 #include <linux/mm.h> 76 77 #include <linux/signal.h> 77 78 #include <linux/smp.h> ··· 685 684 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */ 686 685 const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; 687 686 688 - void emulate_load_store_microMIPS(struct pt_regs *regs, void __user * addr) 687 + static void emulate_load_store_microMIPS(struct pt_regs *regs, 688 + void __user *addr) 689 689 { 690 690 unsigned long value; 691 691 unsigned int res; ··· 1550 1548 ("Unhandled kernel unaligned access or invalid instruction", regs); 1551 1549 force_sig(SIGILL, current); 1552 1550 } 1551 + 1553 1552 asmlinkage void do_ade(struct pt_regs *regs) 1554 1553 { 1554 + enum ctx_state prev_state; 1555 1555 unsigned int __user *pc; 1556 1556 mm_segment_t seg; 1557 1557 1558 + prev_state = exception_enter(); 1558 1559 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1559 1560 1, regs, regs->cp0_badvaddr); 1560 1561 /* ··· 1633 1628 /* 1634 1629 * XXX On return from the signal handler we should advance the epc 1635 1630 */ 1631 + exception_exit(prev_state); 1636 1632 } 1637 1633 1638 1634 #ifdef CONFIG_DEBUG_FS

+8

arch/mips/kernel/watch.c

··· 111 111 * disable the register. 112 112 */ 113 113 write_c0_watchlo0(7); 114 + back_to_back_c0_hazard(); 114 115 t = read_c0_watchlo0(); 115 116 write_c0_watchlo0(0); 116 117 c->watch_reg_masks[0] = t & 7; ··· 122 121 c->watch_reg_use_cnt = 1; 123 122 t = read_c0_watchhi0(); 124 123 write_c0_watchhi0(t | 0xff8); 124 + back_to_back_c0_hazard(); 125 125 t = read_c0_watchhi0(); 126 126 c->watch_reg_masks[0] |= (t & 0xff8); 127 127 if ((t & 0x80000000) == 0) 128 128 return; 129 129 130 130 write_c0_watchlo1(7); 131 + back_to_back_c0_hazard(); 131 132 t = read_c0_watchlo1(); 132 133 write_c0_watchlo1(0); 133 134 c->watch_reg_masks[1] = t & 7; ··· 138 135 c->watch_reg_use_cnt = 2; 139 136 t = read_c0_watchhi1(); 140 137 write_c0_watchhi1(t | 0xff8); 138 + back_to_back_c0_hazard(); 141 139 t = read_c0_watchhi1(); 142 140 c->watch_reg_masks[1] |= (t & 0xff8); 143 141 if ((t & 0x80000000) == 0) 144 142 return; 145 143 146 144 write_c0_watchlo2(7); 145 + back_to_back_c0_hazard(); 147 146 t = read_c0_watchlo2(); 148 147 write_c0_watchlo2(0); 149 148 c->watch_reg_masks[2] = t & 7; ··· 154 149 c->watch_reg_use_cnt = 3; 155 150 t = read_c0_watchhi2(); 156 151 write_c0_watchhi2(t | 0xff8); 152 + back_to_back_c0_hazard(); 157 153 t = read_c0_watchhi2(); 158 154 c->watch_reg_masks[2] |= (t & 0xff8); 159 155 if ((t & 0x80000000) == 0) 160 156 return; 161 157 162 158 write_c0_watchlo3(7); 159 + back_to_back_c0_hazard(); 163 160 t = read_c0_watchlo3(); 164 161 write_c0_watchlo3(0); 165 162 c->watch_reg_masks[3] = t & 7; ··· 170 163 c->watch_reg_use_cnt = 4; 171 164 t = read_c0_watchhi3(); 172 165 write_c0_watchhi3(t | 0xff8); 166 + back_to_back_c0_hazard(); 173 167 t = read_c0_watchhi3(); 174 168 c->watch_reg_masks[3] |= (t & 0xff8); 175 169 if ((t & 0x80000000) == 0)

+1 -1

arch/mips/lantiq/prom.c

··· 112 112 if (!of_have_populated_dt()) 113 113 panic("device tree not present"); 114 114 115 - strncpy(of_ids[0].compatible, soc_info.compatible, 115 + strlcpy(of_ids[0].compatible, soc_info.compatible, 116 116 sizeof(of_ids[0].compatible)); 117 117 strncpy(of_ids[1].compatible, "simple-bus", 118 118 sizeof(of_ids[1].compatible));

+7 -7

arch/mips/lasat/sysctl.c

··· 39 39 40 40 41 41 /* And the same for proc */ 42 - int proc_dolasatstring(ctl_table *table, int write, 42 + int proc_dolasatstring(struct ctl_table *table, int write, 43 43 void *buffer, size_t *lenp, loff_t *ppos) 44 44 { 45 45 int r; ··· 54 54 } 55 55 56 56 /* proc function to write EEPROM after changing int entry */ 57 - int proc_dolasatint(ctl_table *table, int write, 57 + int proc_dolasatint(struct ctl_table *table, int write, 58 58 void *buffer, size_t *lenp, loff_t *ppos) 59 59 { 60 60 int r; ··· 72 72 static int rtctmp; 73 73 74 74 /* proc function to read/write RealTime Clock */ 75 - int proc_dolasatrtc(ctl_table *table, int write, 75 + int proc_dolasatrtc(struct ctl_table *table, int write, 76 76 void *buffer, size_t *lenp, loff_t *ppos) 77 77 { 78 78 struct timespec ts; ··· 97 97 #endif 98 98 99 99 #ifdef CONFIG_INET 100 - int proc_lasat_ip(ctl_table *table, int write, 100 + int proc_lasat_ip(struct ctl_table *table, int write, 101 101 void *buffer, size_t *lenp, loff_t *ppos) 102 102 { 103 103 unsigned int ip; ··· 157 157 } 158 158 #endif 159 159 160 - int proc_lasat_prid(ctl_table *table, int write, 160 + int proc_lasat_prid(struct ctl_table *table, int write, 161 161 void *buffer, size_t *lenp, loff_t *ppos) 162 162 { 163 163 int r; ··· 176 176 177 177 extern int lasat_boot_to_service; 178 178 179 - static ctl_table lasat_table[] = { 179 + static struct ctl_table lasat_table[] = { 180 180 { 181 181 .procname = "cpu-hz", 182 182 .data = &lasat_board_info.li_cpu_hz, ··· 262 262 {} 263 263 }; 264 264 265 - static ctl_table lasat_root_table[] = { 265 + static struct ctl_table lasat_root_table[] = { 266 266 { 267 267 .procname = "lasat", 268 268 .mode = 0555,

+14

arch/mips/loongson/common/cs5536/cs5536_isa.c

··· 13 13 * option) any later version. 14 14 */ 15 15 16 + #include <linux/pci.h> 16 17 #include <cs5536/cs5536.h> 17 18 #include <cs5536/cs5536_pci.h> 18 19 ··· 315 314 316 315 return conf_data; 317 316 } 317 + 318 + /* 319 + * The mfgpt timer interrupt is running early, so we must keep the south bridge 320 + * mmio always enabled. Otherwise we may race with the PCI configuration which 321 + * may temporarily disable it. When that happens and the timer interrupt fires, 322 + * we are not able to clear it and the system will hang. 323 + */ 324 + static void cs5536_isa_mmio_always_on(struct pci_dev *dev) 325 + { 326 + dev->mmio_always_on = 1; 327 + } 328 + DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 329 + PCI_CLASS_BRIDGE_ISA, 8, cs5536_isa_mmio_always_on);

+3

arch/mips/math-emu/cp1emu.c

··· 471 471 unsigned int fcr31; 472 472 unsigned int bit; 473 473 474 + if (!cpu_has_mmips) 475 + return 0; 476 + 474 477 switch (insn.mm_i_format.opcode) { 475 478 case mm_pool32a_op: 476 479 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==

+1 -1

arch/mips/mm/Makefile

··· 4 4 5 5 obj-y += cache.o dma-default.o extable.o fault.o \ 6 6 gup.o init.o mmap.o page.o page-funcs.o \ 7 - tlbex.o tlbex-fault.o uasm-mips.o 7 + tlbex.o tlbex-fault.o tlb-funcs.o uasm-mips.o 8 8 9 9 obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 10 10 obj-$(CONFIG_64BIT) += pgtable-64.o

-4

arch/mips/mm/cerr-sb1.c

··· 182 182 183 183 #ifdef CONFIG_SIBYTE_BW_TRACE 184 184 /* Freeze the trace buffer now */ 185 - #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 186 - csr_out32(M_BCM1480_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 187 - #else 188 185 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); 189 - #endif 190 186 printk("Trace buffer frozen\n"); 191 187 #endif 192 188

+3

arch/mips/mm/dma-default.c

··· 246 246 if (!plat_device_is_coherent(dev)) 247 247 __dma_sync(sg_page(sg), sg->offset, sg->length, 248 248 direction); 249 + #ifdef CONFIG_NEED_SG_DMA_LENGTH 250 + sg->dma_length = sg->length; 251 + #endif 249 252 sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + 250 253 sg->offset; 251 254 }

+13 -2

arch/mips/mm/fault.c

··· 5 5 * 6 6 * Copyright (C) 1995 - 2000 by Ralf Baechle 7 7 */ 8 + #include <linux/context_tracking.h> 8 9 #include <linux/signal.h> 9 10 #include <linux/sched.h> 10 11 #include <linux/interrupt.h> ··· 33 32 * and the problem, and then passes it off to one of the appropriate 34 33 * routines. 35 34 */ 36 - asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write, 37 - unsigned long address) 35 + static void __kprobes __do_page_fault(struct pt_regs *regs, unsigned long write, 36 + unsigned long address) 38 37 { 39 38 struct vm_area_struct * vma = NULL; 40 39 struct task_struct *tsk = current; ··· 312 311 return; 313 312 } 314 313 #endif 314 + } 315 + 316 + asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, 317 + unsigned long write, unsigned long address) 318 + { 319 + enum ctx_state prev_state; 320 + 321 + prev_state = exception_enter(); 322 + __do_page_fault(regs, write, address); 323 + exception_exit(prev_state); 315 324 }

+1 -1

arch/mips/mm/page.c

··· 232 232 233 233 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); 234 234 } 235 - } 235 + } 236 236 } 237 237 238 238 extern u32 __clear_page_start;

+37

arch/mips/mm/tlb-funcs.S

··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Micro-assembler generated tlb handler functions. 7 + * 8 + * Copyright (C) 2013 Broadcom Corporation. 9 + * 10 + * Based on mm/page-funcs.c 11 + * Copyright (C) 2012 MIPS Technologies, Inc. 12 + * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> 13 + */ 14 + #include <asm/asm.h> 15 + #include <asm/regdef.h> 16 + 17 + #define FASTPATH_SIZE 128 18 + 19 + LEAF(tlbmiss_handler_setup_pgd) 20 + .space 16 * 4 21 + END(tlbmiss_handler_setup_pgd) 22 + EXPORT(tlbmiss_handler_setup_pgd_end) 23 + 24 + LEAF(handle_tlbm) 25 + .space FASTPATH_SIZE * 4 26 + END(handle_tlbm) 27 + EXPORT(handle_tlbm_end) 28 + 29 + LEAF(handle_tlbs) 30 + .space FASTPATH_SIZE * 4 31 + END(handle_tlbs) 32 + EXPORT(handle_tlbs_end) 33 + 34 + LEAF(handle_tlbl) 35 + .space FASTPATH_SIZE * 4 36 + END(handle_tlbl) 37 + EXPORT(handle_tlbl_end)

+114 -71

arch/mips/mm/tlbex.c

··· 305 305 306 306 static unsigned int kscratch_used_mask __cpuinitdata; 307 307 308 + static inline int __maybe_unused c0_kscratch(void) 309 + { 310 + switch (current_cpu_type()) { 311 + case CPU_XLP: 312 + case CPU_XLR: 313 + return 22; 314 + default: 315 + return 31; 316 + } 317 + } 318 + 308 319 static int __cpuinit allocate_kscratch(void) 309 320 { 310 321 int r; ··· 345 334 int smp_processor_id_sel; 346 335 int smp_processor_id_shift; 347 336 348 - if (scratch_reg > 0) { 337 + if (scratch_reg >= 0) { 349 338 /* Save in CPU local C0_KScratch? */ 350 - UASM_i_MTC0(p, 1, 31, scratch_reg); 339 + UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 351 340 r.r1 = K0; 352 341 r.r2 = K1; 353 342 r.r3 = 1; ··· 395 384 396 385 static void __cpuinit build_restore_work_registers(u32 **p) 397 386 { 398 - if (scratch_reg > 0) { 399 - UASM_i_MFC0(p, 1, 31, scratch_reg); 387 + if (scratch_reg >= 0) { 388 + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 400 389 return; 401 390 } 402 391 /* K0 already points to save area, restore $1 and $2 */ ··· 684 673 uasm_i_mtc0(p, 0, C0_PAGEMASK); 685 674 uasm_il_b(p, r, lid); 686 675 } 687 - if (scratch_reg > 0) 688 - UASM_i_MFC0(p, 1, 31, scratch_reg); 676 + if (scratch_reg >= 0) 677 + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 689 678 else 690 679 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 691 680 } else { ··· 828 817 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 829 818 if (pgd_reg != -1) { 830 819 /* pgd is in pgd_reg */ 831 - UASM_i_MFC0(p, ptr, 31, pgd_reg); 820 + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 832 821 } else { 833 822 /* 834 823 * &pgd << 11 stored in CONTEXT [23..63]. ··· 940 929 uasm_i_jr(p, ptr); 941 930 942 931 if (mode == refill_scratch) { 943 - if (scratch_reg > 0) 944 - UASM_i_MFC0(p, 1, 31, scratch_reg); 932 + if (scratch_reg >= 0) 933 + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 945 934 else 946 935 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 947 936 } else { ··· 972 961 uasm_i_srl(p, ptr, ptr, 19); 973 962 #else 974 963 /* 975 - * smp_processor_id() << 3 is stored in CONTEXT. 964 + * smp_processor_id() << 2 is stored in CONTEXT. 976 965 */ 977 966 uasm_i_mfc0(p, ptr, C0_CONTEXT); 978 967 UASM_i_LA_mostly(p, tmp, pgdc); ··· 1107 1096 static struct mips_huge_tlb_info __cpuinit 1108 1097 build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1109 1098 struct uasm_reloc **r, unsigned int tmp, 1110 - unsigned int ptr, int c0_scratch) 1099 + unsigned int ptr, int c0_scratch_reg) 1111 1100 { 1112 1101 struct mips_huge_tlb_info rv; 1113 1102 unsigned int even, odd; ··· 1121 1110 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1122 1111 1123 1112 if (pgd_reg != -1) 1124 - UASM_i_MFC0(p, ptr, 31, pgd_reg); 1113 + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1125 1114 else 1126 1115 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1127 1116 1128 - if (c0_scratch >= 0) 1129 - UASM_i_MTC0(p, scratch, 31, c0_scratch); 1117 + if (c0_scratch_reg >= 0) 1118 + UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1130 1119 else 1131 1120 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1132 1121 ··· 1141 1130 } 1142 1131 } else { 1143 1132 if (pgd_reg != -1) 1144 - UASM_i_MFC0(p, ptr, 31, pgd_reg); 1133 + UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1145 1134 else 1146 1135 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1147 1136 1148 1137 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1149 1138 1150 - if (c0_scratch >= 0) 1151 - UASM_i_MTC0(p, scratch, 31, c0_scratch); 1139 + if (c0_scratch_reg >= 0) 1140 + UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1152 1141 else 1153 1142 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1154 1143 ··· 1253 1242 } 1254 1243 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1255 1244 1256 - if (c0_scratch >= 0) { 1257 - UASM_i_MFC0(p, scratch, 31, c0_scratch); 1245 + if (c0_scratch_reg >= 0) { 1246 + UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1258 1247 build_tlb_write_entry(p, l, r, tlb_random); 1259 1248 uasm_l_leave(l, *p); 1260 1249 rv.restore_scratch = 1; ··· 1297 1286 memset(relocs, 0, sizeof(relocs)); 1298 1287 memset(final_handler, 0, sizeof(final_handler)); 1299 1288 1300 - if ((scratch_reg > 0 || scratchpad_available()) && use_bbit_insns()) { 1289 + if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1301 1290 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1302 1291 scratch_reg); 1303 1292 vmalloc_mode = refill_scratch; ··· 1455 1444 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); 1456 1445 } 1457 1446 1458 - /* 1459 - * 128 instructions for the fastpath handler is generous and should 1460 - * never be exceeded. 1461 - */ 1462 - #define FASTPATH_SIZE 128 1447 + extern u32 handle_tlbl[], handle_tlbl_end[]; 1448 + extern u32 handle_tlbs[], handle_tlbs_end[]; 1449 + extern u32 handle_tlbm[], handle_tlbm_end[]; 1463 1450 1464 - u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; 1465 - u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; 1466 - u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; 1467 1451 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1468 - u32 tlbmiss_handler_setup_pgd_array[16] __cacheline_aligned; 1452 + extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; 1469 1453 1470 1454 static void __cpuinit build_r4000_setup_pgd(void) 1471 1455 { 1472 1456 const int a0 = 4; 1473 1457 const int a1 = 5; 1474 1458 u32 *p = tlbmiss_handler_setup_pgd_array; 1459 + const int tlbmiss_handler_setup_pgd_size = 1460 + tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; 1475 1461 struct uasm_label *l = labels; 1476 1462 struct uasm_reloc *r = relocs; 1477 1463 1478 - memset(tlbmiss_handler_setup_pgd_array, 0, sizeof(tlbmiss_handler_setup_pgd_array)); 1464 + memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * 1465 + sizeof(tlbmiss_handler_setup_pgd[0])); 1479 1466 memset(labels, 0, sizeof(labels)); 1480 1467 memset(relocs, 0, sizeof(relocs)); 1481 1468 ··· 1499 1490 } else { 1500 1491 /* PGD in c0_KScratch */ 1501 1492 uasm_i_jr(&p, 31); 1502 - UASM_i_MTC0(&p, a0, 31, pgd_reg); 1493 + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1503 1494 } 1504 - if (p - tlbmiss_handler_setup_pgd_array > ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)) 1505 - panic("tlbmiss_handler_setup_pgd_array space exceeded"); 1506 - uasm_resolve_relocs(relocs, labels); 1507 - pr_debug("Wrote tlbmiss_handler_setup_pgd_array (%u instructions).\n", 1508 - (unsigned int)(p - tlbmiss_handler_setup_pgd_array)); 1495 + if (p >= tlbmiss_handler_setup_pgd_end) 1496 + panic("tlbmiss_handler_setup_pgd space exceeded"); 1509 1497 1510 - dump_handler("tlbmiss_handler", 1511 - tlbmiss_handler_setup_pgd_array, 1512 - ARRAY_SIZE(tlbmiss_handler_setup_pgd_array)); 1498 + uasm_resolve_relocs(relocs, labels); 1499 + pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1500 + (unsigned int)(p - tlbmiss_handler_setup_pgd)); 1501 + 1502 + dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1503 + tlbmiss_handler_setup_pgd_size); 1513 1504 } 1514 1505 #endif 1515 1506 ··· 1754 1745 static void __cpuinit build_r3000_tlb_load_handler(void) 1755 1746 { 1756 1747 u32 *p = handle_tlbl; 1748 + const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1757 1749 struct uasm_label *l = labels; 1758 1750 struct uasm_reloc *r = relocs; 1759 1751 1760 - memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1752 + memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1761 1753 memset(labels, 0, sizeof(labels)); 1762 1754 memset(relocs, 0, sizeof(relocs)); 1763 1755 ··· 1772 1762 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1773 1763 uasm_i_nop(&p); 1774 1764 1775 - if ((p - handle_tlbl) > FASTPATH_SIZE) 1765 + if (p >= handle_tlbl_end) 1776 1766 panic("TLB load handler fastpath space exceeded"); 1777 1767 1778 1768 uasm_resolve_relocs(relocs, labels); 1779 1769 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1780 1770 (unsigned int)(p - handle_tlbl)); 1781 1771 1782 - dump_handler("r3000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); 1772 + dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); 1783 1773 } 1784 1774 1785 1775 static void __cpuinit build_r3000_tlb_store_handler(void) 1786 1776 { 1787 1777 u32 *p = handle_tlbs; 1778 + const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 1788 1779 struct uasm_label *l = labels; 1789 1780 struct uasm_reloc *r = relocs; 1790 1781 1791 - memset(handle_tlbs, 0, sizeof(handle_tlbs)); 1782 + memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 1792 1783 memset(labels, 0, sizeof(labels)); 1793 1784 memset(relocs, 0, sizeof(relocs)); 1794 1785 ··· 1803 1792 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1804 1793 uasm_i_nop(&p); 1805 1794 1806 - if ((p - handle_tlbs) > FASTPATH_SIZE) 1795 + if (p >= handle_tlbs) 1807 1796 panic("TLB store handler fastpath space exceeded"); 1808 1797 1809 1798 uasm_resolve_relocs(relocs, labels); 1810 1799 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1811 1800 (unsigned int)(p - handle_tlbs)); 1812 1801 1813 - dump_handler("r3000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); 1802 + dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); 1814 1803 } 1815 1804 1816 1805 static void __cpuinit build_r3000_tlb_modify_handler(void) 1817 1806 { 1818 1807 u32 *p = handle_tlbm; 1808 + const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 1819 1809 struct uasm_label *l = labels; 1820 1810 struct uasm_reloc *r = relocs; 1821 1811 1822 - memset(handle_tlbm, 0, sizeof(handle_tlbm)); 1812 + memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 1823 1813 memset(labels, 0, sizeof(labels)); 1824 1814 memset(relocs, 0, sizeof(relocs)); 1825 1815 ··· 1834 1822 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1835 1823 uasm_i_nop(&p); 1836 1824 1837 - if ((p - handle_tlbm) > FASTPATH_SIZE) 1825 + if (p >= handle_tlbm_end) 1838 1826 panic("TLB modify handler fastpath space exceeded"); 1839 1827 1840 1828 uasm_resolve_relocs(relocs, labels); 1841 1829 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1842 1830 (unsigned int)(p - handle_tlbm)); 1843 1831 1844 - dump_handler("r3000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1832 + dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); 1845 1833 } 1846 1834 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 1847 1835 ··· 1905 1893 static void __cpuinit build_r4000_tlb_load_handler(void) 1906 1894 { 1907 1895 u32 *p = handle_tlbl; 1896 + const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1908 1897 struct uasm_label *l = labels; 1909 1898 struct uasm_reloc *r = relocs; 1910 1899 struct work_registers wr; 1911 1900 1912 - memset(handle_tlbl, 0, sizeof(handle_tlbl)); 1901 + memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1913 1902 memset(labels, 0, sizeof(labels)); 1914 1903 memset(relocs, 0, sizeof(relocs)); 1915 1904 ··· 1948 1935 uasm_i_nop(&p); 1949 1936 1950 1937 uasm_i_tlbr(&p); 1938 + 1939 + switch (current_cpu_type()) { 1940 + default: 1941 + if (cpu_has_mips_r2) { 1942 + uasm_i_ehb(&p); 1943 + 1944 + case CPU_CAVIUM_OCTEON: 1945 + case CPU_CAVIUM_OCTEON_PLUS: 1946 + case CPU_CAVIUM_OCTEON2: 1947 + break; 1948 + } 1949 + } 1950 + 1951 1951 /* Examine entrylo 0 or 1 based on ptr. */ 1952 1952 if (use_bbit_insns()) { 1953 1953 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); ··· 2015 1989 uasm_i_nop(&p); 2016 1990 2017 1991 uasm_i_tlbr(&p); 1992 + 1993 + switch (current_cpu_type()) { 1994 + default: 1995 + if (cpu_has_mips_r2) { 1996 + uasm_i_ehb(&p); 1997 + 1998 + case CPU_CAVIUM_OCTEON: 1999 + case CPU_CAVIUM_OCTEON_PLUS: 2000 + case CPU_CAVIUM_OCTEON2: 2001 + break; 2002 + } 2003 + } 2004 + 2018 2005 /* Examine entrylo 0 or 1 based on ptr. */ 2019 2006 if (use_bbit_insns()) { 2020 2007 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); ··· 2075 2036 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2076 2037 uasm_i_nop(&p); 2077 2038 2078 - if ((p - handle_tlbl) > FASTPATH_SIZE) 2039 + if (p >= handle_tlbl_end) 2079 2040 panic("TLB load handler fastpath space exceeded"); 2080 2041 2081 2042 uasm_resolve_relocs(relocs, labels); 2082 2043 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2083 2044 (unsigned int)(p - handle_tlbl)); 2084 2045 2085 - dump_handler("r4000_tlb_load", handle_tlbl, ARRAY_SIZE(handle_tlbl)); 2046 + dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); 2086 2047 } 2087 2048 2088 2049 static void __cpuinit build_r4000_tlb_store_handler(void) 2089 2050 { 2090 2051 u32 *p = handle_tlbs; 2052 + const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 2091 2053 struct uasm_label *l = labels; 2092 2054 struct uasm_reloc *r = relocs; 2093 2055 struct work_registers wr; 2094 2056 2095 - memset(handle_tlbs, 0, sizeof(handle_tlbs)); 2057 + memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 2096 2058 memset(labels, 0, sizeof(labels)); 2097 2059 memset(relocs, 0, sizeof(relocs)); 2098 2060 ··· 2130 2090 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2131 2091 uasm_i_nop(&p); 2132 2092 2133 - if ((p - handle_tlbs) > FASTPATH_SIZE) 2093 + if (p >= handle_tlbs_end) 2134 2094 panic("TLB store handler fastpath space exceeded"); 2135 2095 2136 2096 uasm_resolve_relocs(relocs, labels); 2137 2097 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2138 2098 (unsigned int)(p - handle_tlbs)); 2139 2099 2140 - dump_handler("r4000_tlb_store", handle_tlbs, ARRAY_SIZE(handle_tlbs)); 2100 + dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); 2141 2101 } 2142 2102 2143 2103 static void __cpuinit build_r4000_tlb_modify_handler(void) 2144 2104 { 2145 2105 u32 *p = handle_tlbm; 2106 + const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 2146 2107 struct uasm_label *l = labels; 2147 2108 struct uasm_reloc *r = relocs; 2148 2109 struct work_registers wr; 2149 2110 2150 - memset(handle_tlbm, 0, sizeof(handle_tlbm)); 2111 + memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 2151 2112 memset(labels, 0, sizeof(labels)); 2152 2113 memset(relocs, 0, sizeof(relocs)); 2153 2114 ··· 2186 2145 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2187 2146 uasm_i_nop(&p); 2188 2147 2189 - if ((p - handle_tlbm) > FASTPATH_SIZE) 2148 + if (p >= handle_tlbm_end) 2190 2149 panic("TLB modify handler fastpath space exceeded"); 2191 2150 2192 2151 uasm_resolve_relocs(relocs, labels); 2193 2152 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2194 2153 (unsigned int)(p - handle_tlbm)); 2195 2154 2196 - dump_handler("r4000_tlb_modify", handle_tlbm, ARRAY_SIZE(handle_tlbm)); 2155 + dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2156 + } 2157 + 2158 + static void __cpuinit flush_tlb_handlers(void) 2159 + { 2160 + local_flush_icache_range((unsigned long)handle_tlbl, 2161 + (unsigned long)handle_tlbl_end); 2162 + local_flush_icache_range((unsigned long)handle_tlbs, 2163 + (unsigned long)handle_tlbs_end); 2164 + local_flush_icache_range((unsigned long)handle_tlbm, 2165 + (unsigned long)handle_tlbm_end); 2166 + #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 2167 + local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2168 + (unsigned long)tlbmiss_handler_setup_pgd_end); 2169 + #endif 2197 2170 } 2198 2171 2199 2172 void __cpuinit build_tlb_refill_handler(void) ··· 2242 2187 build_r3000_tlb_load_handler(); 2243 2188 build_r3000_tlb_store_handler(); 2244 2189 build_r3000_tlb_modify_handler(); 2190 + flush_tlb_handlers(); 2245 2191 run_once++; 2246 2192 } 2247 2193 #else ··· 2270 2214 build_r4000_tlb_modify_handler(); 2271 2215 if (!cpu_has_local_ebase) 2272 2216 build_r4000_tlb_refill_handler(); 2217 + flush_tlb_handlers(); 2273 2218 run_once++; 2274 2219 } 2275 2220 if (cpu_has_local_ebase) 2276 2221 build_r4000_tlb_refill_handler(); 2277 2222 } 2278 - } 2279 - 2280 - void __cpuinit flush_tlb_handlers(void) 2281 - { 2282 - local_flush_icache_range((unsigned long)handle_tlbl, 2283 - (unsigned long)handle_tlbl + sizeof(handle_tlbl)); 2284 - local_flush_icache_range((unsigned long)handle_tlbs, 2285 - (unsigned long)handle_tlbs + sizeof(handle_tlbs)); 2286 - local_flush_icache_range((unsigned long)handle_tlbm, 2287 - (unsigned long)handle_tlbm + sizeof(handle_tlbm)); 2288 - #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 2289 - local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd_array, 2290 - (unsigned long)tlbmiss_handler_setup_pgd_array + sizeof(handle_tlbm)); 2291 - #endif 2292 2223 }

-1

arch/mips/mti-malta/Makefile

··· 10 10 malta-reset.o malta-setup.o malta-time.o 11 11 12 12 obj-$(CONFIG_EARLY_PRINTK) += malta-console.o 13 - obj-$(CONFIG_PCI) += malta-pci.o 14 13 15 14 # FIXME FIXME FIXME 16 15 obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o

+3 -1

arch/mips/mti-malta/malta-int.c

··· 422 422 */ 423 423 int __init gcmp_probe(unsigned long addr, unsigned long size) 424 424 { 425 - if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { 425 + if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) && 426 + (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) { 426 427 gcmp_present = 0; 428 + pr_debug("GCMP NOT present\n"); 427 429 return gcmp_present; 428 430 } 429 431

arch/mips/mti-malta/malta-pci.c arch/mips/pci/pci-malta.c

+8 -25

arch/mips/mti-malta/malta-reset.c

··· 1 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 2 6 * Carsten Langgaard, carstenl@mips.com 3 7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 - * 5 - * ######################################################################## 6 - * 7 - * This program is free software; you can distribute it and/or modify it 8 - * under the terms of the GNU General Public License (Version 2) as 9 - * published by the Free Software Foundation. 10 - * 11 - * This program is distributed in the hope it will be useful, but WITHOUT 12 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 - * for more details. 15 - * 16 - * You should have received a copy of the GNU General Public License along 17 - * with this program; if not, write to the Free Software Foundation, Inc., 18 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 - * 20 - * ######################################################################## 21 - * 22 - * Reset the MIPS boards. 23 - * 24 8 */ 25 - #include <linux/init.h> 9 + #include <linux/io.h> 26 10 #include <linux/pm.h> 27 11 28 - #include <asm/io.h> 29 12 #include <asm/reboot.h> 30 - #include <asm/mips-boards/generic.h> 13 + 14 + #define SOFTRES_REG 0x1f000500 15 + #define GORESET 0x42 31 16 32 17 static void mips_machine_restart(char *command) 33 18 { ··· 30 45 __raw_writel(GORESET, softres_reg); 31 46 } 32 47 33 - 34 48 static int __init mips_reboot_setup(void) 35 49 { 36 50 _machine_restart = mips_machine_restart; ··· 38 54 39 55 return 0; 40 56 } 41 - 42 57 arch_initcall(mips_reboot_setup);

+3 -2

arch/mips/mti-sead3/sead3-reset.c

··· 9 9 #include <linux/pm.h> 10 10 11 11 #include <asm/reboot.h> 12 - #include <asm/mips-boards/generic.h> 12 + 13 + #define SOFTRES_REG 0x1f000050 14 + #define GORESET 0x4d 13 15 14 16 static void mips_machine_restart(char *command) 15 17 { ··· 37 35 38 36 return 0; 39 37 } 40 - 41 38 arch_initcall(mips_reboot_setup);

+11

arch/mips/netlogic/Kconfig

··· 51 51 config NLM_COMMON 52 52 bool 53 53 54 + config IOMMU_HELPER 55 + bool 56 + 57 + config NEED_SG_DMA_LENGTH 58 + bool 59 + 60 + config SWIOTLB 61 + def_bool y 62 + select NEED_SG_DMA_LENGTH 63 + select IOMMU_HELPER 64 + 54 65 endif

+2

arch/mips/netlogic/common/Makefile

··· 1 1 obj-y += irq.o time.o 2 + obj-y += nlm-dma.o 3 + obj-y += reset.o 2 4 obj-$(CONFIG_SMP) += smp.o smpboot.o 3 5 obj-$(CONFIG_EARLY_PRINTK) += earlycons.o

+3 -4

arch/mips/netlogic/common/irq.c

··· 253 253 254 254 node = nlm_nodeid(); 255 255 eirr = read_c0_eirr_and_eimr(); 256 - 257 - i = __ilog2_u64(eirr); 258 - if (i == -1) 256 + if (eirr == 0) 259 257 return; 260 258 259 + i = __ffs64(eirr); 261 260 /* per-CPU IRQs don't need translation */ 262 - if (eirr & PERCPU_IRQ_MASK) { 261 + if (i < PIC_IRQ_BASE) { 263 262 do_IRQ(i); 264 263 return; 265 264 }

+107

arch/mips/netlogic/common/nlm-dma.c

··· 1 + /* 2 + * Copyright (C) 2003-2013 Broadcom Corporation 3 + * All Rights Reserved 4 + * 5 + * This software is available to you under a choice of one of two 6 + * licenses. You may choose to be licensed under the terms of the GNU 7 + * General Public License (GPL) Version 2, available from the file 8 + * COPYING in the main directory of this source tree, or the Broadcom 9 + * license below: 10 + * 11 + * Redistribution and use in source and binary forms, with or without 12 + * modification, are permitted provided that the following conditions 13 + * are met: 14 + * 15 + * 1. Redistributions of source code must retain the above copyright 16 + * notice, this list of conditions and the following disclaimer. 17 + * 2. Redistributions in binary form must reproduce the above copyright 18 + * notice, this list of conditions and the following disclaimer in 19 + * the documentation and/or other materials provided with the 20 + * distribution. 21 + * 22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + #include <linux/dma-mapping.h> 35 + #include <linux/scatterlist.h> 36 + #include <linux/bootmem.h> 37 + #include <linux/export.h> 38 + #include <linux/swiotlb.h> 39 + #include <linux/types.h> 40 + #include <linux/init.h> 41 + #include <linux/mm.h> 42 + 43 + #include <asm/bootinfo.h> 44 + 45 + static char *nlm_swiotlb; 46 + 47 + static void *nlm_dma_alloc_coherent(struct device *dev, size_t size, 48 + dma_addr_t *dma_handle, gfp_t gfp, struct dma_attrs *attrs) 49 + { 50 + void *ret; 51 + 52 + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) 53 + return ret; 54 + 55 + /* ignore region specifiers */ 56 + gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); 57 + 58 + #ifdef CONFIG_ZONE_DMA32 59 + if (dev->coherent_dma_mask <= DMA_BIT_MASK(32)) 60 + gfp |= __GFP_DMA32; 61 + #endif 62 + 63 + /* Don't invoke OOM killer */ 64 + gfp |= __GFP_NORETRY; 65 + 66 + return swiotlb_alloc_coherent(dev, size, dma_handle, gfp); 67 + } 68 + 69 + static void nlm_dma_free_coherent(struct device *dev, size_t size, 70 + void *vaddr, dma_addr_t dma_handle, struct dma_attrs *attrs) 71 + { 72 + int order = get_order(size); 73 + 74 + if (dma_release_from_coherent(dev, order, vaddr)) 75 + return; 76 + 77 + swiotlb_free_coherent(dev, size, vaddr, dma_handle); 78 + } 79 + 80 + struct dma_map_ops nlm_swiotlb_dma_ops = { 81 + .alloc = nlm_dma_alloc_coherent, 82 + .free = nlm_dma_free_coherent, 83 + .map_page = swiotlb_map_page, 84 + .unmap_page = swiotlb_unmap_page, 85 + .map_sg = swiotlb_map_sg_attrs, 86 + .unmap_sg = swiotlb_unmap_sg_attrs, 87 + .sync_single_for_cpu = swiotlb_sync_single_for_cpu, 88 + .sync_single_for_device = swiotlb_sync_single_for_device, 89 + .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu, 90 + .sync_sg_for_device = swiotlb_sync_sg_for_device, 91 + .mapping_error = swiotlb_dma_mapping_error, 92 + .dma_supported = swiotlb_dma_supported 93 + }; 94 + 95 + void __init plat_swiotlb_setup(void) 96 + { 97 + size_t swiotlbsize; 98 + unsigned long swiotlb_nslabs; 99 + 100 + swiotlbsize = 1 << 20; /* 1 MB for now */ 101 + swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; 102 + swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); 103 + swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; 104 + 105 + nlm_swiotlb = alloc_bootmem_low_pages(swiotlbsize); 106 + swiotlb_init_with_tbl(nlm_swiotlb, swiotlb_nslabs, 1); 107 + }

+230

arch/mips/netlogic/common/reset.S

··· 1 + /* 2 + * Copyright 2003-2013 Broadcom Corporation. 3 + * All Rights Reserved. 4 + * 5 + * This software is available to you under a choice of one of two 6 + * licenses. You may choose to be licensed under the terms of the GNU 7 + * General Public License (GPL) Version 2, available from the file 8 + * COPYING in the main directory of this source tree, or the Broadcom 9 + * license below: 10 + * 11 + * Redistribution and use in source and binary forms, with or without 12 + * modification, are permitted provided that the following conditions 13 + * are met: 14 + * 15 + * 1. Redistributions of source code must retain the above copyright 16 + * notice, this list of conditions and the following disclaimer. 17 + * 2. Redistributions in binary form must reproduce the above copyright 18 + * notice, this list of conditions and the following disclaimer in 19 + * the documentation and/or other materials provided with the 20 + * distribution. 21 + * 22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + 35 + #include <linux/init.h> 36 + 37 + #include <asm/asm.h> 38 + #include <asm/asm-offsets.h> 39 + #include <asm/regdef.h> 40 + #include <asm/mipsregs.h> 41 + #include <asm/stackframe.h> 42 + #include <asm/asmmacro.h> 43 + #include <asm/addrspace.h> 44 + 45 + #include <asm/netlogic/common.h> 46 + 47 + #include <asm/netlogic/xlp-hal/iomap.h> 48 + #include <asm/netlogic/xlp-hal/xlp.h> 49 + #include <asm/netlogic/xlp-hal/sys.h> 50 + #include <asm/netlogic/xlp-hal/cpucontrol.h> 51 + 52 + #define CP0_EBASE $15 53 + #define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 54 + XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 55 + SYS_CPU_NONCOHERENT_MODE * 4 56 + 57 + /* Enable XLP features and workarounds in the LSU */ 58 + .macro xlp_config_lsu 59 + li t0, LSU_DEFEATURE 60 + mfcr t1, t0 61 + 62 + lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ 63 + or t1, t1, t2 64 + mtcr t1, t0 65 + 66 + li t0, ICU_DEFEATURE 67 + mfcr t1, t0 68 + ori t1, 0x1000 /* Enable Icache partitioning */ 69 + mtcr t1, t0 70 + 71 + li t0, SCHED_DEFEATURE 72 + lui t1, 0x0100 /* Disable BRU accepting ALU ops */ 73 + mtcr t1, t0 74 + .endm 75 + 76 + /* 77 + * Low level flush for L1D cache on XLP, the normal cache ops does 78 + * not do the complete and correct cache flush. 79 + */ 80 + .macro xlp_flush_l1_dcache 81 + li t0, LSU_DEBUG_DATA0 82 + li t1, LSU_DEBUG_ADDR 83 + li t2, 0 /* index */ 84 + li t3, 0x1000 /* loop count */ 85 + 1: 86 + sll v0, t2, 5 87 + mtcr zero, t0 88 + ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 89 + mtcr v1, t1 90 + 2: 91 + mfcr v1, t1 92 + andi v1, 0x1 /* wait for write_active == 0 */ 93 + bnez v1, 2b 94 + nop 95 + mtcr zero, t0 96 + ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 97 + mtcr v1, t1 98 + 3: 99 + mfcr v1, t1 100 + andi v1, 0x1 /* wait for write_active == 0 */ 101 + bnez v1, 3b 102 + nop 103 + addi t2, 1 104 + bne t3, t2, 1b 105 + nop 106 + .endm 107 + 108 + /* 109 + * nlm_reset_entry will be copied to the reset entry point for 110 + * XLR and XLP. The XLP cores start here when they are woken up. This 111 + * is also the NMI entry point. 112 + * 113 + * We use scratch reg 6/7 to save k0/k1 and check for NMI first. 114 + * 115 + * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS 116 + * location, this will have the thread mask (used when core is woken up) 117 + * and the current NMI handler in case we reached here for an NMI. 118 + * 119 + * When a core or thread is newly woken up, it marks itself ready and 120 + * loops in a 'wait'. When the CPU really needs waking up, we send an NMI 121 + * IPI to it, with the NMI handler set to prom_boot_secondary_cpus 122 + */ 123 + .set noreorder 124 + .set noat 125 + .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ 126 + 127 + FEXPORT(nlm_reset_entry) 128 + dmtc0 k0, $22, 6 129 + dmtc0 k1, $22, 7 130 + mfc0 k0, CP0_STATUS 131 + li k1, 0x80000 132 + and k1, k0, k1 133 + beqz k1, 1f /* go to real reset entry */ 134 + nop 135 + li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 136 + ld k0, BOOT_NMI_HANDLER(k1) 137 + jr k0 138 + nop 139 + 140 + 1: /* Entry point on core wakeup */ 141 + mfc0 t0, CP0_EBASE, 1 142 + mfc0 t1, CP0_EBASE, 1 143 + srl t1, 5 144 + andi t1, 0x3 /* t1 <- node */ 145 + li t2, 0x40000 146 + mul t3, t2, t1 /* t3 = node * 0x40000 */ 147 + srl t0, t0, 2 148 + and t0, t0, 0x7 /* t0 <- core */ 149 + li t1, 0x1 150 + sll t0, t1, t0 151 + nor t0, t0, zero /* t0 <- ~(1 << core) */ 152 + li t2, SYS_CPU_COHERENT_BASE(0) 153 + add t2, t2, t3 /* t2 <- SYS offset for node */ 154 + lw t1, 0(t2) 155 + and t1, t1, t0 156 + sw t1, 0(t2) 157 + 158 + /* read back to ensure complete */ 159 + lw t1, 0(t2) 160 + sync 161 + 162 + /* Configure LSU on Non-0 Cores. */ 163 + xlp_config_lsu 164 + /* FALL THROUGH */ 165 + 166 + /* 167 + * Wake up sibling threads from the initial thread in 168 + * a core. 169 + */ 170 + EXPORT(nlm_boot_siblings) 171 + /* core L1D flush before enable threads */ 172 + xlp_flush_l1_dcache 173 + /* Enable hw threads by writing to MAP_THREADMODE of the core */ 174 + li t0, CKSEG1ADDR(RESET_DATA_PHYS) 175 + lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ 176 + li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) 177 + mfcr t2, t0 178 + or t2, t2, t1 179 + mtcr t2, t0 180 + 181 + /* 182 + * The new hardware thread starts at the next instruction 183 + * For all the cases other than core 0 thread 0, we will 184 + * jump to the secondary wait function. 185 + */ 186 + mfc0 v0, CP0_EBASE, 1 187 + andi v0, 0x3ff /* v0 <- node/core */ 188 + 189 + beqz v0, 4f /* boot cpu (cpuid == 0)? */ 190 + nop 191 + 192 + /* setup status reg */ 193 + move t1, zero 194 + #ifdef CONFIG_64BIT 195 + ori t1, ST0_KX 196 + #endif 197 + mtc0 t1, CP0_STATUS 198 + 199 + /* mark CPU ready, careful here, previous mtcr trashed registers */ 200 + li t3, CKSEG1ADDR(RESET_DATA_PHYS) 201 + ADDIU t1, t3, BOOT_CPU_READY 202 + sll v1, v0, 2 203 + PTR_ADDU t1, v1 204 + li t2, 1 205 + sw t2, 0(t1) 206 + /* Wait until NMI hits */ 207 + 3: wait 208 + b 3b 209 + nop 210 + 211 + /* 212 + * For the boot CPU, we have to restore registers and 213 + * return 214 + */ 215 + 4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ 216 + li t1, 0xfadebeef 217 + dmtc0 t1, $4, 2 /* restore SP from UserLocal */ 218 + PTR_SUBU sp, t0, PT_SIZE 219 + RESTORE_ALL 220 + jr ra 221 + nop 222 + EXPORT(nlm_reset_entry_end) 223 + 224 + LEAF(nlm_init_boot_cpu) 225 + #ifdef CONFIG_CPU_XLP 226 + xlp_config_lsu 227 + #endif 228 + jr ra 229 + nop 230 + END(nlm_init_boot_cpu)

+6 -12

arch/mips/netlogic/common/smp.c

··· 145 145 * Boot all other cpus in the system, initialize them, and bring them into 146 146 * the boot function 147 147 */ 148 - int nlm_cpu_ready[NR_CPUS]; 149 148 unsigned long nlm_next_gp; 150 149 unsigned long nlm_next_sp; 151 150 static cpumask_t phys_cpu_present_mask; ··· 167 168 { 168 169 unsigned int boot_cpu; 169 170 int num_cpus, i, ncore; 171 + volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 170 172 char buf[64]; 171 173 172 174 boot_cpu = hard_smp_processor_id(); ··· 181 181 num_cpus = 1; 182 182 for (i = 0; i < NR_CPUS; i++) { 183 183 /* 184 - * nlm_cpu_ready array is not set for the boot_cpu, 184 + * cpu_ready array is not set for the boot_cpu, 185 185 * it is only set for ASPs (see smpboot.S) 186 186 */ 187 - if (nlm_cpu_ready[i]) { 187 + if (cpu_ready[i]) { 188 188 cpumask_set_cpu(i, &phys_cpu_present_mask); 189 189 __cpu_number_map[i] = num_cpus; 190 190 __cpu_logical_map[num_cpus] = i; ··· 254 254 255 255 int __cpuinit nlm_wakeup_secondary_cpus(void) 256 256 { 257 - unsigned long reset_vec; 258 - char *reset_data; 257 + u32 *reset_data; 259 258 int threadmode; 260 - 261 - /* Update reset entry point with CPU init code */ 262 - reset_vec = CKSEG1ADDR(RESET_VEC_PHYS); 263 - memcpy((void *)reset_vec, (void *)nlm_reset_entry, 264 - (nlm_reset_entry_end - nlm_reset_entry)); 265 259 266 260 /* verify the mask and setup core config variables */ 267 261 threadmode = nlm_parse_cpumask(&nlm_cpumask); 268 262 269 263 /* Setup CPU init parameters */ 270 - reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); 271 - *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode; 264 + reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); 265 + *reset_data = threadmode; 272 266 273 267 #ifdef CONFIG_CPU_XLP 274 268 xlp_wakeup_secondary_cpus();

+5 -189

arch/mips/netlogic/common/smpboot.S

··· 50 50 #include <asm/netlogic/xlp-hal/cpucontrol.h> 51 51 52 52 #define CP0_EBASE $15 53 - #define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 54 - XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 55 - SYS_CPU_NONCOHERENT_MODE * 4 56 - 57 - #define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */ 58 - 59 - /* Enable XLP features and workarounds in the LSU */ 60 - .macro xlp_config_lsu 61 - li t0, LSU_DEFEATURE 62 - mfcr t1, t0 63 - 64 - lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ 65 - or t1, t1, t2 66 - #ifdef XLP_AX_WORKAROUND 67 - li t2, ~0xe /* S1RCM */ 68 - and t1, t1, t2 69 - #endif 70 - mtcr t1, t0 71 - 72 - li t0, ICU_DEFEATURE 73 - mfcr t1, t0 74 - ori t1, 0x1000 /* Enable Icache partitioning */ 75 - mtcr t1, t0 76 - 77 - 78 - #ifdef XLP_AX_WORKAROUND 79 - li t0, SCHED_DEFEATURE 80 - lui t1, 0x0100 /* Disable BRU accepting ALU ops */ 81 - mtcr t1, t0 82 - #endif 83 - .endm 84 - 85 - /* 86 - * This is the code that will be copied to the reset entry point for 87 - * XLR and XLP. The XLP cores start here when they are woken up. This 88 - * is also the NMI entry point. 89 - */ 90 - .macro xlp_flush_l1_dcache 91 - li t0, LSU_DEBUG_DATA0 92 - li t1, LSU_DEBUG_ADDR 93 - li t2, 0 /* index */ 94 - li t3, 0x1000 /* loop count */ 95 - 1: 96 - sll v0, t2, 5 97 - mtcr zero, t0 98 - ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 99 - mtcr v1, t1 100 - 2: 101 - mfcr v1, t1 102 - andi v1, 0x1 /* wait for write_active == 0 */ 103 - bnez v1, 2b 104 - nop 105 - mtcr zero, t0 106 - ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 107 - mtcr v1, t1 108 - 3: 109 - mfcr v1, t1 110 - andi v1, 0x1 /* wait for write_active == 0 */ 111 - bnez v1, 3b 112 - nop 113 - addi t2, 1 114 - bne t3, t2, 1b 115 - nop 116 - .endm 117 - 118 - /* 119 - * The cores can come start when they are woken up. This is also the NMI 120 - * entry, so check that first. 121 - * 122 - * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS 123 - * location, this will have the thread mask (used when core is woken up) 124 - * and the current NMI handler in case we reached here for an NMI. 125 - * 126 - * When a core or thread is newly woken up, it loops in a 'wait'. When 127 - * the CPU really needs waking up, we send an NMI to it, with the NMI 128 - * handler set to prom_boot_secondary_cpus 129 - */ 130 53 131 54 .set noreorder 132 55 .set noat 133 - .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ 134 - 135 - FEXPORT(nlm_reset_entry) 136 - dmtc0 k0, $22, 6 137 - dmtc0 k1, $22, 7 138 - mfc0 k0, CP0_STATUS 139 - li k1, 0x80000 140 - and k1, k0, k1 141 - beqz k1, 1f /* go to real reset entry */ 142 - nop 143 - li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 144 - ld k0, BOOT_NMI_HANDLER(k1) 145 - jr k0 146 - nop 147 - 148 - 1: /* Entry point on core wakeup */ 149 - mfc0 t0, CP0_EBASE, 1 150 - mfc0 t1, CP0_EBASE, 1 151 - srl t1, 5 152 - andi t1, 0x3 /* t1 <- node */ 153 - li t2, 0x40000 154 - mul t3, t2, t1 /* t3 = node * 0x40000 */ 155 - srl t0, t0, 2 156 - and t0, t0, 0x7 /* t0 <- core */ 157 - li t1, 0x1 158 - sll t0, t1, t0 159 - nor t0, t0, zero /* t0 <- ~(1 << core) */ 160 - li t2, SYS_CPU_COHERENT_BASE(0) 161 - add t2, t2, t3 /* t2 <- SYS offset for node */ 162 - lw t1, 0(t2) 163 - and t1, t1, t0 164 - sw t1, 0(t2) 165 - 166 - /* read back to ensure complete */ 167 - lw t1, 0(t2) 168 - sync 169 - 170 - /* Configure LSU on Non-0 Cores. */ 171 - xlp_config_lsu 172 - /* FALL THROUGH */ 173 - 174 - /* 175 - * Wake up sibling threads from the initial thread in 176 - * a core. 177 - */ 178 - EXPORT(nlm_boot_siblings) 179 - /* core L1D flush before enable threads */ 180 - xlp_flush_l1_dcache 181 - /* Enable hw threads by writing to MAP_THREADMODE of the core */ 182 - li t0, CKSEG1ADDR(RESET_DATA_PHYS) 183 - lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ 184 - li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) 185 - mfcr t2, t0 186 - or t2, t2, t1 187 - mtcr t2, t0 188 - 189 - /* 190 - * The new hardware thread starts at the next instruction 191 - * For all the cases other than core 0 thread 0, we will 192 - * jump to the secondary wait function. 193 - */ 194 - mfc0 v0, CP0_EBASE, 1 195 - andi v0, 0x3ff /* v0 <- node/core */ 196 - 197 - /* Init MMU in the first thread after changing THREAD_MODE 198 - * register (Ax Errata?) 199 - */ 200 - andi v1, v0, 0x3 /* v1 <- thread id */ 201 - bnez v1, 2f 202 - nop 203 - 204 - li t0, MMU_SETUP 205 - li t1, 0 206 - mtcr t1, t0 207 - _ehb 208 - 209 - 2: beqz v0, 4f /* boot cpu (cpuid == 0)? */ 210 - nop 211 - 212 - /* setup status reg */ 213 - move t1, zero 214 - #ifdef CONFIG_64BIT 215 - ori t1, ST0_KX 216 - #endif 217 - mtc0 t1, CP0_STATUS 218 - /* mark CPU ready */ 219 - PTR_LA t1, nlm_cpu_ready 220 - sll v1, v0, 2 221 - PTR_ADDU t1, v1 222 - li t2, 1 223 - sw t2, 0(t1) 224 - /* Wait until NMI hits */ 225 - 3: wait 226 - j 3b 227 - nop 228 - 229 - /* 230 - * For the boot CPU, we have to restore registers and 231 - * return 232 - */ 233 - 4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ 234 - li t1, 0xfadebeef 235 - dmtc0 t1, $4, 2 /* restore SP from UserLocal */ 236 - PTR_SUBU sp, t0, PT_SIZE 237 - RESTORE_ALL 238 - jr ra 239 - nop 240 - EXPORT(nlm_reset_entry_end) 56 + .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */ 241 57 242 58 FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 243 - xlp_config_lsu 244 59 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 245 60 SAVE_ALL 246 61 sync ··· 109 294 andi t2, t0, 0x3 /* thread num */ 110 295 sll t0, 2 /* offset in cpu array */ 111 296 112 - PTR_LA t1, nlm_cpu_ready /* mark CPU ready */ 113 - PTR_ADDU t1, t0 297 + li t3, CKSEG1ADDR(RESET_DATA_PHYS) 298 + ADDIU t1, t3, BOOT_CPU_READY 299 + ADDU t1, t0 114 300 li t3, 1 115 301 sw t3, 0(t1) 116 302 ··· 137 321 mtcr t1, t0 /* update core control */ 138 322 139 323 1: wait 140 - j 1b 324 + b 1b 141 325 nop 142 326 END(nlm_rmiboot_preboot) 143 327 __FINIT

+1 -1

arch/mips/netlogic/xlp/Makefile

··· 1 - obj-y += setup.o nlm_hal.o 1 + obj-y += setup.o nlm_hal.o cop2-ex.o dt.o 2 2 obj-$(CONFIG_SMP) += wakeup.o 3 3 obj-$(CONFIG_USB) += usb-init.o

+118

arch/mips/netlogic/xlp/cop2-ex.c

··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2013 Broadcom Corporation. 7 + * 8 + * based on arch/mips/cavium-octeon/cpu.c 9 + * Copyright (C) 2009 Wind River Systems, 10 + * written by Ralf Baechle <ralf@linux-mips.org> 11 + */ 12 + #include <linux/init.h> 13 + #include <linux/irqflags.h> 14 + #include <linux/notifier.h> 15 + #include <linux/prefetch.h> 16 + #include <linux/sched.h> 17 + 18 + #include <asm/cop2.h> 19 + #include <asm/current.h> 20 + #include <asm/mipsregs.h> 21 + #include <asm/page.h> 22 + 23 + #include <asm/netlogic/mips-extns.h> 24 + 25 + /* 26 + * 64 bit ops are done in inline assembly to support 32 bit 27 + * compilation 28 + */ 29 + void nlm_cop2_save(struct nlm_cop2_state *r) 30 + { 31 + asm volatile( 32 + ".set push\n" 33 + ".set noat\n" 34 + "dmfc2 $1, $0, 0\n" 35 + "sd $1, 0(%1)\n" 36 + "dmfc2 $1, $0, 1\n" 37 + "sd $1, 8(%1)\n" 38 + "dmfc2 $1, $0, 2\n" 39 + "sd $1, 16(%1)\n" 40 + "dmfc2 $1, $0, 3\n" 41 + "sd $1, 24(%1)\n" 42 + "dmfc2 $1, $1, 0\n" 43 + "sd $1, 0(%2)\n" 44 + "dmfc2 $1, $1, 1\n" 45 + "sd $1, 8(%2)\n" 46 + "dmfc2 $1, $1, 2\n" 47 + "sd $1, 16(%2)\n" 48 + "dmfc2 $1, $1, 3\n" 49 + "sd $1, 24(%2)\n" 50 + ".set pop\n" 51 + : "=m"(*r) 52 + : "r"(r->tx), "r"(r->rx)); 53 + 54 + r->tx_msg_status = __read_32bit_c2_register($2, 0); 55 + r->rx_msg_status = __read_32bit_c2_register($3, 0) & 0x0fffffff; 56 + } 57 + 58 + void nlm_cop2_restore(struct nlm_cop2_state *r) 59 + { 60 + u32 rstat; 61 + 62 + asm volatile( 63 + ".set push\n" 64 + ".set noat\n" 65 + "ld $1, 0(%1)\n" 66 + "dmtc2 $1, $0, 0\n" 67 + "ld $1, 8(%1)\n" 68 + "dmtc2 $1, $0, 1\n" 69 + "ld $1, 16(%1)\n" 70 + "dmtc2 $1, $0, 2\n" 71 + "ld $1, 24(%1)\n" 72 + "dmtc2 $1, $0, 3\n" 73 + "ld $1, 0(%2)\n" 74 + "dmtc2 $1, $1, 0\n" 75 + "ld $1, 8(%2)\n" 76 + "dmtc2 $1, $1, 1\n" 77 + "ld $1, 16(%2)\n" 78 + "dmtc2 $1, $1, 2\n" 79 + "ld $1, 24(%2)\n" 80 + "dmtc2 $1, $1, 3\n" 81 + ".set pop\n" 82 + : : "m"(*r), "r"(r->tx), "r"(r->rx)); 83 + 84 + __write_32bit_c2_register($2, 0, r->tx_msg_status); 85 + rstat = __read_32bit_c2_register($3, 0) & 0xf0000000u; 86 + __write_32bit_c2_register($3, 0, r->rx_msg_status | rstat); 87 + } 88 + 89 + static int nlm_cu2_call(struct notifier_block *nfb, unsigned long action, 90 + void *data) 91 + { 92 + unsigned long flags; 93 + unsigned int status; 94 + 95 + switch (action) { 96 + case CU2_EXCEPTION: 97 + if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 98 + break; 99 + local_irq_save(flags); 100 + KSTK_STATUS(current) |= ST0_CU2; 101 + status = read_c0_status(); 102 + write_c0_status(status | ST0_CU2); 103 + nlm_cop2_restore(&(current->thread.cp2)); 104 + write_c0_status(status & ~ST0_CU2); 105 + local_irq_restore(flags); 106 + pr_info("COP2 access enabled for pid %d (%s)\n", 107 + current->pid, current->comm); 108 + return NOTIFY_BAD; /* Don't call default notifier */ 109 + } 110 + 111 + return NOTIFY_OK; /* Let default notifier send signals */ 112 + } 113 + 114 + static int __init nlm_cu2_setup(void) 115 + { 116 + return cu2_notifier(nlm_cu2_call, 0); 117 + } 118 + early_initcall(nlm_cu2_setup);

+99

arch/mips/netlogic/xlp/dt.c

··· 1 + /* 2 + * Copyright 2003-2013 Broadcom Corporation. 3 + * All Rights Reserved. 4 + * 5 + * This software is available to you under a choice of one of two 6 + * licenses. You may choose to be licensed under the terms of the GNU 7 + * General Public License (GPL) Version 2, available from the file 8 + * COPYING in the main directory of this source tree, or the Broadcom 9 + * license below: 10 + * 11 + * Redistribution and use in source and binary forms, with or without 12 + * modification, are permitted provided that the following conditions 13 + * are met: 14 + * 15 + * 1. Redistributions of source code must retain the above copyright 16 + * notice, this list of conditions and the following disclaimer. 17 + * 2. Redistributions in binary form must reproduce the above copyright 18 + * notice, this list of conditions and the following disclaimer in 19 + * the documentation and/or other materials provided with the 20 + * distribution. 21 + * 22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + 35 + #include <linux/kernel.h> 36 + #include <linux/bootmem.h> 37 + 38 + #include <linux/of_fdt.h> 39 + #include <linux/of_platform.h> 40 + #include <linux/of_device.h> 41 + 42 + extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; 43 + 44 + void __init *xlp_dt_init(void *fdtp) 45 + { 46 + if (!fdtp) { 47 + switch (current_cpu_data.processor_id & 0xff00) { 48 + #ifdef CONFIG_DT_XLP_SVP 49 + case PRID_IMP_NETLOGIC_XLP3XX: 50 + fdtp = __dtb_xlp_svp_begin; 51 + break; 52 + #endif 53 + #ifdef CONFIG_DT_XLP_EVP 54 + case PRID_IMP_NETLOGIC_XLP8XX: 55 + fdtp = __dtb_xlp_evp_begin; 56 + break; 57 + #endif 58 + default: 59 + /* Pick a built-in if any, and hope for the best */ 60 + fdtp = __dtb_start; 61 + break; 62 + } 63 + } 64 + initial_boot_params = fdtp; 65 + return fdtp; 66 + } 67 + 68 + void __init device_tree_init(void) 69 + { 70 + unsigned long base, size; 71 + 72 + if (!initial_boot_params) 73 + return; 74 + 75 + base = virt_to_phys((void *)initial_boot_params); 76 + size = be32_to_cpu(initial_boot_params->totalsize); 77 + 78 + /* Before we do anything, lets reserve the dt blob */ 79 + reserve_bootmem(base, size, BOOTMEM_DEFAULT); 80 + 81 + unflatten_device_tree(); 82 + 83 + /* free the space reserved for the dt blob */ 84 + free_bootmem(base, size); 85 + } 86 + 87 + static struct of_device_id __initdata xlp_ids[] = { 88 + { .compatible = "simple-bus", }, 89 + {}, 90 + }; 91 + 92 + int __init xlp8xx_ds_publish_devices(void) 93 + { 94 + if (!of_have_populated_dt()) 95 + return 0; 96 + return of_platform_bus_probe(NULL, xlp_ids, NULL); 97 + } 98 + 99 + device_initcall(xlp8xx_ds_publish_devices);

+26 -69

arch/mips/netlogic/xlp/setup.c

··· 33 33 */ 34 34 35 35 #include <linux/kernel.h> 36 - #include <linux/serial_8250.h> 37 - #include <linux/pm.h> 38 - #include <linux/bootmem.h> 36 + #include <linux/of_fdt.h> 39 37 40 38 #include <asm/idle.h> 41 39 #include <asm/reboot.h> 42 40 #include <asm/time.h> 43 41 #include <asm/bootinfo.h> 44 - 45 - #include <linux/of_fdt.h> 46 - #include <linux/of_platform.h> 47 - #include <linux/of_device.h> 48 42 49 43 #include <asm/netlogic/haldefs.h> 50 44 #include <asm/netlogic/common.h> ··· 51 57 struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 52 58 cpumask_t nlm_cpumask = CPU_MASK_CPU0; 53 59 unsigned int nlm_threads_per_core; 54 - extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], __dtb_start[]; 55 60 56 61 static void nlm_linux_exit(void) 57 62 { ··· 61 68 cpu_wait(); 62 69 } 63 70 71 + static void nlm_fixup_mem(void) 72 + { 73 + const int pref_backup = 512; 74 + int i; 75 + 76 + for (i = 0; i < boot_mem_map.nr_map; i++) { 77 + if (boot_mem_map.map[i].type != BOOT_MEM_RAM) 78 + continue; 79 + boot_mem_map.map[i].size -= pref_backup; 80 + } 81 + } 82 + 64 83 void __init plat_mem_setup(void) 65 84 { 66 - void *fdtp; 67 - 68 85 panic_timeout = 5; 69 86 _machine_restart = (void (*)(char *))nlm_linux_exit; 70 87 _machine_halt = nlm_linux_exit; 71 88 pm_power_off = nlm_linux_exit; 72 89 73 - /* 74 - * If no FDT pointer is passed in, use the built-in FDT. 75 - * device_tree_init() does not handle CKSEG0 pointers in 76 - * 64-bit, so convert pointer. 77 - */ 78 - fdtp = (void *)(long)fw_arg0; 79 - if (!fdtp) { 80 - switch (current_cpu_data.processor_id & 0xff00) { 81 - #ifdef CONFIG_DT_XLP_SVP 82 - case PRID_IMP_NETLOGIC_XLP3XX: 83 - fdtp = __dtb_xlp_svp_begin; 84 - break; 85 - #endif 86 - #ifdef CONFIG_DT_XLP_EVP 87 - case PRID_IMP_NETLOGIC_XLP8XX: 88 - fdtp = __dtb_xlp_evp_begin; 89 - break; 90 - #endif 91 - default: 92 - /* Pick a built-in if any, and hope for the best */ 93 - fdtp = __dtb_start; 94 - break; 95 - } 96 - } 97 - fdtp = phys_to_virt(__pa(fdtp)); 98 - early_init_devtree(fdtp); 90 + /* memory and bootargs from DT */ 91 + early_init_devtree(initial_boot_params); 92 + nlm_fixup_mem(); 99 93 } 100 94 101 95 const char *get_system_type(void) ··· 111 131 112 132 void __init prom_init(void) 113 133 { 134 + void *reset_vec; 135 + 114 136 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 137 + nlm_init_boot_cpu(); 115 138 xlp_mmu_init(); 116 139 nlm_node_init(0); 140 + xlp_dt_init((void *)(long)fw_arg0); 141 + 142 + /* Update reset entry point with CPU init code */ 143 + reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); 144 + memset(reset_vec, 0, RESET_VEC_SIZE); 145 + memcpy(reset_vec, (void *)nlm_reset_entry, 146 + (nlm_reset_entry_end - nlm_reset_entry)); 117 147 118 148 #ifdef CONFIG_SMP 119 149 cpumask_setall(&nlm_cpumask); ··· 135 145 register_smp_ops(&nlm_smp_ops); 136 146 #endif 137 147 } 138 - 139 - void __init device_tree_init(void) 140 - { 141 - unsigned long base, size; 142 - 143 - if (!initial_boot_params) 144 - return; 145 - 146 - base = virt_to_phys((void *)initial_boot_params); 147 - size = be32_to_cpu(initial_boot_params->totalsize); 148 - 149 - /* Before we do anything, lets reserve the dt blob */ 150 - reserve_bootmem(base, size, BOOTMEM_DEFAULT); 151 - 152 - unflatten_device_tree(); 153 - 154 - /* free the space reserved for the dt blob */ 155 - free_bootmem(base, size); 156 - } 157 - 158 - static struct of_device_id __initdata xlp_ids[] = { 159 - { .compatible = "simple-bus", }, 160 - {}, 161 - }; 162 - 163 - int __init xlp8xx_ds_publish_devices(void) 164 - { 165 - if (!of_have_populated_dt()) 166 - return 0; 167 - return of_platform_bus_probe(NULL, xlp_ids, NULL); 168 - } 169 - 170 - device_initcall(xlp8xx_ds_publish_devices);

+20 -6

arch/mips/netlogic/xlp/wakeup.c

··· 77 77 return count != 0; 78 78 } 79 79 80 + static int wait_for_cpus(int cpu, int bootcpu) 81 + { 82 + volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 83 + int i, count, notready; 84 + 85 + count = 0x20000000; 86 + do { 87 + notready = nlm_threads_per_core; 88 + for (i = 0; i < nlm_threads_per_core; i++) 89 + if (cpu_ready[cpu + i] || cpu == bootcpu) 90 + --notready; 91 + } while (notready != 0 && --count > 0); 92 + 93 + return count != 0; 94 + } 95 + 80 96 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 81 97 { 82 98 struct nlm_soc_info *nodep; 83 99 uint64_t syspcibase; 84 100 uint32_t syscoremask; 85 - int core, n, cpu, count, val; 101 + int core, n, cpu; 86 102 87 103 for (n = 0; n < NLM_NR_NODES; n++) { 88 104 syspcibase = nlm_get_sys_pcibase(n); ··· 138 122 /* core is up */ 139 123 nodep->coremask |= 1u << core; 140 124 141 - /* spin until the first hw thread sets its ready */ 142 - count = 0x20000000; 143 - do { 144 - val = *(volatile int *)&nlm_cpu_ready[cpu]; 145 - } while (val == 0 && --count > 0); 125 + /* spin until the hw threads sets their ready */ 126 + wait_for_cpus(cpu, 0); 146 127 } 147 128 } 148 129 } ··· 151 138 * first wakeup core 0 threads 152 139 */ 153 140 xlp_boot_core0_siblings(); 141 + wait_for_cpus(0, 0); 154 142 155 143 /* now get other cores out of reset */ 156 144 xlp_enable_secondary_cores(&nlm_cpumask);

+9 -9

arch/mips/netlogic/xlr/fmn.c

··· 74 74 struct nlm_fmn_msg msg; 75 75 uint32_t mflags, bkt_status; 76 76 77 - mflags = nlm_cop2_enable(); 77 + mflags = nlm_cop2_enable_irqsave(); 78 78 /* Disable message ring interrupt */ 79 79 nlm_fmn_setup_intr(irq, 0); 80 80 while (1) { 81 81 /* 8 bkts per core, [24:31] each bit represents one bucket 82 82 * Bit is Zero if bucket is not empty */ 83 - bkt_status = (nlm_read_c2_status() >> 24) & 0xff; 83 + bkt_status = (nlm_read_c2_status0() >> 24) & 0xff; 84 84 if (bkt_status == 0xff) 85 85 break; 86 86 for (bucket = 0; bucket < 8; bucket++) { ··· 97 97 pr_warn("No msgring handler for stnid %d\n", 98 98 src_stnid); 99 99 else { 100 - nlm_cop2_restore(mflags); 100 + nlm_cop2_disable_irqrestore(mflags); 101 101 hndlr->action(bucket, src_stnid, size, code, 102 102 &msg, hndlr->arg); 103 - mflags = nlm_cop2_enable(); 103 + mflags = nlm_cop2_enable_irqsave(); 104 104 } 105 105 } 106 106 }; 107 107 /* Enable message ring intr, to any thread in core */ 108 108 nlm_fmn_setup_intr(irq, (1 << nlm_threads_per_core) - 1); 109 - nlm_cop2_restore(mflags); 109 + nlm_cop2_disable_irqrestore(mflags); 110 110 return IRQ_HANDLED; 111 111 } 112 112 ··· 128 128 129 129 bucket_sizes = xlr_board_fmn_config.bucket_size; 130 130 cpu_fmn_info = &xlr_board_fmn_config.cpu[id]; 131 - flags = nlm_cop2_enable(); 131 + flags = nlm_cop2_enable_irqsave(); 132 132 133 133 /* Setup bucket sizes for the core. */ 134 134 nlm_write_c2_bucksize(0, bucket_sizes[id * 8 + 0]); ··· 166 166 167 167 /* enable FMN interrupts on this CPU */ 168 168 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); 169 - nlm_cop2_restore(flags); 169 + nlm_cop2_disable_irqrestore(flags); 170 170 } 171 171 172 172 ··· 198 198 /* setup irq only once */ 199 199 setup_irq(IRQ_FMN, &fmn_irqaction); 200 200 201 - flags = nlm_cop2_enable(); 201 + flags = nlm_cop2_enable_irqsave(); 202 202 nlm_fmn_setup_intr(IRQ_FMN, (1 << nlm_threads_per_core) - 1); 203 - nlm_cop2_restore(flags); 203 + nlm_cop2_disable_irqrestore(flags); 204 204 }

+7

arch/mips/netlogic/xlr/setup.c

··· 196 196 { 197 197 int *argv, *envp; /* passed as 32 bit ptrs */ 198 198 struct psb_info *prom_infop; 199 + void *reset_vec; 199 200 #ifdef CONFIG_SMP 200 201 int i; 201 202 #endif ··· 208 207 209 208 nlm_prom_info = *prom_infop; 210 209 nlm_init_node(); 210 + 211 + /* Update reset entry point with CPU init code */ 212 + reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); 213 + memset(reset_vec, 0, RESET_VEC_SIZE); 214 + memcpy(reset_vec, (void *)nlm_reset_entry, 215 + (nlm_reset_entry_end - nlm_reset_entry)); 211 216 212 217 nlm_early_serial_setup(); 213 218 build_arcs_cmdline(argv);

+2 -1

arch/mips/netlogic/xlr/wakeup.c

··· 53 53 { 54 54 struct nlm_soc_info *nodep; 55 55 unsigned int i, j, boot_cpu; 56 + volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 56 57 57 58 /* 58 59 * In case of RMI boot, hit with NMI to get the cores ··· 72 71 nodep->coremask = 1; 73 72 for (i = 1; i < NLM_CORES_PER_NODE; i++) { 74 73 for (j = 1000000; j > 0; j--) { 75 - if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE]) 74 + if (cpu_ready[i * NLM_THREADS_PER_CORE]) 76 75 break; 77 76 udelay(10); 78 77 }

+3 -4

arch/mips/pci/Makefile

··· 29 29 obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 30 30 obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o 31 31 obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o 32 - obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32 + obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o 33 33 obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 34 34 obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 35 35 obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o ··· 52 52 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o 53 53 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 54 54 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 55 - obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 56 55 obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 57 - obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 56 + obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o 58 57 obj-$(CONFIG_CPU_XLR) += pci-xlr.o 59 58 obj-$(CONFIG_CPU_XLP) += pci-xlp.o 60 59 61 60 ifdef CONFIG_PCI_MSI 62 - obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 61 + obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o 63 62 endif

-37

arch/mips/pci/fixup-wrppmc.c

··· 1 - /* 2 - * fixup-wrppmc.c: PPMC board specific PCI fixup 3 - * 4 - * This file is subject to the terms and conditions of the GNU General Public 5 - * License. See the file "COPYING" in the main directory of this archive 6 - * for more details. 7 - * 8 - * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com) 9 - */ 10 - #include <linux/init.h> 11 - #include <linux/pci.h> 12 - #include <asm/gt64120.h> 13 - 14 - /* PCI interrupt pins */ 15 - #define PCI_INTA 1 16 - #define PCI_INTB 2 17 - #define PCI_INTC 3 18 - #define PCI_INTD 4 19 - 20 - #define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */ 21 - 22 - static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { 23 - /* 0 INTA INTB INTC INTD */ 24 - [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */ 25 - [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, 26 - }; 27 - 28 - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 29 - { 30 - return pci_irq_tab[slot][pin]; 31 - } 32 - 33 - /* Do platform specific device initialization at pci_enable_device() time */ 34 - int pcibios_plat_dev_init(struct pci_dev *dev) 35 - { 36 - return 0; 37 - }

+2 -1

arch/mips/pci/pci-bcm63xx.c

··· 266 266 /* setup PCI to local bus access, used by PCI device to target 267 267 * local RAM while bus mastering */ 268 268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 269 - if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) 269 + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) 270 270 val = MPI_SP0_REMAP_ENABLE_MASK; 271 271 else 272 272 val = 0; ··· 338 338 case BCM6328_CPU_ID: 339 339 case BCM6362_CPU_ID: 340 340 return bcm63xx_register_pcie(); 341 + case BCM3368_CPU_ID: 341 342 case BCM6348_CPU_ID: 342 343 case BCM6358_CPU_ID: 343 344 case BCM6368_CPU_ID:

+2

arch/mips/pci/pci-ip27.c

··· 217 217 pci_disable_swapping(d); 218 218 } 219 219 220 + #ifdef CONFIG_NUMA 220 221 int pcibus_to_node(struct pci_bus *bus) 221 222 { 222 223 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); ··· 225 224 return bc->nasid; 226 225 } 227 226 EXPORT_SYMBOL(pcibus_to_node); 227 + #endif /* CONFIG_NUMA */ 228 228 229 229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 230 230 pci_fixup_ioc3);

-1

arch/mips/pmcs-msp71xx/Makefile

··· 3 3 # 4 4 obj-y += msp_prom.o msp_setup.o msp_irq.o \ 5 5 msp_time.o msp_serial.o msp_elb.o 6 - obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o 7 6 obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o 8 7 obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o 9 8 obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o

-216

arch/mips/pmcs-msp71xx/gpio.c

··· 1 - /* 2 - * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two 3 - * types of registers. The data register sets the output level when in output 4 - * mode and when in input mode will contain the value at the input. The config 5 - * register sets the various modes for each gpio. 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License version 2 as 9 - * published by the Free Software Foundation. 10 - * 11 - * @author Patrick Glass <patrickglass@gmail.com> 12 - */ 13 - 14 - #include <linux/kernel.h> 15 - #include <linux/module.h> 16 - #include <linux/init.h> 17 - #include <linux/gpio.h> 18 - #include <linux/spinlock.h> 19 - #include <linux/io.h> 20 - 21 - #define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio)) 22 - #define CONF_MASK 0x0F 23 - #define MSP71XX_GPIO_INPUT 0x01 24 - #define MSP71XX_GPIO_OUTPUT 0x08 25 - 26 - #define MSP71XX_GPIO_BASE 0x0B8400000L 27 - 28 - #define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip) 29 - 30 - static spinlock_t gpio_lock; 31 - 32 - /* 33 - * struct msp71xx_gpio_chip - container for gpio chip and registers 34 - * @chip: chip structure for the specified gpio bank 35 - * @data_reg: register for reading and writing the gpio pin value 36 - * @config_reg: register to set the mode for the gpio pin bank 37 - * @out_drive_reg: register to set the output drive mode for the gpio pin bank 38 - */ 39 - struct msp71xx_gpio_chip { 40 - struct gpio_chip chip; 41 - void __iomem *data_reg; 42 - void __iomem *config_reg; 43 - void __iomem *out_drive_reg; 44 - }; 45 - 46 - /* 47 - * msp71xx_gpio_get() - return the chip's gpio value 48 - * @chip: chip structure which controls the specified gpio 49 - * @offset: gpio whose value will be returned 50 - * 51 - * It will return 0 if gpio value is low and other if high. 52 - */ 53 - static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset) 54 - { 55 - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); 56 - 57 - return __raw_readl(msp_chip->data_reg) & (1 << offset); 58 - } 59 - 60 - /* 61 - * msp71xx_gpio_set() - set the output value for the gpio 62 - * @chip: chip structure who controls the specified gpio 63 - * @offset: gpio whose value will be assigned 64 - * @value: logic level to assign to the gpio initially 65 - * 66 - * This will set the gpio bit specified to the desired value. It will set the 67 - * gpio pin low if value is 0 otherwise it will be high. 68 - */ 69 - static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 70 - { 71 - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); 72 - unsigned long flags; 73 - u32 data; 74 - 75 - spin_lock_irqsave(&gpio_lock, flags); 76 - 77 - data = __raw_readl(msp_chip->data_reg); 78 - if (value) 79 - data |= (1 << offset); 80 - else 81 - data &= ~(1 << offset); 82 - __raw_writel(data, msp_chip->data_reg); 83 - 84 - spin_unlock_irqrestore(&gpio_lock, flags); 85 - } 86 - 87 - /* 88 - * msp71xx_set_gpio_mode() - declare the mode for a gpio 89 - * @chip: chip structure which controls the specified gpio 90 - * @offset: gpio whose value will be assigned 91 - * @mode: desired configuration for the gpio (see datasheet) 92 - * 93 - * It will set the gpio pin config to the @mode value passed in. 94 - */ 95 - static int msp71xx_set_gpio_mode(struct gpio_chip *chip, 96 - unsigned offset, int mode) 97 - { 98 - struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip); 99 - const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset); 100 - unsigned long flags; 101 - u32 cfg; 102 - 103 - spin_lock_irqsave(&gpio_lock, flags); 104 - 105 - cfg = __raw_readl(msp_chip->config_reg); 106 - cfg &= ~(CONF_MASK << bit_offset); 107 - cfg |= (mode << bit_offset); 108 - __raw_writel(cfg, msp_chip->config_reg); 109 - 110 - spin_unlock_irqrestore(&gpio_lock, flags); 111 - 112 - return 0; 113 - } 114 - 115 - /* 116 - * msp71xx_direction_output() - declare the direction mode for a gpio 117 - * @chip: chip structure which controls the specified gpio 118 - * @offset: gpio whose value will be assigned 119 - * @value: logic level to assign to the gpio initially 120 - * 121 - * This call will set the mode for the @gpio to output. It will set the 122 - * gpio pin low if value is 0 otherwise it will be high. 123 - */ 124 - static int msp71xx_direction_output(struct gpio_chip *chip, 125 - unsigned offset, int value) 126 - { 127 - msp71xx_gpio_set(chip, offset, value); 128 - 129 - return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT); 130 - } 131 - 132 - /* 133 - * msp71xx_direction_input() - declare the direction mode for a gpio 134 - * @chip: chip structure which controls the specified gpio 135 - * @offset: gpio whose to which the value will be assigned 136 - * 137 - * This call will set the mode for the @gpio to input. 138 - */ 139 - static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset) 140 - { 141 - return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT); 142 - } 143 - 144 - /* 145 - * msp71xx_set_output_drive() - declare the output drive for the gpio line 146 - * @gpio: gpio pin whose output drive you wish to modify 147 - * @value: zero for active drain 1 for open drain drive 148 - * 149 - * This call will set the output drive mode for the @gpio to output. 150 - */ 151 - int msp71xx_set_output_drive(unsigned gpio, int value) 152 - { 153 - unsigned long flags; 154 - u32 data; 155 - 156 - if (gpio > 15 || gpio < 0) 157 - return -EINVAL; 158 - 159 - spin_lock_irqsave(&gpio_lock, flags); 160 - 161 - data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); 162 - if (value) 163 - data |= (1 << gpio); 164 - else 165 - data &= ~(1 << gpio); 166 - __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190)); 167 - 168 - spin_unlock_irqrestore(&gpio_lock, flags); 169 - 170 - return 0; 171 - } 172 - EXPORT_SYMBOL(msp71xx_set_output_drive); 173 - 174 - #define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \ 175 - { \ 176 - .chip = { \ 177 - .label = name, \ 178 - .direction_input = msp71xx_direction_input, \ 179 - .direction_output = msp71xx_direction_output, \ 180 - .get = msp71xx_gpio_get, \ 181 - .set = msp71xx_gpio_set, \ 182 - .base = base_gpio, \ 183 - .ngpio = num_gpio \ 184 - }, \ 185 - .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \ 186 - .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \ 187 - .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \ 188 - } 189 - 190 - /* 191 - * struct msp71xx_gpio_banks[] - container array of gpio banks 192 - * @chip: chip structure for the specified gpio bank 193 - * @data_reg: register for reading and writing the gpio pin value 194 - * @config_reg: register to set the mode for the gpio pin bank 195 - * 196 - * This array structure defines the gpio banks for the PMC MIPS Processor. 197 - * We specify the bank name, the data register, the config register, base 198 - * starting gpio number, and the number of gpios exposed by the bank. 199 - */ 200 - static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = { 201 - 202 - MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2), 203 - MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4), 204 - MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4), 205 - MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6), 206 - }; 207 - 208 - void __init msp71xx_init_gpio(void) 209 - { 210 - int i; 211 - 212 - spin_lock_init(&gpio_lock); 213 - 214 - for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++) 215 - gpiochip_add(&msp71xx_gpio_banks[i].chip); 216 - }

-146

arch/mips/pmcs-msp71xx/gpio_extended.c

··· 1 - /* 2 - * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is 3 - * a set of hardware registers that have no need for explicit locking as 4 - * it is handled by unique method of writing individual set/clr bits. 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License version 2 as 8 - * published by the Free Software Foundation. 9 - * 10 - * @author Patrick Glass <patrickglass@gmail.com> 11 - */ 12 - 13 - #include <linux/kernel.h> 14 - #include <linux/module.h> 15 - #include <linux/init.h> 16 - #include <linux/gpio.h> 17 - #include <linux/io.h> 18 - 19 - #define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio)) 20 - #define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1) 21 - #define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16) 22 - #define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1) 23 - 24 - #define MSP71XX_EXD_GPIO_BASE 0x0BC000000L 25 - 26 - #define to_msp71xx_exd_gpio_chip(c) \ 27 - container_of(c, struct msp71xx_exd_gpio_chip, chip) 28 - 29 - /* 30 - * struct msp71xx_exd_gpio_chip - container for gpio chip and registers 31 - * @chip: chip structure for the specified gpio bank 32 - * @reg: register for control and data of gpio pin 33 - */ 34 - struct msp71xx_exd_gpio_chip { 35 - struct gpio_chip chip; 36 - void __iomem *reg; 37 - }; 38 - 39 - /* 40 - * msp71xx_exd_gpio_get() - return the chip's gpio value 41 - * @chip: chip structure which controls the specified gpio 42 - * @offset: gpio whose value will be returned 43 - * 44 - * It will return 0 if gpio value is low and other if high. 45 - */ 46 - static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset) 47 - { 48 - struct msp71xx_exd_gpio_chip *msp71xx_chip = 49 - to_msp71xx_exd_gpio_chip(chip); 50 - const unsigned bit = MSP71XX_READ_OFFSET(offset); 51 - 52 - return __raw_readl(msp71xx_chip->reg) & (1 << bit); 53 - } 54 - 55 - /* 56 - * msp71xx_exd_gpio_set() - set the output value for the gpio 57 - * @chip: chip structure who controls the specified gpio 58 - * @offset: gpio whose value will be assigned 59 - * @value: logic level to assign to the gpio initially 60 - * 61 - * This will set the gpio bit specified to the desired value. It will set the 62 - * gpio pin low if value is 0 otherwise it will be high. 63 - */ 64 - static void msp71xx_exd_gpio_set(struct gpio_chip *chip, 65 - unsigned offset, int value) 66 - { 67 - struct msp71xx_exd_gpio_chip *msp71xx_chip = 68 - to_msp71xx_exd_gpio_chip(chip); 69 - const unsigned bit = MSP71XX_DATA_OFFSET(offset); 70 - 71 - __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg); 72 - } 73 - 74 - /* 75 - * msp71xx_exd_direction_output() - declare the direction mode for a gpio 76 - * @chip: chip structure which controls the specified gpio 77 - * @offset: gpio whose value will be assigned 78 - * @value: logic level to assign to the gpio initially 79 - * 80 - * This call will set the mode for the @gpio to output. It will set the 81 - * gpio pin low if value is 0 otherwise it will be high. 82 - */ 83 - static int msp71xx_exd_direction_output(struct gpio_chip *chip, 84 - unsigned offset, int value) 85 - { 86 - struct msp71xx_exd_gpio_chip *msp71xx_chip = 87 - to_msp71xx_exd_gpio_chip(chip); 88 - 89 - msp71xx_exd_gpio_set(chip, offset, value); 90 - __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg); 91 - return 0; 92 - } 93 - 94 - /* 95 - * msp71xx_exd_direction_input() - declare the direction mode for a gpio 96 - * @chip: chip structure which controls the specified gpio 97 - * @offset: gpio whose to which the value will be assigned 98 - * 99 - * This call will set the mode for the @gpio to input. 100 - */ 101 - static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset) 102 - { 103 - struct msp71xx_exd_gpio_chip *msp71xx_chip = 104 - to_msp71xx_exd_gpio_chip(chip); 105 - 106 - __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg); 107 - return 0; 108 - } 109 - 110 - #define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \ 111 - { \ 112 - .chip = { \ 113 - .label = name, \ 114 - .direction_input = msp71xx_exd_direction_input, \ 115 - .direction_output = msp71xx_exd_direction_output, \ 116 - .get = msp71xx_exd_gpio_get, \ 117 - .set = msp71xx_exd_gpio_set, \ 118 - .base = base_gpio, \ 119 - .ngpio = num_gpio, \ 120 - }, \ 121 - .reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \ 122 - } 123 - 124 - /* 125 - * struct msp71xx_exd_gpio_banks[] - container array of gpio banks 126 - * @chip: chip structure for the specified gpio bank 127 - * @reg: register for reading and writing the gpio pin value 128 - * 129 - * This array structure defines the extended gpio banks for the 130 - * PMC MIPS Processor. We specify the bank name, the data/config 131 - * register,the base starting gpio number, and the number of 132 - * gpios exposed by the bank of gpios. 133 - */ 134 - static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = { 135 - 136 - MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8), 137 - MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4), 138 - }; 139 - 140 - void __init msp71xx_init_gpio_extended(void) 141 - { 142 - int i; 143 - 144 - for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++) 145 - gpiochip_add(&msp71xx_exd_gpio_banks[i].chip); 146 - }

+2 -11

arch/mips/powertv/asic/asic_devices.c

··· 529 529 */ 530 530 void platform_release_memory(void *ptr, int size) 531 531 { 532 - unsigned long addr; 533 - unsigned long end; 534 - 535 - addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; 536 - end = ((unsigned long)ptr + size) & PAGE_MASK; 537 - 538 - for (; addr < end; addr += PAGE_SIZE) { 539 - ClearPageReserved(virt_to_page(__va(addr))); 540 - init_page_count(virt_to_page(__va(addr))); 541 - free_page((unsigned long)__va(addr)); 542 - } 532 + free_reserved_area((unsigned long)ptr, (unsigned long)(ptr + size), 533 + -1, NULL); 543 534 } 544 535 EXPORT_SYMBOL(platform_release_memory); 545 536

+1 -1

arch/mips/ralink/of.c

··· 104 104 if (!of_have_populated_dt()) 105 105 panic("device tree not present"); 106 106 107 - strncpy(of_ids[0].compatible, soc_info.compatible, len); 107 + strlcpy(of_ids[0].compatible, soc_info.compatible, len); 108 108 strncpy(of_ids[1].compatible, "palmbus", len); 109 109 110 110 if (of_platform_populate(NULL, of_ids, NULL, NULL))

+1

arch/mips/sgi-ip27/Makefile

··· 7 7 ip27-xtalk.o 8 8 9 9 obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 10 + obj-$(CONFIG_PCI) += ip27-irq-pci.o 10 11 obj-$(CONFIG_SMP) += ip27-smp.o

+266

arch/mips/sgi-ip27/ip27-irq-pci.c

··· 1 + /* 2 + * ip27-irq.c: Highlevel interrupt handling for IP27 architecture. 3 + * 4 + * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 5 + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 6 + * Copyright (C) 1999 - 2001 Kanoj Sarcar 7 + */ 8 + 9 + #undef DEBUG 10 + 11 + #include <linux/init.h> 12 + #include <linux/irq.h> 13 + #include <linux/errno.h> 14 + #include <linux/signal.h> 15 + #include <linux/sched.h> 16 + #include <linux/types.h> 17 + #include <linux/interrupt.h> 18 + #include <linux/ioport.h> 19 + #include <linux/timex.h> 20 + #include <linux/smp.h> 21 + #include <linux/random.h> 22 + #include <linux/kernel.h> 23 + #include <linux/kernel_stat.h> 24 + #include <linux/delay.h> 25 + #include <linux/bitops.h> 26 + 27 + #include <asm/bootinfo.h> 28 + #include <asm/io.h> 29 + #include <asm/mipsregs.h> 30 + 31 + #include <asm/processor.h> 32 + #include <asm/pci/bridge.h> 33 + #include <asm/sn/addrs.h> 34 + #include <asm/sn/agent.h> 35 + #include <asm/sn/arch.h> 36 + #include <asm/sn/hub.h> 37 + #include <asm/sn/intr.h> 38 + 39 + /* 40 + * Linux has a controller-independent x86 interrupt architecture. 41 + * every controller has a 'controller-template', that is used 42 + * by the main code to do the right thing. Each driver-visible 43 + * interrupt source is transparently wired to the appropriate 44 + * controller. Thus drivers need not be aware of the 45 + * interrupt-controller. 46 + * 47 + * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, 48 + * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. 49 + * (IO-APICs assumed to be messaging to Pentium local-APICs) 50 + * 51 + * the code is designed to be easily extended with new/different 52 + * interrupt controllers, without having to do assembly magic. 53 + */ 54 + 55 + extern struct bridge_controller *irq_to_bridge[]; 56 + extern int irq_to_slot[]; 57 + 58 + /* 59 + * use these macros to get the encoded nasid and widget id 60 + * from the irq value 61 + */ 62 + #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] 63 + #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] 64 + 65 + static inline int alloc_level(int cpu, int irq) 66 + { 67 + struct hub_data *hub = hub_data(cpu_to_node(cpu)); 68 + struct slice_data *si = cpu_data[cpu].data; 69 + int level; 70 + 71 + level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); 72 + if (level >= LEVELS_PER_SLICE) 73 + panic("Cpu %d flooded with devices", cpu); 74 + 75 + __set_bit(level, hub->irq_alloc_mask); 76 + si->level_to_irq[level] = irq; 77 + 78 + return level; 79 + } 80 + 81 + static inline int find_level(cpuid_t *cpunum, int irq) 82 + { 83 + int cpu, i; 84 + 85 + for_each_online_cpu(cpu) { 86 + struct slice_data *si = cpu_data[cpu].data; 87 + 88 + for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) 89 + if (si->level_to_irq[i] == irq) { 90 + *cpunum = cpu; 91 + 92 + return i; 93 + } 94 + } 95 + 96 + panic("Could not identify cpu/level for irq %d", irq); 97 + } 98 + 99 + static int intr_connect_level(int cpu, int bit) 100 + { 101 + nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 102 + struct slice_data *si = cpu_data[cpu].data; 103 + 104 + set_bit(bit, si->irq_enable_mask); 105 + 106 + if (!cputoslice(cpu)) { 107 + REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 108 + REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 109 + } else { 110 + REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 111 + REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 112 + } 113 + 114 + return 0; 115 + } 116 + 117 + static int intr_disconnect_level(int cpu, int bit) 118 + { 119 + nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 120 + struct slice_data *si = cpu_data[cpu].data; 121 + 122 + clear_bit(bit, si->irq_enable_mask); 123 + 124 + if (!cputoslice(cpu)) { 125 + REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 126 + REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 127 + } else { 128 + REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 129 + REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 130 + } 131 + 132 + return 0; 133 + } 134 + 135 + /* Startup one of the (PCI ...) IRQs routes over a bridge. */ 136 + static unsigned int startup_bridge_irq(struct irq_data *d) 137 + { 138 + struct bridge_controller *bc; 139 + bridgereg_t device; 140 + bridge_t *bridge; 141 + int pin, swlevel; 142 + cpuid_t cpu; 143 + 144 + pin = SLOT_FROM_PCI_IRQ(d->irq); 145 + bc = IRQ_TO_BRIDGE(d->irq); 146 + bridge = bc->base; 147 + 148 + pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); 149 + /* 150 + * "map" irq to a swlevel greater than 6 since the first 6 bits 151 + * of INT_PEND0 are taken 152 + */ 153 + swlevel = find_level(&cpu, d->irq); 154 + bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); 155 + bridge->b_int_enable |= (1 << pin); 156 + bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ 157 + 158 + /* 159 + * Enable sending of an interrupt clear packt to the hub on a high to 160 + * low transition of the interrupt pin. 161 + * 162 + * IRIX sets additional bits in the address which are documented as 163 + * reserved in the bridge docs. 164 + */ 165 + bridge->b_int_mode |= (1UL << pin); 166 + 167 + /* 168 + * We assume the bridge to have a 1:1 mapping between devices 169 + * (slots) and intr pins. 170 + */ 171 + device = bridge->b_int_device; 172 + device &= ~(7 << (pin*3)); 173 + device |= (pin << (pin*3)); 174 + bridge->b_int_device = device; 175 + 176 + bridge->b_wid_tflush; 177 + 178 + intr_connect_level(cpu, swlevel); 179 + 180 + return 0; /* Never anything pending. */ 181 + } 182 + 183 + /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ 184 + static void shutdown_bridge_irq(struct irq_data *d) 185 + { 186 + struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); 187 + bridge_t *bridge = bc->base; 188 + int pin, swlevel; 189 + cpuid_t cpu; 190 + 191 + pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); 192 + pin = SLOT_FROM_PCI_IRQ(d->irq); 193 + 194 + /* 195 + * map irq to a swlevel greater than 6 since the first 6 bits 196 + * of INT_PEND0 are taken 197 + */ 198 + swlevel = find_level(&cpu, d->irq); 199 + intr_disconnect_level(cpu, swlevel); 200 + 201 + bridge->b_int_enable &= ~(1 << pin); 202 + bridge->b_wid_tflush; 203 + } 204 + 205 + static inline void enable_bridge_irq(struct irq_data *d) 206 + { 207 + cpuid_t cpu; 208 + int swlevel; 209 + 210 + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 211 + intr_connect_level(cpu, swlevel); 212 + } 213 + 214 + static inline void disable_bridge_irq(struct irq_data *d) 215 + { 216 + cpuid_t cpu; 217 + int swlevel; 218 + 219 + swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 220 + intr_disconnect_level(cpu, swlevel); 221 + } 222 + 223 + static struct irq_chip bridge_irq_type = { 224 + .name = "bridge", 225 + .irq_startup = startup_bridge_irq, 226 + .irq_shutdown = shutdown_bridge_irq, 227 + .irq_mask = disable_bridge_irq, 228 + .irq_unmask = enable_bridge_irq, 229 + }; 230 + 231 + void register_bridge_irq(unsigned int irq) 232 + { 233 + irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 234 + } 235 + 236 + int request_bridge_irq(struct bridge_controller *bc) 237 + { 238 + int irq = allocate_irqno(); 239 + int swlevel, cpu; 240 + nasid_t nasid; 241 + 242 + if (irq < 0) 243 + return irq; 244 + 245 + /* 246 + * "map" irq to a swlevel greater than 6 since the first 6 bits 247 + * of INT_PEND0 are taken 248 + */ 249 + cpu = bc->irq_cpu; 250 + swlevel = alloc_level(cpu, irq); 251 + if (unlikely(swlevel < 0)) { 252 + free_irqno(irq); 253 + 254 + return -EAGAIN; 255 + } 256 + 257 + /* Make sure it's not already pending when we connect it. */ 258 + nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 259 + REMOTE_HUB_CLR_INTR(nasid, swlevel); 260 + 261 + intr_connect_level(cpu, swlevel); 262 + 263 + register_bridge_irq(irq); 264 + 265 + return irq; 266 + }

-214

arch/mips/sgi-ip27/ip27-irq.c

··· 29 29 #include <asm/mipsregs.h> 30 30 31 31 #include <asm/processor.h> 32 - #include <asm/pci/bridge.h> 33 32 #include <asm/sn/addrs.h> 34 33 #include <asm/sn/agent.h> 35 34 #include <asm/sn/arch.h> ··· 52 53 */ 53 54 54 55 extern asmlinkage void ip27_irq(void); 55 - 56 - extern struct bridge_controller *irq_to_bridge[]; 57 - extern int irq_to_slot[]; 58 - 59 - /* 60 - * use these macros to get the encoded nasid and widget id 61 - * from the irq value 62 - */ 63 - #define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)] 64 - #define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i] 65 - 66 - static inline int alloc_level(int cpu, int irq) 67 - { 68 - struct hub_data *hub = hub_data(cpu_to_node(cpu)); 69 - struct slice_data *si = cpu_data[cpu].data; 70 - int level; 71 - 72 - level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE); 73 - if (level >= LEVELS_PER_SLICE) 74 - panic("Cpu %d flooded with devices", cpu); 75 - 76 - __set_bit(level, hub->irq_alloc_mask); 77 - si->level_to_irq[level] = irq; 78 - 79 - return level; 80 - } 81 - 82 - static inline int find_level(cpuid_t *cpunum, int irq) 83 - { 84 - int cpu, i; 85 - 86 - for_each_online_cpu(cpu) { 87 - struct slice_data *si = cpu_data[cpu].data; 88 - 89 - for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++) 90 - if (si->level_to_irq[i] == irq) { 91 - *cpunum = cpu; 92 - 93 - return i; 94 - } 95 - } 96 - 97 - panic("Could not identify cpu/level for irq %d", irq); 98 - } 99 56 100 57 /* 101 58 * Find first bit set ··· 157 202 static void ip27_hub_error(void) 158 203 { 159 204 panic("CPU %d got a hub error interrupt", smp_processor_id()); 160 - } 161 - 162 - static int intr_connect_level(int cpu, int bit) 163 - { 164 - nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 165 - struct slice_data *si = cpu_data[cpu].data; 166 - 167 - set_bit(bit, si->irq_enable_mask); 168 - 169 - if (!cputoslice(cpu)) { 170 - REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 171 - REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 172 - } else { 173 - REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 174 - REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 175 - } 176 - 177 - return 0; 178 - } 179 - 180 - static int intr_disconnect_level(int cpu, int bit) 181 - { 182 - nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 183 - struct slice_data *si = cpu_data[cpu].data; 184 - 185 - clear_bit(bit, si->irq_enable_mask); 186 - 187 - if (!cputoslice(cpu)) { 188 - REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]); 189 - REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]); 190 - } else { 191 - REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]); 192 - REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]); 193 - } 194 - 195 - return 0; 196 - } 197 - 198 - /* Startup one of the (PCI ...) IRQs routes over a bridge. */ 199 - static unsigned int startup_bridge_irq(struct irq_data *d) 200 - { 201 - struct bridge_controller *bc; 202 - bridgereg_t device; 203 - bridge_t *bridge; 204 - int pin, swlevel; 205 - cpuid_t cpu; 206 - 207 - pin = SLOT_FROM_PCI_IRQ(d->irq); 208 - bc = IRQ_TO_BRIDGE(d->irq); 209 - bridge = bc->base; 210 - 211 - pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); 212 - /* 213 - * "map" irq to a swlevel greater than 6 since the first 6 bits 214 - * of INT_PEND0 are taken 215 - */ 216 - swlevel = find_level(&cpu, d->irq); 217 - bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); 218 - bridge->b_int_enable |= (1 << pin); 219 - bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ 220 - 221 - /* 222 - * Enable sending of an interrupt clear packt to the hub on a high to 223 - * low transition of the interrupt pin. 224 - * 225 - * IRIX sets additional bits in the address which are documented as 226 - * reserved in the bridge docs. 227 - */ 228 - bridge->b_int_mode |= (1UL << pin); 229 - 230 - /* 231 - * We assume the bridge to have a 1:1 mapping between devices 232 - * (slots) and intr pins. 233 - */ 234 - device = bridge->b_int_device; 235 - device &= ~(7 << (pin*3)); 236 - device |= (pin << (pin*3)); 237 - bridge->b_int_device = device; 238 - 239 - bridge->b_wid_tflush; 240 - 241 - intr_connect_level(cpu, swlevel); 242 - 243 - return 0; /* Never anything pending. */ 244 - } 245 - 246 - /* Shutdown one of the (PCI ...) IRQs routes over a bridge. */ 247 - static void shutdown_bridge_irq(struct irq_data *d) 248 - { 249 - struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); 250 - bridge_t *bridge = bc->base; 251 - int pin, swlevel; 252 - cpuid_t cpu; 253 - 254 - pr_debug("bridge_shutdown: irq 0x%x\n", d->irq); 255 - pin = SLOT_FROM_PCI_IRQ(d->irq); 256 - 257 - /* 258 - * map irq to a swlevel greater than 6 since the first 6 bits 259 - * of INT_PEND0 are taken 260 - */ 261 - swlevel = find_level(&cpu, d->irq); 262 - intr_disconnect_level(cpu, swlevel); 263 - 264 - bridge->b_int_enable &= ~(1 << pin); 265 - bridge->b_wid_tflush; 266 - } 267 - 268 - static inline void enable_bridge_irq(struct irq_data *d) 269 - { 270 - cpuid_t cpu; 271 - int swlevel; 272 - 273 - swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 274 - intr_connect_level(cpu, swlevel); 275 - } 276 - 277 - static inline void disable_bridge_irq(struct irq_data *d) 278 - { 279 - cpuid_t cpu; 280 - int swlevel; 281 - 282 - swlevel = find_level(&cpu, d->irq); /* Criminal offence */ 283 - intr_disconnect_level(cpu, swlevel); 284 - } 285 - 286 - static struct irq_chip bridge_irq_type = { 287 - .name = "bridge", 288 - .irq_startup = startup_bridge_irq, 289 - .irq_shutdown = shutdown_bridge_irq, 290 - .irq_mask = disable_bridge_irq, 291 - .irq_unmask = enable_bridge_irq, 292 - }; 293 - 294 - void register_bridge_irq(unsigned int irq) 295 - { 296 - irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 297 - } 298 - 299 - int request_bridge_irq(struct bridge_controller *bc) 300 - { 301 - int irq = allocate_irqno(); 302 - int swlevel, cpu; 303 - nasid_t nasid; 304 - 305 - if (irq < 0) 306 - return irq; 307 - 308 - /* 309 - * "map" irq to a swlevel greater than 6 since the first 6 bits 310 - * of INT_PEND0 are taken 311 - */ 312 - cpu = bc->irq_cpu; 313 - swlevel = alloc_level(cpu, irq); 314 - if (unlikely(swlevel < 0)) { 315 - free_irqno(irq); 316 - 317 - return -EAGAIN; 318 - } 319 - 320 - /* Make sure it's not already pending when we connect it. */ 321 - nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu)); 322 - REMOTE_HUB_CLR_INTR(nasid, swlevel); 323 - 324 - intr_connect_level(cpu, swlevel); 325 - 326 - register_bridge_irq(irq); 327 - 328 - return irq; 329 205 } 330 206 331 207 asmlinkage void plat_irq_dispatch(void)

+2 -1

arch/mips/sibyte/Kconfig

··· 147 147 148 148 config SIBYTE_BUS_WATCHER 149 149 bool "Support for Bus Watcher statistics" 150 - depends on SIBYTE_SB1xxx_SOC 150 + depends on SIBYTE_SB1xxx_SOC && \ 151 + (SIBYTE_BCM112X || SIBYTE_SB1250) 151 152 help 152 153 Handle and keep statistics on the bus error interrupts (COR_ECC, 153 154 BAD_ECC, IO_BUS).

+3 -2

arch/mips/sibyte/Platform

··· 13 13 -I$(srctree)/arch/mips/include/asm/mach-sibyte \ 14 14 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 15 15 16 - platform-$(CONFIG_SIBYTE_SB1250) += sibyte/ 17 16 cflags-$(CONFIG_SIBYTE_SB1250) += \ 18 17 -I$(srctree)/arch/mips/include/asm/mach-sibyte \ 19 18 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL ··· 30 31 # Sibyte BCM91120C (CRhine) board 31 32 # Sibyte BCM91125C (CRhone) board 32 33 # Sibyte BCM91125E (Rhone) board 33 - # Sibyte SWARM board 34 + # Sibyte BCM91250A (SWARM) board 35 + # Sibyte BCM91250C2 (LittleSur) board 34 36 # Sibyte BCM91x80 (BigSur) board 35 37 # 36 38 load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 ··· 41 41 load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 42 42 load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000 43 43 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 44 + load-$(CONFIG_SIBYTE_LITTLESUR) := 0xffffffff80100000

+1

arch/mips/sibyte/common/Makefile

··· 1 1 obj-y := cfe.o 2 + obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o 2 3 obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o 3 4 obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o

+1

arch/mips/sibyte/common/sb_tbprof.c

··· 27 27 #include <linux/types.h> 28 28 #include <linux/init.h> 29 29 #include <linux/interrupt.h> 30 + #include <linux/sched.h> 30 31 #include <linux/vmalloc.h> 31 32 #include <linux/fs.h> 32 33 #include <linux/errno.h>

-1

arch/mips/sibyte/sb1250/Makefile

··· 1 1 obj-y := setup.o irq.o time.o 2 2 3 3 obj-$(CONFIG_SMP) += smp.o 4 - obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o

+10 -4

arch/mips/sibyte/sb1250/bus_watcher.c arch/mips/sibyte/common/bus_watcher.c

··· 37 37 #include <asm/sibyte/sb1250_regs.h> 38 38 #include <asm/sibyte/sb1250_int.h> 39 39 #include <asm/sibyte/sb1250_scd.h> 40 + #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 41 + #include <asm/sibyte/bcm1480_regs.h> 42 + #endif 40 43 41 44 42 45 struct bw_stats_struct { ··· 84 81 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 85 82 /* Destructive read, clears register and interrupt */ 86 83 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 87 - #else 84 + #elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) 88 85 /* Use non-destructive register */ 89 86 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); 87 + #elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 88 + /* Use non-destructive register */ 89 + /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ 90 + status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); 91 + #else 92 + #error bus watcher being built for unknown Sibyte SOC! 90 93 #endif 91 94 if (!(status & 0x7fffffff)) { 92 95 printk("Using last values reaped by bus watcher driver\n"); ··· 183 174 unsigned long cntr; 184 175 #ifdef CONFIG_SIBYTE_BW_TRACE 185 176 int i; 186 - #endif 187 - #ifndef CONFIG_PROC_FS 188 - char bw_buf[1024]; 189 177 #endif 190 178 191 179 #ifdef CONFIG_SIBYTE_BW_TRACE

+2

arch/mips/sni/pcimt.c

··· 185 185 186 186 extern struct pci_ops sni_pcimt_ops; 187 187 188 + #ifdef CONFIG_PCI 188 189 static struct pci_controller sni_controller = { 189 190 .pci_ops = &sni_pcimt_ops, 190 191 .mem_resource = &sni_mem_resource, ··· 194 193 .io_offset = 0x00000000UL, 195 194 .io_map_base = SNI_PORT_BASE 196 195 }; 196 + #endif 197 197 198 198 static void enable_pcimt_irq(struct irq_data *d) 199 199 {

+9 -7

arch/mips/sni/pcit.c

··· 128 128 } 129 129 }; 130 130 131 - static struct resource sni_mem_resource = { 132 - .start = 0x18000000UL, 133 - .end = 0x1fbfffffUL, 134 - .name = "PCIT PCI MEM", 135 - .flags = IORESOURCE_MEM 136 - }; 137 - 138 131 static void __init sni_pcit_resource_init(void) 139 132 { 140 133 int i; ··· 140 147 141 148 extern struct pci_ops sni_pcit_ops; 142 149 150 + #ifdef CONFIG_PCI 151 + static struct resource sni_mem_resource = { 152 + .start = 0x18000000UL, 153 + .end = 0x1fbfffffUL, 154 + .name = "PCIT PCI MEM", 155 + .flags = IORESOURCE_MEM 156 + }; 157 + 143 158 static struct pci_controller sni_pcit_controller = { 144 159 .pci_ops = &sni_pcit_ops, 145 160 .mem_resource = &sni_mem_resource, ··· 156 155 .io_offset = 0x00000000UL, 157 156 .io_map_base = SNI_PORT_BASE 158 157 }; 158 + #endif /* CONFIG_PCI */ 159 159 160 160 static void enable_pcit_irq(struct irq_data *d) 161 161 {

-12

arch/mips/wrppmc/Makefile

··· 1 - # 2 - # This file is subject to the terms and conditions of the GNU General Public 3 - # License. See the file "COPYING" in the main directory of this archive 4 - # for more details. 5 - # 6 - # Copyright 2006 Wind River System, Inc. 7 - # Author: Rongkai.Zhan <rongkai.zhan@windriver.com> 8 - # 9 - # Makefile for the Wind River MIPS 4Kc PPMC Eval Board 10 - # 11 - 12 - obj-y += irq.o pci.o reset.o serial.o setup.o time.o

-7

arch/mips/wrppmc/Platform

··· 1 - # 2 - # Wind River PPMC Board (4KC + GT64120) 3 - # 4 - platform-$(CONFIG_WR_PPMC) += wrppmc/ 5 - cflags-$(CONFIG_WR_PPMC) += \ 6 - -I$(srctree)/arch/mips/include/asm/mach-wrppmc 7 - load-$(CONFIG_WR_PPMC) += 0xffffffff80100000

-56

arch/mips/wrppmc/irq.c

··· 1 - /* 2 - * irq.c: GT64120 Interrupt Controller 3 - * 4 - * Copyright (C) 2006, Wind River System Inc. 5 - * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com> 6 - * 7 - * This program is free software; you can redistribute it and/or modify it 8 - * under the terms of the GNU General Public License as published by the 9 - * Free Software Foundation; either version 2 of the License, or (at your 10 - * option) any later version. 11 - */ 12 - #include <linux/hardirq.h> 13 - #include <linux/init.h> 14 - #include <linux/irq.h> 15 - 16 - #include <asm/gt64120.h> 17 - #include <asm/irq_cpu.h> 18 - #include <asm/mipsregs.h> 19 - 20 - asmlinkage void plat_irq_dispatch(void) 21 - { 22 - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 23 - 24 - if (pending & STATUSF_IP7) 25 - do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */ 26 - else if (pending & STATUSF_IP6) 27 - do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */ 28 - else if (pending & STATUSF_IP3) 29 - do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */ 30 - else 31 - spurious_interrupt(); 32 - } 33 - 34 - /** 35 - * Initialize GT64120 Interrupt Controller 36 - */ 37 - void gt64120_init_pic(void) 38 - { 39 - /* clear CPU Interrupt Cause Registers */ 40 - GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21)); 41 - GT_WRITE(GT_HINTRCAUSE_OFS, 0x00); 42 - 43 - /* Disable all interrupts from GT64120 bridge chip */ 44 - GT_WRITE(GT_INTRMASK_OFS, 0x00); 45 - GT_WRITE(GT_HINTRMASK_OFS, 0x00); 46 - GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00); 47 - GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00); 48 - } 49 - 50 - void __init arch_init_irq(void) 51 - { 52 - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ 53 - mips_cpu_irq_init(); 54 - 55 - gt64120_init_pic(); 56 - }

-52

arch/mips/wrppmc/pci.c

··· 1 - /* 2 - * pci.c: GT64120 PCI support. 3 - * 4 - * Copyright (C) 2006, Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> 5 - * 6 - * This file is subject to the terms and conditions of the GNU General Public 7 - * License. See the file "COPYING" in the main directory of this archive 8 - * for more details. 9 - */ 10 - #include <linux/init.h> 11 - #include <linux/ioport.h> 12 - #include <linux/types.h> 13 - #include <linux/pci.h> 14 - 15 - #include <asm/gt64120.h> 16 - 17 - extern struct pci_ops gt64xxx_pci0_ops; 18 - 19 - static struct resource pci0_io_resource = { 20 - .name = "pci_0 io", 21 - .start = GT_PCI_IO_BASE, 22 - .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, 23 - .flags = IORESOURCE_IO, 24 - }; 25 - 26 - static struct resource pci0_mem_resource = { 27 - .name = "pci_0 memory", 28 - .start = GT_PCI_MEM_BASE, 29 - .end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1, 30 - .flags = IORESOURCE_MEM, 31 - }; 32 - 33 - static struct pci_controller hose_0 = { 34 - .pci_ops = &gt64xxx_pci0_ops, 35 - .io_resource = &pci0_io_resource, 36 - .mem_resource = &pci0_mem_resource, 37 - }; 38 - 39 - static int __init gt64120_pci_init(void) 40 - { 41 - (void) GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ 42 - (void) GT_READ(GT_PCI0_BARE_OFS); 43 - 44 - /* reset the whole PCI I/O space range */ 45 - ioport_resource.start = GT_PCI_IO_BASE; 46 - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; 47 - 48 - register_pci_controller(&hose_0); 49 - return 0; 50 - } 51 - 52 - arch_initcall(gt64120_pci_init);

-41

arch/mips/wrppmc/reset.c

··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 1997 Ralf Baechle 7 - */ 8 - #include <linux/irqflags.h> 9 - #include <linux/kernel.h> 10 - 11 - #include <asm/cacheflush.h> 12 - #include <asm/idle.h> 13 - #include <asm/mipsregs.h> 14 - #include <asm/processor.h> 15 - 16 - void wrppmc_machine_restart(char *command) 17 - { 18 - /* 19 - * Ouch, we're still alive ... This time we take the silver bullet ... 20 - * ... and find that we leave the hardware in a state in which the 21 - * kernel in the flush locks up somewhen during of after the PCI 22 - * detection stuff. 23 - */ 24 - local_irq_disable(); 25 - set_c0_status(ST0_BEV | ST0_ERL); 26 - change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); 27 - flush_cache_all(); 28 - write_c0_wired(0); 29 - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); 30 - } 31 - 32 - void wrppmc_machine_halt(void) 33 - { 34 - local_irq_disable(); 35 - 36 - printk(KERN_NOTICE "You can safely turn off the power\n"); 37 - while (1) { 38 - if (cpu_wait) 39 - cpu_wait(); 40 - } 41 - }

-80

arch/mips/wrppmc/serial.c

··· 1 - /* 2 - * Registration of WRPPMC UART platform device. 3 - * 4 - * Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org> 5 - * 6 - * This program is free software; you can redistribute it and/or modify 7 - * it under the terms of the GNU General Public License as published by 8 - * the Free Software Foundation; either version 2 of the License, or 9 - * (at your option) any later version. 10 - * 11 - * This program is distributed in the hope that it will be useful, 12 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 - * GNU General Public License for more details. 15 - * 16 - * You should have received a copy of the GNU General Public License 17 - * along with this program; if not, write to the Free Software 18 - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 19 - */ 20 - #include <linux/errno.h> 21 - #include <linux/init.h> 22 - #include <linux/ioport.h> 23 - #include <linux/platform_device.h> 24 - #include <linux/serial_8250.h> 25 - 26 - #include <asm/gt64120.h> 27 - 28 - static struct resource wrppmc_uart_resource[] __initdata = { 29 - { 30 - .start = WRPPMC_UART16550_BASE, 31 - .end = WRPPMC_UART16550_BASE + 7, 32 - .flags = IORESOURCE_MEM, 33 - }, 34 - { 35 - .start = WRPPMC_UART16550_IRQ, 36 - .end = WRPPMC_UART16550_IRQ, 37 - .flags = IORESOURCE_IRQ, 38 - }, 39 - }; 40 - 41 - static struct plat_serial8250_port wrppmc_serial8250_port[] = { 42 - { 43 - .irq = WRPPMC_UART16550_IRQ, 44 - .uartclk = WRPPMC_UART16550_CLOCK, 45 - .iotype = UPIO_MEM, 46 - .flags = UPF_IOREMAP | UPF_SKIP_TEST, 47 - .mapbase = WRPPMC_UART16550_BASE, 48 - }, 49 - {}, 50 - }; 51 - 52 - static __init int wrppmc_uart_add(void) 53 - { 54 - struct platform_device *pdev; 55 - int retval; 56 - 57 - pdev = platform_device_alloc("serial8250", -1); 58 - if (!pdev) 59 - return -ENOMEM; 60 - 61 - pdev->id = PLAT8250_DEV_PLATFORM; 62 - pdev->dev.platform_data = wrppmc_serial8250_port; 63 - 64 - retval = platform_device_add_resources(pdev, wrppmc_uart_resource, 65 - ARRAY_SIZE(wrppmc_uart_resource)); 66 - if (retval) 67 - goto err_free_device; 68 - 69 - retval = platform_device_add(pdev); 70 - if (retval) 71 - goto err_free_device; 72 - 73 - return 0; 74 - 75 - err_free_device: 76 - platform_device_put(pdev); 77 - 78 - return retval; 79 - } 80 - device_initcall(wrppmc_uart_add);

-128

arch/mips/wrppmc/setup.c

··· 1 - /* 2 - * setup.c: Setup pointers to hardware dependent routines. 3 - * 4 - * This file is subject to the terms and conditions of the GNU General Public 5 - * License. See the file "COPYING" in the main directory of this archive 6 - * for more details. 7 - * 8 - * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) 9 - * Copyright (C) 2006, Wind River System Inc. Rongkai.zhan <rongkai.zhan@windriver.com> 10 - */ 11 - #include <linux/init.h> 12 - #include <linux/string.h> 13 - #include <linux/kernel.h> 14 - #include <linux/pm.h> 15 - 16 - #include <asm/io.h> 17 - #include <asm/bootinfo.h> 18 - #include <asm/reboot.h> 19 - #include <asm/time.h> 20 - #include <asm/gt64120.h> 21 - 22 - unsigned long gt64120_base = KSEG1ADDR(0x14000000); 23 - 24 - #ifdef WRPPMC_EARLY_DEBUG 25 - 26 - static volatile unsigned char * wrppmc_led = \ 27 - (volatile unsigned char *)KSEG1ADDR(WRPPMC_LED_BASE); 28 - 29 - /* 30 - * PPMC LED control register: 31 - * -) bit[0] controls DS1 LED (1 - OFF, 0 - ON) 32 - * -) bit[1] controls DS2 LED (1 - OFF, 0 - ON) 33 - * -) bit[2] controls DS4 LED (1 - OFF, 0 - ON) 34 - */ 35 - void wrppmc_led_on(int mask) 36 - { 37 - unsigned char value = *wrppmc_led; 38 - 39 - value &= (0xF8 | mask); 40 - *wrppmc_led = value; 41 - } 42 - 43 - /* If mask = 0, turn off all LEDs */ 44 - void wrppmc_led_off(int mask) 45 - { 46 - unsigned char value = *wrppmc_led; 47 - 48 - value |= (0x7 & mask); 49 - *wrppmc_led = value; 50 - } 51 - 52 - /* 53 - * We assume that bootloader has initialized UART16550 correctly 54 - */ 55 - void __init wrppmc_early_putc(char ch) 56 - { 57 - static volatile unsigned char *wrppmc_uart = \ 58 - (volatile unsigned char *)KSEG1ADDR(WRPPMC_UART16550_BASE); 59 - unsigned char value; 60 - 61 - /* Wait until Transmit-Holding-Register is empty */ 62 - while (1) { 63 - value = *(wrppmc_uart + 5); 64 - if (value & 0x20) 65 - break; 66 - } 67 - 68 - *wrppmc_uart = ch; 69 - } 70 - 71 - void __init wrppmc_early_printk(const char *fmt, ...) 72 - { 73 - static char pbuf[256] = {'\0', }; 74 - char *ch = pbuf; 75 - va_list args; 76 - unsigned int i; 77 - 78 - memset(pbuf, 0, 256); 79 - va_start(args, fmt); 80 - i = vsprintf(pbuf, fmt, args); 81 - va_end(args); 82 - 83 - /* Print the string */ 84 - while (*ch != '\0') { 85 - wrppmc_early_putc(*ch); 86 - /* if print '\n', also print '\r' */ 87 - if (*ch++ == '\n') 88 - wrppmc_early_putc('\r'); 89 - } 90 - } 91 - #endif /* WRPPMC_EARLY_DEBUG */ 92 - 93 - void __init prom_free_prom_memory(void) 94 - { 95 - } 96 - 97 - void __init plat_mem_setup(void) 98 - { 99 - extern void wrppmc_machine_restart(char *command); 100 - extern void wrppmc_machine_halt(void); 101 - 102 - _machine_restart = wrppmc_machine_restart; 103 - _machine_halt = wrppmc_machine_halt; 104 - pm_power_off = wrppmc_machine_halt; 105 - 106 - /* This makes the operations of 'in/out[bwl]' to the 107 - * physical address ( < KSEG0) can work via KSEG1 108 - */ 109 - set_io_port_base(KSEG1); 110 - } 111 - 112 - const char *get_system_type(void) 113 - { 114 - return "Wind River PPMC (GT64120)"; 115 - } 116 - 117 - /* 118 - * Initializes basic routines and structures pointers, memory size (as 119 - * given by the bios and saves the command line. 120 - */ 121 - void __init prom_init(void) 122 - { 123 - add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); 124 - add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); 125 - 126 - wrppmc_early_printk("prom_init: GT64120 SDRAM Bank 0: 0x%x - 0x%08lx\n", 127 - WRPPMC_SDRAM_SCS0_BASE, (WRPPMC_SDRAM_SCS0_BASE + WRPPMC_SDRAM_SCS0_SIZE)); 128 - }

-39

arch/mips/wrppmc/time.c

··· 1 - /* 2 - * time.c: MIPS CPU Count/Compare timer hookup 3 - * 4 - * Author: Mark.Zhan, <rongkai.zhan@windriver.com> 5 - * 6 - * This file is subject to the terms and conditions of the GNU General Public 7 - * License. See the file "COPYING" in the main directory of this archive 8 - * for more details. 9 - * 10 - * Copyright (C) 1996, 1997, 2004 by Ralf Baechle (ralf@linux-mips.org) 11 - * Copyright (C) 2006, Wind River System Inc. 12 - */ 13 - #include <linux/init.h> 14 - #include <linux/interrupt.h> 15 - #include <linux/irq.h> 16 - 17 - #include <asm/gt64120.h> 18 - #include <asm/time.h> 19 - 20 - #define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ 21 - 22 - /* 23 - * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 24 - * 25 - * NOTE: We disable all GT64120 timers, and use MIPS processor internal 26 - * timer as the source of kernel clock tick. 27 - */ 28 - void __init plat_time_init(void) 29 - { 30 - /* Disable GT64120 timers */ 31 - GT_WRITE(GT_TC_CONTROL_OFS, 0x00); 32 - GT_WRITE(GT_TC0_OFS, 0x00); 33 - GT_WRITE(GT_TC1_OFS, 0x00); 34 - GT_WRITE(GT_TC2_OFS, 0x00); 35 - GT_WRITE(GT_TC3_OFS, 0x00); 36 - 37 - /* Use MIPS compare/count internal timer */ 38 - mips_hpt_frequency = WRPPMC_CPU_CLK_FREQ; 39 - }

+1 -1

drivers/ata/Kconfig

··· 160 160 161 161 config PATA_OCTEON_CF 162 162 tristate "OCTEON Boot Bus Compact Flash support" 163 - depends on CPU_CAVIUM_OCTEON 163 + depends on CAVIUM_OCTEON_SOC 164 164 help 165 165 This option enables a polled compact flash driver for use with 166 166 compact flash cards attached to the OCTEON boot bus.

+1 -1

drivers/char/hw_random/Kconfig

··· 167 167 168 168 config HW_RANDOM_OCTEON 169 169 tristate "Octeon Random Number Generator support" 170 - depends on HW_RANDOM && CPU_CAVIUM_OCTEON 170 + depends on HW_RANDOM && CAVIUM_OCTEON_SOC 171 171 default HW_RANDOM 172 172 ---help--- 173 173 This driver provides kernel-side support for the Random Number

+3 -3

drivers/edac/Kconfig

··· 349 349 350 350 config EDAC_OCTEON_L2C 351 351 tristate "Cavium Octeon Secondary Caches (L2C)" 352 - depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON 352 + depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 353 353 help 354 354 Support for error detection and correction on the 355 355 Cavium Octeon family of SOCs. 356 356 357 357 config EDAC_OCTEON_LMC 358 358 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 359 - depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON 359 + depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 360 360 help 361 361 Support for error detection and correction on the 362 362 Cavium Octeon family of SOCs. 363 363 364 364 config EDAC_OCTEON_PCI 365 365 tristate "Cavium Octeon PCI Controller" 366 - depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON 366 + depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC 367 367 help 368 368 Support for error detection and correction on the 369 369 Cavium Octeon family of SOCs.

+1 -1

drivers/i2c/busses/Kconfig

··· 739 739 740 740 config I2C_OCTEON 741 741 tristate "Cavium OCTEON I2C bus support" 742 - depends on CPU_CAVIUM_OCTEON 742 + depends on CAVIUM_OCTEON_SOC 743 743 help 744 744 Say yes if you want to support the I2C serial bus on Cavium 745 745 OCTEON SOC.

+1 -1

drivers/net/ethernet/octeon/Kconfig

··· 4 4 5 5 config OCTEON_MGMT_ETHERNET 6 6 tristate "Octeon Management port ethernet driver (CN5XXX, CN6XXX)" 7 - depends on CPU_CAVIUM_OCTEON 7 + depends on CAVIUM_OCTEON_SOC 8 8 select PHYLIB 9 9 select MDIO_OCTEON 10 10 default y

+1 -1

drivers/net/phy/Kconfig

··· 135 135 136 136 config MDIO_OCTEON 137 137 tristate "Support for MDIO buses on Octeon SOCs" 138 - depends on CPU_CAVIUM_OCTEON 138 + depends on CAVIUM_OCTEON_SOC 139 139 default y 140 140 help 141 141

+2

drivers/rapidio/switches/idt_gen2.c

··· 16 16 #include <linux/rio_drv.h> 17 17 #include <linux/rio_ids.h> 18 18 #include <linux/delay.h> 19 + 20 + #include <asm/page.h> 19 21 #include "../rio.h" 20 22 21 23 #define LOCAL_RTE_CONF_DESTID_SEL 0x010070

+1 -1

drivers/spi/Kconfig

··· 266 266 267 267 config SPI_OCTEON 268 268 tristate "Cavium OCTEON SPI controller" 269 - depends on CPU_CAVIUM_OCTEON 269 + depends on CAVIUM_OCTEON_SOC 270 270 help 271 271 SPI host driver for the hardware found on some Cavium OCTEON 272 272 SOCs.

+1 -1

drivers/ssb/Kconfig

··· 144 144 # Assumption: We are on embedded, if we compile the MIPS core. 145 145 config SSB_EMBEDDED 146 146 bool 147 - depends on SSB_DRIVER_MIPS 147 + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE 148 148 default y 149 149 150 150 config SSB_DRIVER_EXTIF

+1 -1

drivers/staging/octeon/Kconfig

··· 1 1 config OCTEON_ETHERNET 2 2 tristate "Cavium Networks Octeon Ethernet support" 3 - depends on CPU_CAVIUM_OCTEON && NETDEVICES 3 + depends on CAVIUM_OCTEON_SOC && NETDEVICES 4 4 select PHYLIB 5 5 select MDIO_OCTEON 6 6 help

+105 -75

drivers/tty/serial/8250/8250_dw.c

··· 29 29 #include <linux/clk.h> 30 30 #include <linux/pm_runtime.h> 31 31 32 + #include <asm/byteorder.h> 33 + 32 34 #include "8250.h" 33 35 34 36 /* Offsets for the DesignWare specific registers */ ··· 59 57 int last_lcr; 60 58 int line; 61 59 struct clk *clk; 60 + u8 usr_reg; 62 61 }; 63 62 64 63 static void dw8250_serial_out(struct uart_port *p, int offset, int value) ··· 78 75 offset <<= p->regshift; 79 76 80 77 return readb(p->membase + offset); 78 + } 79 + 80 + /* Read Back (rb) version to ensure register access ording. */ 81 + static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value) 82 + { 83 + dw8250_serial_out(p, offset, value); 84 + dw8250_serial_in(p, UART_LCR); 81 85 } 82 86 83 87 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) ··· 114 104 return 1; 115 105 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 116 106 /* Clear the USR and write the LCR again. */ 117 - (void)p->serial_in(p, DW_UART_USR); 107 + (void)p->serial_in(p, d->usr_reg); 118 108 p->serial_out(p, UART_LCR, d->last_lcr); 119 109 120 110 return 1; ··· 134 124 if (state) 135 125 pm_runtime_put_sync_suspend(port->dev); 136 126 } 137 - 138 - static int dw8250_probe_of(struct uart_port *p) 139 - { 140 - struct device_node *np = p->dev->of_node; 141 - u32 val; 142 - 143 - if (!of_property_read_u32(np, "reg-io-width", &val)) { 144 - switch (val) { 145 - case 1: 146 - break; 147 - case 4: 148 - p->iotype = UPIO_MEM32; 149 - p->serial_in = dw8250_serial_in32; 150 - p->serial_out = dw8250_serial_out32; 151 - break; 152 - default: 153 - dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 154 - return -EINVAL; 155 - } 156 - } 157 - 158 - if (!of_property_read_u32(np, "reg-shift", &val)) 159 - p->regshift = val; 160 - 161 - /* clock got configured through clk api, all done */ 162 - if (p->uartclk) 163 - return 0; 164 - 165 - /* try to find out clock frequency from DT as fallback */ 166 - if (of_property_read_u32(np, "clock-frequency", &val)) { 167 - dev_err(p->dev, "clk or clock-frequency not defined\n"); 168 - return -EINVAL; 169 - } 170 - p->uartclk = val; 171 - 172 - return 0; 173 - } 174 - 175 - #ifdef CONFIG_ACPI 176 - static int dw8250_probe_acpi(struct uart_8250_port *up) 177 - { 178 - const struct acpi_device_id *id; 179 - struct uart_port *p = &up->port; 180 - 181 - id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); 182 - if (!id) 183 - return -ENODEV; 184 - 185 - p->iotype = UPIO_MEM32; 186 - p->serial_in = dw8250_serial_in32; 187 - p->serial_out = dw8250_serial_out32; 188 - p->regshift = 2; 189 - 190 - if (!p->uartclk) 191 - p->uartclk = (unsigned int)id->driver_data; 192 - 193 - up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL); 194 - if (!up->dma) 195 - return -ENOMEM; 196 - 197 - up->dma->rxconf.src_maxburst = p->fifosize / 4; 198 - up->dma->txconf.dst_maxburst = p->fifosize / 4; 199 - 200 - return 0; 201 - } 202 - #else 203 - static inline int dw8250_probe_acpi(struct uart_8250_port *up) 204 - { 205 - return -ENODEV; 206 - } 207 - #endif /* CONFIG_ACPI */ 208 127 209 128 static void dw8250_setup_port(struct uart_8250_port *up) 210 129 { ··· 167 228 up->capabilities |= UART_CAP_AFE; 168 229 } 169 230 231 + static int dw8250_probe_of(struct uart_port *p, 232 + struct dw8250_data *data) 233 + { 234 + struct device_node *np = p->dev->of_node; 235 + u32 val; 236 + bool has_ucv = true; 237 + 238 + if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 239 + #ifdef __BIG_ENDIAN 240 + /* 241 + * Low order bits of these 64-bit registers, when 242 + * accessed as a byte, are 7 bytes further down in the 243 + * address space in big endian mode. 244 + */ 245 + p->membase += 7; 246 + #endif 247 + p->serial_out = dw8250_serial_out_rb; 248 + p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 249 + p->type = PORT_OCTEON; 250 + data->usr_reg = 0x27; 251 + has_ucv = false; 252 + } else if (!of_property_read_u32(np, "reg-io-width", &val)) { 253 + switch (val) { 254 + case 1: 255 + break; 256 + case 4: 257 + p->iotype = UPIO_MEM32; 258 + p->serial_in = dw8250_serial_in32; 259 + p->serial_out = dw8250_serial_out32; 260 + break; 261 + default: 262 + dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 263 + return -EINVAL; 264 + } 265 + } 266 + if (has_ucv) 267 + dw8250_setup_port(container_of(p, struct uart_8250_port, port)); 268 + 269 + if (!of_property_read_u32(np, "reg-shift", &val)) 270 + p->regshift = val; 271 + 272 + /* clock got configured through clk api, all done */ 273 + if (p->uartclk) 274 + return 0; 275 + 276 + /* try to find out clock frequency from DT as fallback */ 277 + if (of_property_read_u32(np, "clock-frequency", &val)) { 278 + dev_err(p->dev, "clk or clock-frequency not defined\n"); 279 + return -EINVAL; 280 + } 281 + p->uartclk = val; 282 + 283 + return 0; 284 + } 285 + 286 + #ifdef CONFIG_ACPI 287 + static int dw8250_probe_acpi(struct uart_8250_port *up) 288 + { 289 + const struct acpi_device_id *id; 290 + struct uart_port *p = &up->port; 291 + 292 + dw8250_setup_port(up); 293 + 294 + id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); 295 + if (!id) 296 + return -ENODEV; 297 + 298 + p->iotype = UPIO_MEM32; 299 + p->serial_in = dw8250_serial_in32; 300 + p->serial_out = dw8250_serial_out32; 301 + p->regshift = 2; 302 + 303 + if (!p->uartclk) 304 + p->uartclk = (unsigned int)id->driver_data; 305 + 306 + up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL); 307 + if (!up->dma) 308 + return -ENOMEM; 309 + 310 + up->dma->rxconf.src_maxburst = p->fifosize / 4; 311 + up->dma->txconf.dst_maxburst = p->fifosize / 4; 312 + 313 + return 0; 314 + } 315 + #else 316 + static inline int dw8250_probe_acpi(struct uart_8250_port *up) 317 + { 318 + return -ENODEV; 319 + } 320 + #endif /* CONFIG_ACPI */ 321 + 170 322 static int dw8250_probe(struct platform_device *pdev) 171 323 { 172 324 struct uart_8250_port uart = {}; ··· 289 259 if (!data) 290 260 return -ENOMEM; 291 261 262 + data->usr_reg = DW_UART_USR; 292 263 data->clk = devm_clk_get(&pdev->dev, NULL); 293 264 if (!IS_ERR(data->clk)) { 294 265 clk_prepare_enable(data->clk); ··· 301 270 uart.port.serial_out = dw8250_serial_out; 302 271 uart.port.private_data = data; 303 272 304 - dw8250_setup_port(&uart); 305 - 306 273 if (pdev->dev.of_node) { 307 - err = dw8250_probe_of(&uart.port); 274 + err = dw8250_probe_of(&uart.port, data); 308 275 if (err) 309 276 return err; 310 277 } else if (ACPI_HANDLE(&pdev->dev)) { ··· 391 362 392 363 static const struct of_device_id dw8250_of_match[] = { 393 364 { .compatible = "snps,dw-apb-uart" }, 365 + { .compatible = "cavium,octeon-3860-uart" }, 394 366 { /* Sentinel */ } 395 367 }; 396 368 MODULE_DEVICE_TABLE(of, dw8250_of_match);

+2 -2

drivers/usb/host/Kconfig

··· 283 283 284 284 config USB_OCTEON_EHCI 285 285 bool "Octeon on-chip EHCI support" 286 - depends on CPU_CAVIUM_OCTEON 286 + depends on CAVIUM_OCTEON_SOC 287 287 default n 288 288 select USB_EHCI_BIG_ENDIAN_MMIO 289 289 help ··· 488 488 489 489 config USB_OCTEON_OHCI 490 490 bool "Octeon on-chip OHCI support" 491 - depends on CPU_CAVIUM_OCTEON 491 + depends on CAVIUM_OCTEON_SOC 492 492 default USB_OCTEON_EHCI 493 493 select USB_OHCI_BIG_ENDIAN_MMIO 494 494 select USB_OHCI_LITTLE_ENDIAN

+1 -1

drivers/watchdog/Kconfig

··· 1074 1074 1075 1075 config OCTEON_WDT 1076 1076 tristate "Cavium OCTEON SOC family Watchdog Timer" 1077 - depends on CPU_CAVIUM_OCTEON 1077 + depends on CAVIUM_OCTEON_SOC 1078 1078 default y 1079 1079 select EXPORT_UASM if OCTEON_WDT = m 1080 1080 help

+1 -1

drivers/watchdog/sb_wdog.c

··· 208 208 * get the remaining count from the ... count register 209 209 * which is 1*8 before the config register 210 210 */ 211 - ret = put_user(__raw_readq(user_dog - 8) / 1000000, p); 211 + ret = put_user((u32)__raw_readq(user_dog - 8) / 1000000, p); 212 212 break; 213 213 } 214 214 return ret;

+1

include/uapi/linux/Kbuild

··· 62 62 header-y += ax25.h 63 63 header-y += b1lli.h 64 64 header-y += baycom.h 65 + header-y += bcm933xx_hcs.h 65 66 header-y += bfs_fs.h 66 67 header-y += binfmts.h 67 68 header-y += blkpg.h

+24

include/uapi/linux/bcm933xx_hcs.h

··· 1 + /* 2 + * Broadcom Cable Modem firmware format 3 + */ 4 + 5 + #ifndef __BCM933XX_HCS_H 6 + #define __BCM933XX_HCS_H 7 + 8 + #include <linux/types.h> 9 + 10 + struct bcm_hcs { 11 + __u16 magic; 12 + __u16 control; 13 + __u16 rev_maj; 14 + __u16 rev_min; 15 + __u32 build_date; 16 + __u32 filelen; 17 + __u32 ldaddress; 18 + char filename[64]; 19 + __u16 hcs; 20 + __u16 her_znaet_chto; 21 + __u32 crc; 22 + }; 23 + 24 + #endif /* __BCM933XX_HCS */

-12

kernel/irq/irqdomain.c

··· 475 475 476 476 domain = controller ? irq_find_host(controller) : irq_default_domain; 477 477 if (!domain) { 478 - #ifdef CONFIG_MIPS 479 - /* 480 - * Workaround to avoid breaking interrupt controller drivers 481 - * that don't yet register an irq_domain. This is temporary 482 - * code. ~~~gcl, Feb 24, 2012 483 - * 484 - * Scheduled for removal in Linux v3.6. That should be enough 485 - * time. 486 - */ 487 - if (intsize > 0) 488 - return intspec[0]; 489 - #endif 490 478 pr_warn("no irq domain found for %s !\n", 491 479 of_node_full_name(controller)); 492 480 return 0;

+1 -1

lib/Kconfig.debug

··· 1347 1347 depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT 1348 1348 depends on !X86_64 1349 1349 select STACKTRACE 1350 - select FRAME_POINTER if !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND 1350 + select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND 1351 1351 help 1352 1352 Provide stacktrace filter for fault-injection capabilities 1353 1353

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