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phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()

While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk
support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set
on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
the frequency of the reference clock for the USB2.0 phy instead.

I stumbled across this while adding support for the Google Tensor
gs101, but this should apply to E850 just the same.

Do so.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507-samsung-usb-phy-fixes-v1-5-4ccba5afa7cc@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

André Draszik and committed by
Vinod Koul d14c1461 32b2495e

+29
+29
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 8 8 * Author: Vivek Gautam <gautam.vivek@samsung.com> 9 9 */ 10 10 11 + #include <linux/bitfield.h> 11 12 #include <linux/clk.h> 12 13 #include <linux/delay.h> 13 14 #include <linux/io.h> ··· 141 140 #define CLKRST_PHY_SW_RST BIT(3) 142 141 #define CLKRST_PORT_RST BIT(1) 143 142 #define CLKRST_LINK_SW_RST BIT(0) 143 + 144 + #define EXYNOS850_DRD_SSPPLLCTL 0x30 145 + #define SSPPLLCTL_FSEL GENMASK(2, 0) 144 146 145 147 #define EXYNOS850_DRD_UTMI 0x50 146 148 #define UTMI_FORCE_VBUSVALID BIT(5) ··· 776 772 reg = readl(regs_base + EXYNOS850_DRD_HSP); 777 773 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; 778 774 writel(reg, regs_base + EXYNOS850_DRD_HSP); 775 + 776 + reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); 777 + reg &= ~SSPPLLCTL_FSEL; 778 + switch (phy_drd->extrefclk) { 779 + case EXYNOS5_FSEL_50MHZ: 780 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); 781 + break; 782 + case EXYNOS5_FSEL_26MHZ: 783 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); 784 + break; 785 + case EXYNOS5_FSEL_24MHZ: 786 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); 787 + break; 788 + case EXYNOS5_FSEL_20MHZ: 789 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); 790 + break; 791 + case EXYNOS5_FSEL_19MHZ2: 792 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); 793 + break; 794 + default: 795 + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", 796 + phy_drd->extrefclk); 797 + break; 798 + } 799 + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); 779 800 780 801 /* Power up PHY analog blocks */ 781 802 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);