Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux
Pull intel kabylake drm fixes from Dave Airlie:
"As mentioned Intel has gathered all the Kabylake fixes from -next,
which we've enabled in 4.7 for the first time, these are pretty much
limited in scope to only affects kabylake, which is hw that isn't
shipping yet. So I'm mostly okay with it going in now.
If we don't land this, it might be a good idea to disable kabylake
support in 4.7 before we ship"
* tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux: (28 commits)
drm/i915/kbl: Introduce the first official DMC for Kabylake.
drm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate
drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
drm/i195/fbc: Add WaFbcNukeOnHostModify
drm/i915/gen9: Add WaFbcWakeMemOn
drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
drm/i915/gen9: Add WaEnableChickenDCPR
drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
drm/i915/kbl: Add WaDisableGafsUnitClkGating
drm/i915/kbl: Add WaForGAMHang
drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
drm/i915/kbl: Add WaDisableDynamicCreditSharing
drm/i915/kbl: Add WaDisableGamClockGating
drm/i915/gen9: Enable must set chicken bits in config0 reg
drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
drm/i915/kbl: Add WaDisableSDEUnitClockGating
drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
drm/i915/kbl: Add WaEnableGapsTsvCreditFix
...
+295
-61
+4
drivers/gpu/drm/i915/i915_drv.c
+4
drivers/gpu/drm/i915/i915_drv.c
···
512
512
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
513
513
WARN_ON(!IS_SKYLAKE(dev) &&
514
514
!IS_KABYLAKE(dev));
515
+
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
516
+
dev_priv->pch_type = PCH_KBP;
517
+
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
518
+
WARN_ON(!IS_KABYLAKE(dev));
515
519
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
516
520
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
517
521
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
+12
drivers/gpu/drm/i915/i915_drv.h
+12
drivers/gpu/drm/i915/i915_drv.h
···
990
990
PCH_CPT, /* Cougarpoint PCH */
991
991
PCH_LPT, /* Lynxpoint PCH */
992
992
PCH_SPT, /* Sunrisepoint PCH */
993
+
PCH_KBP, /* Kabypoint PCH */
993
994
PCH_NOP,
994
995
};
995
996
···
2601
2600
2602
2601
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2603
2602
2603
+
#define KBL_REVID_A0 0x0
2604
+
#define KBL_REVID_B0 0x1
2605
+
#define KBL_REVID_C0 0x2
2606
+
#define KBL_REVID_D0 0x3
2607
+
#define KBL_REVID_E0 0x4
2608
+
2609
+
#define IS_KBL_REVID(p, since, until) \
2610
+
(IS_KABYLAKE(p) && IS_REVID(p, since, until))
2611
+
2604
2612
/*
2605
2613
* The genX designation typically refers to the render engine, so render
2606
2614
* capability related checks should use IS_GEN, while display and other checks
···
2718
2708
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2719
2709
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2720
2710
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2711
+
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2721
2712
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2722
2713
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2723
2714
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2724
2715
2725
2716
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2717
+
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2726
2718
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2727
2719
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2728
2720
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+4
-2
drivers/gpu/drm/i915/i915_gem_stolen.c
+4
-2
drivers/gpu/drm/i915/i915_gem_stolen.c
···
55
55
return -ENODEV;
56
56
57
57
/* See the comment at the drm_mm_init() call for more about this check.
58
-
* WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
59
-
if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096)
58
+
* WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)
59
+
*/
60
+
if (start < 4096 && (IS_GEN8(dev_priv) ||
61
+
IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
60
62
start = 4096;
61
63
62
64
mutex_lock(&dev_priv->mm.stolen_lock);
+2
-2
drivers/gpu/drm/i915/i915_irq.c
+2
-2
drivers/gpu/drm/i915/i915_irq.c
···
2471
2471
I915_WRITE(SDEIIR, iir);
2472
2472
ret = IRQ_HANDLED;
2473
2473
2474
-
if (HAS_PCH_SPT(dev_priv))
2474
+
if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2475
2475
spt_irq_handler(dev, iir);
2476
2476
else
2477
2477
cpt_irq_handler(dev, iir);
···
4661
4661
dev->driver->disable_vblank = gen8_disable_vblank;
4662
4662
if (IS_BROXTON(dev))
4663
4663
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4664
-
else if (HAS_PCH_SPT(dev))
4664
+
else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4665
4665
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4666
4666
else
4667
4667
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+21
drivers/gpu/drm/i915/i915_reg.h
+21
drivers/gpu/drm/i915/i915_reg.h
···
220
220
#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
221
221
#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
222
222
223
+
#define GEN8_CONFIG0 _MMIO(0xD00)
224
+
#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
225
+
223
226
#define GAC_ECO_BITS _MMIO(0x14090)
224
227
#define ECOBITS_SNB_BIT (1<<13)
225
228
#define ECOBITS_PPGTT_CACHE64B (3<<8)
···
1672
1669
1673
1670
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
1674
1671
1672
+
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
1673
+
#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
1674
+
1675
1675
#if 0
1676
1676
#define PRB0_TAIL _MMIO(0x2030)
1677
1677
#define PRB0_HEAD _MMIO(0x2034)
···
1809
1803
#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1810
1804
#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1811
1805
#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
1806
+
1807
+
/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
1808
+
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
1809
+
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
1812
1810
1813
1811
/* WaClearTdlStateAckDirtyBits */
1814
1812
#define GEN8_STATE_ACK _MMIO(0x20F0)
···
2210
2200
#define ILK_DPFC_STATUS _MMIO(0x43210)
2211
2201
#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2212
2202
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
2203
+
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
2204
+
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
2213
2205
#define ILK_FBC_RT_BASE _MMIO(0x2128)
2214
2206
#define ILK_FBC_RT_VALID (1<<0)
2215
2207
#define SNB_FBC_FRONT_BUFFER (1<<1)
···
6043
6031
#define CHICKEN_PAR1_1 _MMIO(0x42080)
6044
6032
#define DPA_MASK_VBLANK_SRD (1 << 15)
6045
6033
#define FORCE_ARB_IDLE_PLANES (1 << 14)
6034
+
#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
6046
6035
6047
6036
#define _CHICKEN_PIPESL_1_A 0x420b0
6048
6037
#define _CHICKEN_PIPESL_1_B 0x420b4
···
6052
6039
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
6053
6040
6054
6041
#define DISP_ARB_CTL _MMIO(0x45000)
6042
+
#define DISP_FBC_MEMORY_WAKE (1<<31)
6055
6043
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
6056
6044
#define DISP_FBC_WM_DIS (1<<15)
6057
6045
#define DISP_ARB_CTL2 _MMIO(0x45004)
···
6065
6051
#define WAIT_FOR_PCH_FLR_ACK (1<<0)
6066
6052
#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
6067
6053
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
6054
+
6055
+
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6056
+
#define MASK_WAKEMEM (1<<13)
6068
6057
6069
6058
#define SKL_DFSM _MMIO(0x51000)
6070
6059
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
···
6086
6069
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
6087
6070
6088
6071
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
6072
+
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
6089
6073
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
6090
6074
6091
6075
/* GEN7 chicken */
···
6094
6076
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
6095
6077
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
6096
6078
#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
6079
+
# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
6097
6080
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
6098
6081
6099
6082
#define HIZ_CHICKEN _MMIO(0x7018)
···
6940
6921
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
6941
6922
6942
6923
#define GEN6_UCGCTL1 _MMIO(0x9400)
6924
+
# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
6943
6925
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6944
6926
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6945
6927
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
···
6957
6937
6958
6938
#define GEN7_UCGCTL4 _MMIO(0x940c)
6959
6939
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6940
+
#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
6960
6941
6961
6942
#define GEN6_RCGCTL1 _MMIO(0x9410)
6962
6943
#define GEN6_RCGCTL2 _MMIO(0x9414)
+19
-11
drivers/gpu/drm/i915/intel_csr.c
+19
-11
drivers/gpu/drm/i915/intel_csr.c
···
41
41
* be moved to FW_FAILED.
42
42
*/
43
43
44
+
#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
45
+
MODULE_FIRMWARE(I915_CSR_KBL);
46
+
#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
47
+
44
48
#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
49
+
MODULE_FIRMWARE(I915_CSR_SKL);
50
+
#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
51
+
45
52
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
53
+
MODULE_FIRMWARE(I915_CSR_BXT);
54
+
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
46
55
47
56
#define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
48
57
49
-
MODULE_FIRMWARE(I915_CSR_SKL);
50
-
MODULE_FIRMWARE(I915_CSR_BXT);
51
58
52
-
#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
53
-
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
59
+
54
60
55
61
#define CSR_MAX_FW_SIZE 0x2FFF
56
62
#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
···
175
169
char substepping;
176
170
};
177
171
178
-
/*
179
-
* Kabylake derivated from Skylake H0, so SKL H0
180
-
* is the right firmware for KBL A0 (revid 0).
181
-
*/
182
172
static const struct stepping_info kbl_stepping_info[] = {
183
-
{'H', '0'}, {'I', '0'}
173
+
{'A', '0'}, {'B', '0'}, {'C', '0'},
174
+
{'D', '0'}, {'E', '0'}, {'F', '0'},
175
+
{'G', '0'}, {'H', '0'}, {'I', '0'},
184
176
};
185
177
186
178
static const struct stepping_info skl_stepping_info[] = {
···
302
298
303
299
csr->version = css_header->version;
304
300
305
-
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
301
+
if (IS_KABYLAKE(dev_priv)) {
302
+
required_min_version = KBL_CSR_VERSION_REQUIRED;
303
+
} else if (IS_SKYLAKE(dev_priv)) {
306
304
required_min_version = SKL_CSR_VERSION_REQUIRED;
307
305
} else if (IS_BROXTON(dev_priv)) {
308
306
required_min_version = BXT_CSR_VERSION_REQUIRED;
···
452
446
if (!HAS_CSR(dev_priv))
453
447
return;
454
448
455
-
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
449
+
if (IS_KABYLAKE(dev_priv))
450
+
csr->fw_path = I915_CSR_KBL;
451
+
else if (IS_SKYLAKE(dev_priv))
456
452
csr->fw_path = I915_CSR_SKL;
457
453
else if (IS_BROXTON(dev_priv))
458
454
csr->fw_path = I915_CSR_BXT;
+55
-4
drivers/gpu/drm/i915/intel_lrc.c
+55
-4
drivers/gpu/drm/i915/intel_lrc.c
···
1103
1103
uint32_t *const batch,
1104
1104
uint32_t index)
1105
1105
{
1106
+
struct drm_i915_private *dev_priv = engine->dev->dev_private;
1106
1107
uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
1107
1108
1108
1109
/*
1109
-
* WaDisableLSQCROPERFforOCL:skl
1110
+
* WaDisableLSQCROPERFforOCL:skl,kbl
1110
1111
* This WA is implemented in skl_init_clock_gating() but since
1111
1112
* this batch updates GEN8_L3SQCREG4 with default value we need to
1112
1113
* set this bit here to retain the WA during flush.
1113
1114
*/
1114
-
if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1115
+
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
1116
+
IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1115
1117
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
1116
1118
1117
1119
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
···
1275
1273
{
1276
1274
int ret;
1277
1275
struct drm_device *dev = engine->dev;
1276
+
struct drm_i915_private *dev_priv = dev->dev_private;
1278
1277
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1279
1278
1280
1279
/* WaDisableCtxRestoreArbitration:skl,bxt */
···
1289
1286
return ret;
1290
1287
index = ret;
1291
1288
1289
+
/* WaClearSlmSpaceAtContextSwitch:kbl */
1290
+
/* Actual scratch location is at 128 bytes offset */
1291
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1292
+
uint32_t scratch_addr
1293
+
= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1294
+
1295
+
wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1296
+
wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1297
+
PIPE_CONTROL_GLOBAL_GTT_IVB |
1298
+
PIPE_CONTROL_CS_STALL |
1299
+
PIPE_CONTROL_QW_WRITE));
1300
+
wa_ctx_emit(batch, index, scratch_addr);
1301
+
wa_ctx_emit(batch, index, 0);
1302
+
wa_ctx_emit(batch, index, 0);
1303
+
wa_ctx_emit(batch, index, 0);
1304
+
}
1292
1305
/* Pad to end of cacheline */
1293
1306
while (index % CACHELINE_DWORDS)
1294
1307
wa_ctx_emit(batch, index, MI_NOOP);
···
1706
1687
struct intel_ringbuffer *ringbuf = request->ringbuf;
1707
1688
struct intel_engine_cs *engine = ringbuf->engine;
1708
1689
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1709
-
bool vf_flush_wa = false;
1690
+
bool vf_flush_wa = false, dc_flush_wa = false;
1710
1691
u32 flags = 0;
1711
1692
int ret;
1693
+
int len;
1712
1694
1713
1695
flags |= PIPE_CONTROL_CS_STALL;
1714
1696
···
1736
1716
*/
1737
1717
if (IS_GEN9(engine->dev))
1738
1718
vf_flush_wa = true;
1719
+
1720
+
/* WaForGAMHang:kbl */
1721
+
if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1722
+
dc_flush_wa = true;
1739
1723
}
1740
1724
1741
-
ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
1725
+
len = 6;
1726
+
1727
+
if (vf_flush_wa)
1728
+
len += 6;
1729
+
1730
+
if (dc_flush_wa)
1731
+
len += 12;
1732
+
1733
+
ret = intel_ring_begin(request, len);
1742
1734
if (ret)
1743
1735
return ret;
1744
1736
···
1763
1731
intel_logical_ring_emit(ringbuf, 0);
1764
1732
}
1765
1733
1734
+
if (dc_flush_wa) {
1735
+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1736
+
intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
1737
+
intel_logical_ring_emit(ringbuf, 0);
1738
+
intel_logical_ring_emit(ringbuf, 0);
1739
+
intel_logical_ring_emit(ringbuf, 0);
1740
+
intel_logical_ring_emit(ringbuf, 0);
1741
+
}
1742
+
1766
1743
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1767
1744
intel_logical_ring_emit(ringbuf, flags);
1768
1745
intel_logical_ring_emit(ringbuf, scratch_addr);
1769
1746
intel_logical_ring_emit(ringbuf, 0);
1770
1747
intel_logical_ring_emit(ringbuf, 0);
1771
1748
intel_logical_ring_emit(ringbuf, 0);
1749
+
1750
+
if (dc_flush_wa) {
1751
+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1752
+
intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
1753
+
intel_logical_ring_emit(ringbuf, 0);
1754
+
intel_logical_ring_emit(ringbuf, 0);
1755
+
intel_logical_ring_emit(ringbuf, 0);
1756
+
intel_logical_ring_emit(ringbuf, 0);
1757
+
}
1758
+
1772
1759
intel_logical_ring_advance(ringbuf);
1773
1760
1774
1761
return 0;
+2
-1
drivers/gpu/drm/i915/intel_panel.c
+2
-1
drivers/gpu/drm/i915/intel_panel.c
···
1731
1731
panel->backlight.set = bxt_set_backlight;
1732
1732
panel->backlight.get = bxt_get_backlight;
1733
1733
panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
1734
-
} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv)) {
1734
+
} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
1735
+
HAS_PCH_KBP(dev_priv)) {
1735
1736
panel->backlight.setup = lpt_setup_backlight;
1736
1737
panel->backlight.enable = lpt_enable_backlight;
1737
1738
panel->backlight.disable = lpt_disable_backlight;
+62
-2
drivers/gpu/drm/i915/intel_pm.c
+62
-2
drivers/gpu/drm/i915/intel_pm.c
···
54
54
#define INTEL_RC6p_ENABLE (1<<1)
55
55
#define INTEL_RC6pp_ENABLE (1<<2)
56
56
57
+
static void gen9_init_clock_gating(struct drm_device *dev)
58
+
{
59
+
struct drm_i915_private *dev_priv = dev->dev_private;
60
+
61
+
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62
+
I915_WRITE(CHICKEN_PAR1_1,
63
+
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
+
65
+
I915_WRITE(GEN8_CONFIG0,
66
+
I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67
+
68
+
/* WaEnableChickenDCPR:skl,bxt,kbl */
69
+
I915_WRITE(GEN8_CHICKEN_DCPR_1,
70
+
I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
71
+
72
+
/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73
+
/* WaFbcWakeMemOn:skl,bxt,kbl */
74
+
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75
+
DISP_FBC_WM_DIS |
76
+
DISP_FBC_MEMORY_WAKE);
77
+
78
+
/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79
+
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80
+
ILK_DPFC_DISABLE_DUMMY0);
81
+
}
82
+
57
83
static void bxt_init_clock_gating(struct drm_device *dev)
58
84
{
59
85
struct drm_i915_private *dev_priv = dev->dev_private;
86
+
87
+
gen9_init_clock_gating(dev);
60
88
61
89
/* WaDisableSDEUnitClockGating:bxt */
62
90
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
···
6726
6698
}
6727
6699
}
6728
6700
6701
+
static void kabylake_init_clock_gating(struct drm_device *dev)
6702
+
{
6703
+
struct drm_i915_private *dev_priv = dev->dev_private;
6704
+
6705
+
gen9_init_clock_gating(dev);
6706
+
6707
+
/* WaDisableSDEUnitClockGating:kbl */
6708
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6709
+
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6710
+
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6711
+
6712
+
/* WaDisableGamClockGating:kbl */
6713
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6714
+
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6715
+
GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
6716
+
6717
+
/* WaFbcNukeOnHostModify:kbl */
6718
+
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
6719
+
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
6720
+
}
6721
+
6722
+
static void skylake_init_clock_gating(struct drm_device *dev)
6723
+
{
6724
+
struct drm_i915_private *dev_priv = dev->dev_private;
6725
+
6726
+
gen9_init_clock_gating(dev);
6727
+
6728
+
/* WaFbcNukeOnHostModify:skl */
6729
+
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
6730
+
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
6731
+
}
6732
+
6729
6733
static void broadwell_init_clock_gating(struct drm_device *dev)
6730
6734
{
6731
6735
struct drm_i915_private *dev_priv = dev->dev_private;
···
7223
7163
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7224
7164
{
7225
7165
if (IS_SKYLAKE(dev_priv))
7226
-
dev_priv->display.init_clock_gating = nop_init_clock_gating;
7166
+
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7227
7167
else if (IS_KABYLAKE(dev_priv))
7228
-
dev_priv->display.init_clock_gating = nop_init_clock_gating;
7168
+
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7229
7169
else if (IS_BROXTON(dev_priv))
7230
7170
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7231
7171
else if (IS_BROADWELL(dev_priv))
+114
-39
drivers/gpu/drm/i915/intel_ringbuffer.c
+114
-39
drivers/gpu/drm/i915/intel_ringbuffer.c
···
913
913
{
914
914
struct drm_device *dev = engine->dev;
915
915
struct drm_i915_private *dev_priv = dev->dev_private;
916
-
uint32_t tmp;
917
916
int ret;
918
917
919
-
/* WaEnableLbsSlaRetryTimerDecrement:skl */
918
+
/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
919
+
I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
920
+
921
+
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
920
922
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
921
923
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
922
924
923
-
/* WaDisableKillLogic:bxt,skl */
925
+
/* WaDisableKillLogic:bxt,skl,kbl */
924
926
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
925
927
ECOCHK_DIS_TLB);
926
928
927
-
/* WaClearFlowControlGpgpuContextSave:skl,bxt */
928
-
/* WaDisablePartialInstShootdown:skl,bxt */
929
+
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
930
+
/* WaDisablePartialInstShootdown:skl,bxt,kbl */
929
931
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930
932
FLOW_CONTROL_ENABLE |
931
933
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
932
934
933
-
/* Syncing dependencies between camera and graphics:skl,bxt */
935
+
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
934
936
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
935
937
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
936
938
···
954
952
*/
955
953
}
956
954
957
-
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
958
-
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
955
+
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
956
+
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
959
957
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
960
958
GEN9_ENABLE_YV12_BUGFIX |
961
959
GEN9_ENABLE_GPGPU_PREEMPTION);
962
960
963
-
/* Wa4x4STCOptimizationDisable:skl,bxt */
964
-
/* WaDisablePartialResolveInVc:skl,bxt */
961
+
/* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
962
+
/* WaDisablePartialResolveInVc:skl,bxt,kbl */
965
963
WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
966
964
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
967
965
968
-
/* WaCcsTlbPrefetchDisable:skl,bxt */
966
+
/* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
969
967
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
970
968
GEN9_CCS_TLB_PREFETCH_ENABLE);
971
969
···
975
973
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
976
974
PIXEL_MASK_CAMMING_DISABLE);
977
975
978
-
/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
979
-
tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
980
-
if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
981
-
IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
982
-
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
983
-
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
976
+
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
977
+
WA_SET_BIT_MASKED(HDC_CHICKEN0,
978
+
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
979
+
HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
984
980
985
-
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
986
-
if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
981
+
/* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
982
+
* both tied to WaForceContextSaveRestoreNonCoherent
983
+
* in some hsds for skl. We keep the tie for all gen9. The
984
+
* documentation is a bit hazy and so we want to get common behaviour,
985
+
* even though there is no clear evidence we would need both on kbl/bxt.
986
+
* This area has been source of system hangs so we play it safe
987
+
* and mimic the skl regardless of what bspec says.
988
+
*
989
+
* Use Force Non-Coherent whenever executing a 3D context. This
990
+
* is a workaround for a possible hang in the unlikely event
991
+
* a TLB invalidation occurs during a PSD flush.
992
+
*/
993
+
994
+
/* WaForceEnableNonCoherent:skl,bxt,kbl */
995
+
WA_SET_BIT_MASKED(HDC_CHICKEN0,
996
+
HDC_FORCE_NON_COHERENT);
997
+
998
+
/* WaDisableHDCInvalidation:skl,bxt,kbl */
999
+
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1000
+
BDW_DISABLE_HDC_INVALIDATION);
1001
+
1002
+
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1003
+
if (IS_SKYLAKE(dev_priv) ||
1004
+
IS_KABYLAKE(dev_priv) ||
1005
+
IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
987
1006
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
988
1007
GEN8_SAMPLER_POWER_BYPASS_DIS);
989
1008
990
-
/* WaDisableSTUnitPowerOptimization:skl,bxt */
1009
+
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
991
1010
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
992
1011
993
-
/* WaOCLCoherentLineFlush:skl,bxt */
1012
+
/* WaOCLCoherentLineFlush:skl,bxt,kbl */
994
1013
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
995
1014
GEN8_LQSC_FLUSH_COHERENT_LINES));
996
1015
997
-
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1016
+
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1017
+
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1018
+
if (ret)
1019
+
return ret;
1020
+
1021
+
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
998
1022
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
999
1023
if (ret)
1000
1024
return ret;
1001
1025
1002
-
/* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1026
+
/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1003
1027
ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1004
1028
if (ret)
1005
1029
return ret;
···
1120
1092
WA_SET_BIT_MASKED(HIZ_CHICKEN,
1121
1093
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1122
1094
1123
-
/* This is tied to WaForceContextSaveRestoreNonCoherent */
1124
-
if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1125
-
/*
1126
-
*Use Force Non-Coherent whenever executing a 3D context. This
1127
-
* is a workaround for a possible hang in the unlikely event
1128
-
* a TLB invalidation occurs during a PSD flush.
1129
-
*/
1130
-
/* WaForceEnableNonCoherent:skl */
1131
-
WA_SET_BIT_MASKED(HDC_CHICKEN0,
1132
-
HDC_FORCE_NON_COHERENT);
1133
-
1134
-
/* WaDisableHDCInvalidation:skl */
1135
-
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1136
-
BDW_DISABLE_HDC_INVALIDATION);
1137
-
}
1138
-
1139
1095
/* WaBarrierPerformanceFixDisable:skl */
1140
1096
if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1141
1097
WA_SET_BIT_MASKED(HDC_CHICKEN0,
···
1131
1119
WA_SET_BIT_MASKED(
1132
1120
GEN7_HALF_SLICE_CHICKEN1,
1133
1121
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1122
+
1123
+
/* WaDisableGafsUnitClkGating:skl */
1124
+
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1134
1125
1135
1126
/* WaDisableLSQCROPERFforOCL:skl */
1136
1127
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
···
1189
1174
return ret;
1190
1175
}
1191
1176
1177
+
/* WaInsertDummyPushConstPs:bxt */
1178
+
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1179
+
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1180
+
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1181
+
1182
+
return 0;
1183
+
}
1184
+
1185
+
static int kbl_init_workarounds(struct intel_engine_cs *engine)
1186
+
{
1187
+
struct drm_i915_private *dev_priv = engine->dev->dev_private;
1188
+
int ret;
1189
+
1190
+
ret = gen9_init_workarounds(engine);
1191
+
if (ret)
1192
+
return ret;
1193
+
1194
+
/* WaEnableGapsTsvCreditFix:kbl */
1195
+
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1196
+
GEN9_GAPS_TSV_CREDIT_DISABLE));
1197
+
1198
+
/* WaDisableDynamicCreditSharing:kbl */
1199
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1200
+
WA_SET_BIT(GAMT_CHKN_BIT_REG,
1201
+
GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1202
+
1203
+
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1204
+
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1205
+
WA_SET_BIT_MASKED(HDC_CHICKEN0,
1206
+
HDC_FENCE_DEST_SLM_DISABLE);
1207
+
1208
+
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1209
+
* involving this register should also be added to WA batch as required.
1210
+
*/
1211
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1212
+
/* WaDisableLSQCROPERFforOCL:kbl */
1213
+
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1214
+
GEN8_LQSC_RO_PERF_DIS);
1215
+
1216
+
/* WaInsertDummyPushConstPs:kbl */
1217
+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1218
+
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1219
+
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1220
+
1221
+
/* WaDisableGafsUnitClkGating:kbl */
1222
+
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1223
+
1224
+
/* WaDisableSbeCacheDispatchPortSharing:kbl */
1225
+
WA_SET_BIT_MASKED(
1226
+
GEN7_HALF_SLICE_CHICKEN1,
1227
+
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1228
+
1229
+
/* WaDisableLSQCROPERFforOCL:kbl */
1230
+
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1231
+
if (ret)
1232
+
return ret;
1233
+
1192
1234
return 0;
1193
1235
}
1194
1236
···
1270
1198
1271
1199
if (IS_BROXTON(dev))
1272
1200
return bxt_init_workarounds(engine);
1201
+
1202
+
if (IS_KABYLAKE(dev_priv))
1203
+
return kbl_init_workarounds(engine);
1273
1204
1274
1205
return 0;
1275
1206
}