tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'riscv-for-linus-6.8-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

- detect ".option arch" support on not-yet-released LLVM builds

- fix missing TLB flush when modifying non-leaf PTEs

- fixes for T-Head custom extensions

- fix for systems with the legacy PMU, that manifests as a crash on
kernels built without SBI PMU support

- fix for systems that clear *envcfg on suspend, which manifests as
cbo.zero trapping after resume

- fixes for Svnapot systems, including removing Svnapot support for
huge vmalloc/vmap regions

* tag 'riscv-for-linus-6.8-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Sparse-Memory/vmemmap out-of-bounds fix
riscv: Fix pte_leaf_size() for NAPOT
Revert "riscv: mm: support Svnapot in huge vmap"
riscv: Save/restore envcfg CSR during CPU suspend
riscv: Add a custom ISA extension for the [ms]envcfg CSR
riscv: Fix enabling cbo.zero when running in M-mode
perf: RISCV: Fix panic on pmu overflow handler
MAINTAINERS: Update SiFive driver maintainers
drivers: perf: ctr_get_width function for legacy is not defined
drivers: perf: added capabilities for legacy PMU
RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs
riscv: Fix build error if !CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
riscv: add CALLER_ADDRx support
RISC-V: Drop invalid test from CONFIG_AS_HAS_OPTION_ARCH
kbuild: Add -Wa,--fatal-warnings to as-instr invocation
riscv: tlb: fix __p*d_free_tlb()

Linus Torvalds d17468c6 5870ba3d

+146 -114
+6 -25
MAINTAINERS
··· 1395 1395 1396 1396 ANALOGBITS PLL LIBRARIES 1397 1397 M: Paul Walmsley <paul.walmsley@sifive.com> 1398 + M: Samuel Holland <samuel.holland@sifive.com> 1398 1399 S: Supported 1399 1400 F: drivers/clk/analogbits/* 1400 1401 F: include/linux/clk/analogbits* ··· 16744 16743 PCI DRIVER FOR FU740 16745 16744 M: Paul Walmsley <paul.walmsley@sifive.com> 16746 16745 M: Greentime Hu <greentime.hu@sifive.com> 16746 + M: Samuel Holland <samuel.holland@sifive.com> 16747 16747 L: linux-pci@vger.kernel.org 16748 16748 S: Maintained 16749 16749 F: Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml ··· 19990 19988 F: drivers/watchdog/simatic-ipc-wdt.c 19991 19989 19992 19990 SIFIVE DRIVERS 19993 - M: Palmer Dabbelt <palmer@dabbelt.com> 19994 19991 M: Paul Walmsley <paul.walmsley@sifive.com> 19992 + M: Samuel Holland <samuel.holland@sifive.com> 19995 19993 L: linux-riscv@lists.infradead.org 19996 19994 S: Supported 19997 - N: sifive 19998 - K: [^@]sifive 19999 - 20000 - SIFIVE CACHE DRIVER 20001 - M: Conor Dooley <conor@kernel.org> 20002 - L: linux-riscv@lists.infradead.org 20003 - S: Maintained 20004 - F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml 20005 - F: drivers/cache/sifive_ccache.c 20006 - 20007 - SIFIVE FU540 SYSTEM-ON-CHIP 20008 - M: Paul Walmsley <paul.walmsley@sifive.com> 20009 - M: Palmer Dabbelt <palmer@dabbelt.com> 20010 - L: linux-riscv@lists.infradead.org 20011 - S: Supported 20012 - T: git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git 20013 - N: fu540 20014 - K: fu540 20015 - 20016 - SIFIVE PDMA DRIVER 20017 - M: Green Wan <green.wan@sifive.com> 20018 - S: Maintained 20019 - F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml 20020 19995 F: drivers/dma/sf-pdma/ 20021 - 19996 + N: sifive 19997 + K: fu[57]40 19998 + K: [^@]sifive 20022 19999 20023 20000 SILEAD TOUCHSCREEN DRIVER 20024 20001 M: Hans de Goede <hdegoede@redhat.com>
-1
arch/riscv/Kconfig
··· 315 315 # https://reviews.llvm.org/D123515 316 316 def_bool y 317 317 depends on $(as-instr, .option arch$(comma) +m) 318 - depends on !$(as-instr, .option arch$(comma) -i) 319 318 320 319 source "arch/riscv/Kconfig.socs" 321 320 source "arch/riscv/Kconfig.errata"
+2
arch/riscv/include/asm/csr.h
··· 424 424 # define CSR_STATUS CSR_MSTATUS 425 425 # define CSR_IE CSR_MIE 426 426 # define CSR_TVEC CSR_MTVEC 427 + # define CSR_ENVCFG CSR_MENVCFG 427 428 # define CSR_SCRATCH CSR_MSCRATCH 428 429 # define CSR_EPC CSR_MEPC 429 430 # define CSR_CAUSE CSR_MCAUSE ··· 449 448 # define CSR_STATUS CSR_SSTATUS 450 449 # define CSR_IE CSR_SIE 451 450 # define CSR_TVEC CSR_STVEC 451 + # define CSR_ENVCFG CSR_SENVCFG 452 452 # define CSR_SCRATCH CSR_SSCRATCH 453 453 # define CSR_EPC CSR_SEPC 454 454 # define CSR_CAUSE CSR_SCAUSE
+5
arch/riscv/include/asm/ftrace.h
··· 25 25 26 26 #define ARCH_SUPPORTS_FTRACE_OPS 1 27 27 #ifndef __ASSEMBLY__ 28 + 29 + extern void *return_address(unsigned int level); 30 + 31 + #define ftrace_return_address(n) return_address(n) 32 + 28 33 void MCOUNT_NAME(void); 29 34 static inline unsigned long ftrace_call_adjust(unsigned long addr) 30 35 {
+2
arch/riscv/include/asm/hugetlb.h
··· 11 11 } 12 12 #define arch_clear_hugepage_flags arch_clear_hugepage_flags 13 13 14 + #ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION 14 15 bool arch_hugetlb_migration_supported(struct hstate *h); 15 16 #define arch_hugetlb_migration_supported arch_hugetlb_migration_supported 17 + #endif 16 18 17 19 #ifdef CONFIG_RISCV_ISA_SVNAPOT 18 20 #define __HAVE_ARCH_HUGE_PTE_CLEAR
+2
arch/riscv/include/asm/hwcap.h
··· 81 81 #define RISCV_ISA_EXT_ZTSO 72 82 82 #define RISCV_ISA_EXT_ZACAS 73 83 83 84 + #define RISCV_ISA_EXT_XLINUXENVCFG 127 85 + 84 86 #define RISCV_ISA_EXT_MAX 128 85 87 #define RISCV_ISA_EXT_INVALID U32_MAX 86 88
+17 -3
arch/riscv/include/asm/pgalloc.h
··· 95 95 __pud_free(mm, pud); 96 96 } 97 97 98 - #define __pud_free_tlb(tlb, pud, addr) pud_free((tlb)->mm, pud) 98 + #define __pud_free_tlb(tlb, pud, addr) \ 99 + do { \ 100 + if (pgtable_l4_enabled) { \ 101 + pagetable_pud_dtor(virt_to_ptdesc(pud)); \ 102 + tlb_remove_page_ptdesc((tlb), virt_to_ptdesc(pud)); \ 103 + } \ 104 + } while (0) 99 105 100 106 #define p4d_alloc_one p4d_alloc_one 101 107 static inline p4d_t *p4d_alloc_one(struct mm_struct *mm, unsigned long addr) ··· 130 124 __p4d_free(mm, p4d); 131 125 } 132 126 133 - #define __p4d_free_tlb(tlb, p4d, addr) p4d_free((tlb)->mm, p4d) 127 + #define __p4d_free_tlb(tlb, p4d, addr) \ 128 + do { \ 129 + if (pgtable_l5_enabled) \ 130 + tlb_remove_page_ptdesc((tlb), virt_to_ptdesc(p4d)); \ 131 + } while (0) 134 132 #endif /* __PAGETABLE_PMD_FOLDED */ 135 133 136 134 static inline void sync_kernel_mappings(pgd_t *pgd) ··· 159 149 160 150 #ifndef __PAGETABLE_PMD_FOLDED 161 151 162 - #define __pmd_free_tlb(tlb, pmd, addr) pmd_free((tlb)->mm, pmd) 152 + #define __pmd_free_tlb(tlb, pmd, addr) \ 153 + do { \ 154 + pagetable_pmd_dtor(virt_to_ptdesc(pmd)); \ 155 + tlb_remove_page_ptdesc((tlb), virt_to_ptdesc(pmd)); \ 156 + } while (0) 163 157 164 158 #endif /* __PAGETABLE_PMD_FOLDED */ 165 159
+1 -1
arch/riscv/include/asm/pgtable-64.h
··· 136 136 * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable 137 137 */ 138 138 #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60)) 139 - #define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60)) 139 + #define _PAGE_NOCACHE_THEAD ((1UL << 61) | (1UL << 60)) 140 140 #define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60)) 141 141 #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) 142 142
+5 -1
arch/riscv/include/asm/pgtable.h
··· 84 84 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel 85 85 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. 86 86 */ 87 - #define vmemmap ((struct page *)VMEMMAP_START) 87 + #define vmemmap ((struct page *)VMEMMAP_START - (phys_ram_base >> PAGE_SHIFT)) 88 88 89 89 #define PCI_IO_SIZE SZ_16M 90 90 #define PCI_IO_END VMEMMAP_START ··· 438 438 { 439 439 return pte; 440 440 } 441 + 442 + #define pte_leaf_size(pte) (pte_napot(pte) ? \ 443 + napot_cont_size(napot_cont_order(pte)) :\ 444 + PAGE_SIZE) 441 445 442 446 #ifdef CONFIG_NUMA_BALANCING 443 447 /*
+1
arch/riscv/include/asm/suspend.h
··· 14 14 struct pt_regs regs; 15 15 /* Saved and restored by high-level functions */ 16 16 unsigned long scratch; 17 + unsigned long envcfg; 17 18 unsigned long tvec; 18 19 unsigned long ie; 19 20 #ifdef CONFIG_MMU
+1 -60
arch/riscv/include/asm/vmalloc.h
··· 19 19 return true; 20 20 } 21 21 22 - #ifdef CONFIG_RISCV_ISA_SVNAPOT 23 - #include <linux/pgtable.h> 22 + #endif 24 23 25 - #define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size 26 - static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end, 27 - u64 pfn, unsigned int max_page_shift) 28 - { 29 - unsigned long map_size = PAGE_SIZE; 30 - unsigned long size, order; 31 - 32 - if (!has_svnapot()) 33 - return map_size; 34 - 35 - for_each_napot_order_rev(order) { 36 - if (napot_cont_shift(order) > max_page_shift) 37 - continue; 38 - 39 - size = napot_cont_size(order); 40 - if (end - addr < size) 41 - continue; 42 - 43 - if (!IS_ALIGNED(addr, size)) 44 - continue; 45 - 46 - if (!IS_ALIGNED(PFN_PHYS(pfn), size)) 47 - continue; 48 - 49 - map_size = size; 50 - break; 51 - } 52 - 53 - return map_size; 54 - } 55 - 56 - #define arch_vmap_pte_supported_shift arch_vmap_pte_supported_shift 57 - static inline int arch_vmap_pte_supported_shift(unsigned long size) 58 - { 59 - int shift = PAGE_SHIFT; 60 - unsigned long order; 61 - 62 - if (!has_svnapot()) 63 - return shift; 64 - 65 - WARN_ON_ONCE(size >= PMD_SIZE); 66 - 67 - for_each_napot_order_rev(order) { 68 - if (napot_cont_size(order) > size) 69 - continue; 70 - 71 - if (!IS_ALIGNED(size, napot_cont_size(order))) 72 - continue; 73 - 74 - shift = napot_cont_shift(order); 75 - break; 76 - } 77 - 78 - return shift; 79 - } 80 - 81 - #endif /* CONFIG_RISCV_ISA_SVNAPOT */ 82 - #endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */ 83 24 #endif /* _ASM_RISCV_VMALLOC_H */
+2
arch/riscv/kernel/Makefile
··· 7 7 CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE) 8 8 CFLAGS_REMOVE_patch.o = $(CC_FLAGS_FTRACE) 9 9 CFLAGS_REMOVE_sbi.o = $(CC_FLAGS_FTRACE) 10 + CFLAGS_REMOVE_return_address.o = $(CC_FLAGS_FTRACE) 10 11 endif 11 12 CFLAGS_syscall_table.o += $(call cc-option,-Wno-override-init,) 12 13 CFLAGS_compat_syscall_table.o += $(call cc-option,-Wno-override-init,) ··· 47 46 obj-y += process.o 48 47 obj-y += ptrace.o 49 48 obj-y += reset.o 49 + obj-y += return_address.o 50 50 obj-y += setup.o 51 51 obj-y += signal.o 52 52 obj-y += syscall_table.o
+28 -3
arch/riscv/kernel/cpufeature.c
··· 24 24 #include <asm/hwprobe.h> 25 25 #include <asm/patch.h> 26 26 #include <asm/processor.h> 27 + #include <asm/sbi.h> 27 28 #include <asm/vector.h> 28 29 29 30 #include "copy-unaligned.h" ··· 203 202 }; 204 203 205 204 /* 205 + * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V 206 + * privileged ISA, the existence of the CSRs is implied by any extension which 207 + * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the 208 + * existence of the CSR, and treat it as a subset of those other extensions. 209 + */ 210 + static const unsigned int riscv_xlinuxenvcfg_exts[] = { 211 + RISCV_ISA_EXT_XLINUXENVCFG 212 + }; 213 + 214 + /* 206 215 * The canonical order of ISA extension names in the ISA string is defined in 207 216 * chapter 27 of the unprivileged specification. 208 217 * ··· 261 250 __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), 262 251 __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), 263 252 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), 264 - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), 265 - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), 253 + __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), 254 + __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), 266 255 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), 267 256 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), 268 257 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), ··· 547 536 set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa); 548 537 set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa); 549 538 set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); 539 + } 540 + 541 + /* 542 + * "V" in ISA strings is ambiguous in practice: it should mean 543 + * just the standard V-1.0 but vendors aren't well behaved. 544 + * Many vendors with T-Head CPU cores which implement the 0.7.1 545 + * version of the vector specification put "v" into their DTs. 546 + * CPU cores with the ratified spec will contain non-zero 547 + * marchid. 548 + */ 549 + if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID && 550 + riscv_cached_marchid(cpu) == 0x0) { 551 + this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; 552 + clear_bit(RISCV_ISA_EXT_v, isainfo->isa); 550 553 } 551 554 552 555 /* ··· 975 950 void riscv_user_isa_enable(void) 976 951 { 977 952 if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) 978 - csr_set(CSR_SENVCFG, ENVCFG_CBZE); 953 + csr_set(CSR_ENVCFG, ENVCFG_CBZE); 979 954 } 980 955 981 956 #ifdef CONFIG_RISCV_ALTERNATIVE
+48
arch/riscv/kernel/return_address.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * This code come from arch/arm64/kernel/return_address.c 4 + * 5 + * Copyright (C) 2023 SiFive. 6 + */ 7 + 8 + #include <linux/export.h> 9 + #include <linux/kprobes.h> 10 + #include <linux/stacktrace.h> 11 + 12 + struct return_address_data { 13 + unsigned int level; 14 + void *addr; 15 + }; 16 + 17 + static bool save_return_addr(void *d, unsigned long pc) 18 + { 19 + struct return_address_data *data = d; 20 + 21 + if (!data->level) { 22 + data->addr = (void *)pc; 23 + return false; 24 + } 25 + 26 + --data->level; 27 + 28 + return true; 29 + } 30 + NOKPROBE_SYMBOL(save_return_addr); 31 + 32 + noinline void *return_address(unsigned int level) 33 + { 34 + struct return_address_data data; 35 + 36 + data.level = level + 3; 37 + data.addr = NULL; 38 + 39 + arch_stack_walk(save_return_addr, &data, current, NULL); 40 + 41 + if (!data.level) 42 + return data.addr; 43 + else 44 + return NULL; 45 + 46 + } 47 + EXPORT_SYMBOL_GPL(return_address); 48 + NOKPROBE_SYMBOL(return_address);
+4
arch/riscv/kernel/suspend.c
··· 15 15 void suspend_save_csrs(struct suspend_context *context) 16 16 { 17 17 context->scratch = csr_read(CSR_SCRATCH); 18 + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) 19 + context->envcfg = csr_read(CSR_ENVCFG); 18 20 context->tvec = csr_read(CSR_TVEC); 19 21 context->ie = csr_read(CSR_IE); 20 22 ··· 38 36 void suspend_restore_csrs(struct suspend_context *context) 39 37 { 40 38 csr_write(CSR_SCRATCH, context->scratch); 39 + if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) 40 + csr_write(CSR_ENVCFG, context->envcfg); 41 41 csr_write(CSR_TVEC, context->tvec); 42 42 csr_write(CSR_IE, context->ie); 43 43
+2
arch/riscv/mm/hugetlbpage.c
··· 426 426 return __hugetlb_valid_size(size); 427 427 } 428 428 429 + #ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION 429 430 bool arch_hugetlb_migration_supported(struct hstate *h) 430 431 { 431 432 return __hugetlb_valid_size(huge_page_size(h)); 432 433 } 434 + #endif 433 435 434 436 #ifdef CONFIG_CONTIG_ALLOC 435 437 static __init int gigantic_pages_init(void)
+5 -13
drivers/perf/riscv_pmu.c
··· 150 150 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); 151 151 struct hw_perf_event *hwc = &event->hw; 152 152 153 - if (!rvpmu->ctr_get_width) 154 - /** 155 - * If the pmu driver doesn't support counter width, set it to default 156 - * maximum allowed by the specification. 157 - */ 158 - cwidth = 63; 159 - else { 160 - if (hwc->idx == -1) 161 - /* Handle init case where idx is not initialized yet */ 162 - cwidth = rvpmu->ctr_get_width(0); 163 - else 164 - cwidth = rvpmu->ctr_get_width(hwc->idx); 165 - } 153 + if (hwc->idx == -1) 154 + /* Handle init case where idx is not initialized yet */ 155 + cwidth = rvpmu->ctr_get_width(0); 156 + else 157 + cwidth = rvpmu->ctr_get_width(hwc->idx); 166 158 167 159 return GENMASK_ULL(cwidth, 0); 168 160 }
+9 -1
drivers/perf/riscv_pmu_legacy.c
··· 37 37 return pmu_legacy_ctr_get_idx(event); 38 38 } 39 39 40 + /* cycle & instret are always 64 bit, one bit less according to SBI spec */ 41 + static int pmu_legacy_ctr_get_width(int idx) 42 + { 43 + return 63; 44 + } 45 + 40 46 static u64 pmu_legacy_read_ctr(struct perf_event *event) 41 47 { 42 48 struct hw_perf_event *hwc = &event->hw; ··· 117 111 pmu->ctr_stop = NULL; 118 112 pmu->event_map = pmu_legacy_event_map; 119 113 pmu->ctr_get_idx = pmu_legacy_ctr_get_idx; 120 - pmu->ctr_get_width = NULL; 114 + pmu->ctr_get_width = pmu_legacy_ctr_get_width; 121 115 pmu->ctr_clear_idx = NULL; 122 116 pmu->ctr_read = pmu_legacy_read_ctr; 123 117 pmu->event_mapped = pmu_legacy_event_mapped; 124 118 pmu->event_unmapped = pmu_legacy_event_unmapped; 125 119 pmu->csr_index = pmu_legacy_csr_index; 120 + pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; 121 + pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE; 126 122 127 123 perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); 128 124 }
+4 -4
drivers/perf/riscv_pmu_sbi.c
··· 512 512 513 513 if (event->hw.idx != -1) 514 514 csr_write(CSR_SCOUNTEREN, 515 - csr_read(CSR_SCOUNTEREN) | (1 << pmu_sbi_csr_index(event))); 515 + csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); 516 516 } 517 517 518 518 static void pmu_sbi_reset_scounteren(void *arg) ··· 521 521 522 522 if (event->hw.idx != -1) 523 523 csr_write(CSR_SCOUNTEREN, 524 - csr_read(CSR_SCOUNTEREN) & ~(1 << pmu_sbi_csr_index(event))); 524 + csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); 525 525 } 526 526 527 527 static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) ··· 731 731 /* compute hardware counter index */ 732 732 hidx = info->csr - CSR_CYCLE; 733 733 /* check if the corresponding bit is set in sscountovf */ 734 - if (!(overflow & (1 << hidx))) 734 + if (!(overflow & BIT(hidx))) 735 735 continue; 736 736 737 737 /* 738 738 * Keep a track of overflowed counters so that they can be started 739 739 * with updated initial value. 740 740 */ 741 - overflowed_ctrs |= 1 << lidx; 741 + overflowed_ctrs |= BIT(lidx); 742 742 hw_evt = &event->hw; 743 743 riscv_pmu_event_update(event); 744 744 perf_sample_data_init(&data, 0, hw_evt->last_period);
+1 -1
scripts/Kconfig.include
··· 33 33 34 34 # $(as-instr,<instr>) 35 35 # Return y if the assembler supports <instr>, n otherwise 36 - as-instr = $(success,printf "%b\n" "$(1)" | $(CC) $(CLANG_FLAGS) -c -x assembler-with-cpp -o /dev/null -) 36 + as-instr = $(success,printf "%b\n" "$(1)" | $(CC) $(CLANG_FLAGS) -Wa$(comma)--fatal-warnings -c -x assembler-with-cpp -o /dev/null -) 37 37 38 38 # check if $(CC) and $(LD) exist 39 39 $(error-if,$(failure,command -v $(CC)),C compiler '$(CC)' not found)
+1 -1
scripts/Makefile.compiler
··· 38 38 # Usage: aflags-y += $(call as-instr,instr,option1,option2) 39 39 40 40 as-instr = $(call try-run,\ 41 - printf "%b\n" "$(1)" | $(CC) -Werror $(CLANG_FLAGS) $(KBUILD_AFLAGS) -c -x assembler-with-cpp -o "$$TMP" -,$(2),$(3)) 41 + printf "%b\n" "$(1)" | $(CC) -Werror $(CLANG_FLAGS) $(KBUILD_AFLAGS) -Wa$(comma)--fatal-warnings -c -x assembler-with-cpp -o "$$TMP" -,$(2),$(3)) 42 42 43 43 # __cc-option 44 44 # Usage: MY_CFLAGS += $(call __cc-option,$(CC),$(MY_CFLAGS),-march=winchip-c6,-march=i586)