Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon:
"I've picked up a handful of arm64 fixes while Catalin's been away, so
here they are. Below is the usual summary, but we have basically have
two cleanups, a fix for an SME crash and a fix for hibernation:
- Fix saving of SME state after SVE vector length is changed
- Fix sparse warnings for missing vDSO function prototypes
- Fix hibernation resume path when kfence is enabled
- Fix field names for the HFGxTR_EL2 register"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/fpsimd: Ensure SME storage is allocated after SVE VL changes
arm64: vdso: Clear common make C=2 warnings
arm64: mm: Make hibernation aware of KFENCE
arm64: Fix HFGxTR_EL2 field naming
+38
-15
+25
-8
arch/arm64/kernel/fpsimd.c
+25
-8
arch/arm64/kernel/fpsimd.c
···
847
847
int vec_set_vector_length(struct task_struct *task, enum vec_type type,
848
848
unsigned long vl, unsigned long flags)
849
849
{
850
+
bool free_sme = false;
851
+
850
852
if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
851
853
PR_SVE_SET_VL_ONEXEC))
852
854
return -EINVAL;
···
899
897
task->thread.fp_type = FP_STATE_FPSIMD;
900
898
}
901
899
902
-
if (system_supports_sme() && type == ARM64_VEC_SME) {
903
-
task->thread.svcr &= ~(SVCR_SM_MASK |
904
-
SVCR_ZA_MASK);
905
-
clear_thread_flag(TIF_SME);
900
+
if (system_supports_sme()) {
901
+
if (type == ARM64_VEC_SME ||
902
+
!(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) {
903
+
/*
904
+
* We are changing the SME VL or weren't using
905
+
* SME anyway, discard the state and force a
906
+
* reallocation.
907
+
*/
908
+
task->thread.svcr &= ~(SVCR_SM_MASK |
909
+
SVCR_ZA_MASK);
910
+
clear_thread_flag(TIF_SME);
911
+
free_sme = true;
912
+
}
906
913
}
907
914
908
915
if (task == current)
909
916
put_cpu_fpsimd_context();
910
917
911
918
/*
912
-
* Force reallocation of task SVE and SME state to the correct
913
-
* size on next use:
919
+
* Free the changed states if they are not in use, SME will be
920
+
* reallocated to the correct size on next use and we just
921
+
* allocate SVE now in case it is needed for use in streaming
922
+
* mode.
914
923
*/
915
-
sve_free(task);
916
-
if (system_supports_sme() && type == ARM64_VEC_SME)
924
+
if (system_supports_sve()) {
925
+
sve_free(task);
926
+
sve_alloc(task, true);
927
+
}
928
+
929
+
if (free_sme)
917
930
sme_free(task);
918
931
919
932
task_set_vl(task, type, vl);
+4
arch/arm64/kernel/vdso/vgettimeofday.c
+4
arch/arm64/kernel/vdso/vgettimeofday.c
···
6
6
*
7
7
*/
8
8
9
+
int __kernel_clock_gettime(clockid_t clock, struct __kernel_timespec *ts);
10
+
int __kernel_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz);
11
+
int __kernel_clock_getres(clockid_t clock_id, struct __kernel_timespec *res);
12
+
9
13
int __kernel_clock_gettime(clockid_t clock,
10
14
struct __kernel_timespec *ts)
11
15
{
+3
-1
arch/arm64/mm/trans_pgd.c
+3
-1
arch/arm64/mm/trans_pgd.c
···
24
24
#include <linux/bug.h>
25
25
#include <linux/mm.h>
26
26
#include <linux/mmzone.h>
27
+
#include <linux/kfence.h>
27
28
28
29
static void *trans_alloc(struct trans_pgd_info *info)
29
30
{
···
42
41
* the temporary mappings we use during restore.
43
42
*/
44
43
set_pte(dst_ptep, pte_mkwrite(pte));
45
-
} else if (debug_pagealloc_enabled() && !pte_none(pte)) {
44
+
} else if ((debug_pagealloc_enabled() ||
45
+
is_kfence_address((void *)addr)) && !pte_none(pte)) {
46
46
/*
47
47
* debug_pagealloc will removed the PTE_VALID bit if
48
48
* the page isn't in use by the resume kernel. It may have
+6
-6
arch/arm64/tools/sysreg
+6
-6
arch/arm64/tools/sysreg
···
2017
2017
EndSysreg
2018
2018
2019
2019
SysregFields HFGxTR_EL2
2020
-
Field 63 nAMIAIR2_EL1
2020
+
Field 63 nAMAIR2_EL1
2021
2021
Field 62 nMAIR2_EL1
2022
2022
Field 61 nS2POR_EL1
2023
2023
Field 60 nPOR_EL1
···
2032
2032
Res0 51
2033
2033
Field 50 nACCDATA_EL1
2034
2034
Field 49 ERXADDR_EL1
2035
-
Field 48 EXRPFGCDN_EL1
2036
-
Field 47 EXPFGCTL_EL1
2037
-
Field 46 EXPFGF_EL1
2035
+
Field 48 ERXPFGCDN_EL1
2036
+
Field 47 ERXPFGCTL_EL1
2037
+
Field 46 ERXPFGF_EL1
2038
2038
Field 45 ERXMISCn_EL1
2039
2039
Field 44 ERXSTATUS_EL1
2040
2040
Field 43 ERXCTLR_EL1
···
2049
2049
Field 34 TPIDRRO_EL0
2050
2050
Field 33 TPIDR_EL1
2051
2051
Field 32 TCR_EL1
2052
-
Field 31 SCTXNUM_EL0
2053
-
Field 30 SCTXNUM_EL1
2052
+
Field 31 SCXTNUM_EL0
2053
+
Field 30 SCXTNUM_EL1
2054
2054
Field 29 SCTLR_EL1
2055
2055
Field 28 REVIDR_EL1
2056
2056
Field 27 PAR_EL1