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drm/msm/mdss: Add a TODO for better managing the MDSS clock power state

There's a small window where the MDP clock could be set to a high rate
(say, from the bootloader) without a corresponding RPM(H)PD vote to
back it up. This is normally not an issue, but could be, if rmmod fails
to shut down the display driver cleanly, and the module is inserted
again, or when the providers' .sync_state has timed out.

Mark a TODO to fix it one day. Linking the relevant discussion below.

Link: https://lore.kernel.org/linux-arm-msm/d5c4eed5-bd87-4156-b178-2d78140ec8a9@oss.qualcomm.com/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/710572/
Link: https://lore.kernel.org/r/20260310-topic-mdss_power_todo-v1-1-59457b8b7486@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

authored by

Konrad Dybcio and committed by
Dmitry Baryshkov d19faa0d 958adefc

+8
+8
drivers/gpu/drm/msm/msm_mdss.c
··· 262 262 icc_set_bw(msm_mdss->reg_bus_path, 0, 263 263 msm_mdss->reg_bus_bw); 264 264 265 + /* 266 + * TODO: 267 + * Previous users (e.g. the bootloader) may have left this clock at a high rate, which 268 + * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a 269 + * risk of brownout, but realistically this path is almost exclusively excercised after the 270 + * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, 271 + * before the RPM(H)PD sync_state is done. 272 + */ 265 273 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 266 274 if (ret) { 267 275 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);